From 556d65af7e480b3799c39da31fe4c9f1e9296064 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Tue, 9 Apr 2013 11:45:05 +0300 Subject: [PATCH] --- yaml --- r: 371469 b: refs/heads/master c: 3a062478308187d4b4d0ef546a16e66852d03489 h: refs/heads/master i: 371467: f36b66fcb06d999d0bdd9d289ad22f1d846a7270 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem_tiling.c | 9 ++++++--- trunk/drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 3ca9e185e45f..e6bed34cf0fd 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fe48d8de34eeaefb2c71dab68ea7c236f06e5877 +refs/heads/master: 3a062478308187d4b4d0ef546a16e66852d03489 diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c index b56185f4babb..537545be69db 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) tile_width = 512; /* check maximum stride & object size */ - if (INTEL_INFO(dev)->gen >= 4) { - /* i965 stores the end address of the gtt mapping in the fence - * reg, so dont bother to check the size */ + /* i965+ stores the end address of the gtt mapping in the fence + * reg, so dont bother to check the size */ + if (INTEL_INFO(dev)->gen >= 7) { + if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) + return false; + } else if (INTEL_INFO(dev)->gen >= 4) { if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) return false; } else { diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 3b9ec9bcd383..e0fc0706e034 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -430,6 +430,7 @@ #define FENCE_REG_SANDYBRIDGE_0 0x100000 #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 /* control register for cpu gtt access */ #define TILECTL 0x101000