From 55df7d36d4034fb990207c8d0af6b6a0783a0758 Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Fri, 12 Aug 2011 08:28:35 +0200 Subject: [PATCH] --- yaml --- r: 264306 b: refs/heads/master c: dd0a028183369cccc0826199a7ccdc850ece289b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/alchemy/devboards/bcsr.c | 4 ++++ trunk/arch/mips/alchemy/devboards/db1200/setup.c | 7 ------- 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index fc307b411309..9895243999f6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b7867f1bfcb76c75d98d35f576fcd9d7759a96fe +refs/heads/master: dd0a028183369cccc0826199a7ccdc850ece289b diff --git a/trunk/arch/mips/alchemy/devboards/bcsr.c b/trunk/arch/mips/alchemy/devboards/bcsr.c index 596ad00e7f05..463d2c4d9441 100644 --- a/trunk/arch/mips/alchemy/devboards/bcsr.c +++ b/trunk/arch/mips/alchemy/devboards/bcsr.c @@ -89,8 +89,12 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d) { unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); + disable_irq_nosync(irq); + for ( ; bisr; bisr &= bisr - 1) generic_handle_irq(bcsr_csc_base + __ffs(bisr)); + + enable_irq(irq); } /* NOTE: both the enable and mask bits must be cleared, otherwise the diff --git a/trunk/arch/mips/alchemy/devboards/db1200/setup.c b/trunk/arch/mips/alchemy/devboards/db1200/setup.c index 1dac4f27d334..4a8980027ecf 100644 --- a/trunk/arch/mips/alchemy/devboards/db1200/setup.c +++ b/trunk/arch/mips/alchemy/devboards/db1200/setup.c @@ -23,13 +23,6 @@ void __init board_setup(void) unsigned long freq0, clksrc, div, pfc; unsigned short whoami; - /* Set Config[OD] (disable overlapping bus transaction): - * This gets rid of a _lot_ of spurious interrupts (especially - * wrt. IDE); but incurs ~10% performance hit in some - * cpu-bound applications. - */ - set_c0_config(1 << 19); - bcsr_init(DB1200_BCSR_PHYS_ADDR, DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);