From 560714f6dcafa5b39f65389d811635a6a8b8d1eb Mon Sep 17 00:00:00 2001
From: Manuel Lauss <mano@roarinelk.homelinux.net>
Date: Wed, 25 Mar 2009 17:49:30 +0100
Subject: [PATCH] --- yaml --- r: 138615 b: refs/heads/master c:
 2f794d099da2f081de2fe19b289a3aa807f735fa h: refs/heads/master i:   138613:
 884f98a723da66251315dda24ae7604ec3d87d21   138611:
 b9294883ef9cd8aba36903436017a0845c9f9a86   138607:
 86e18bf2b455da64bb89de07a3c5a9c14c6e9542 v: v3

---
 [refs]                                | 2 +-
 trunk/arch/mips/include/asm/hazards.h | 4 ++--
 trunk/arch/mips/mm/tlbex.c            | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 739983e2ef40..b018b5d62d1e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 32647e0c1f63eead3e84d52b3edb8bc2f1fa2dd4
+refs/heads/master: 2f794d099da2f081de2fe19b289a3aa807f735fa
diff --git a/trunk/arch/mips/include/asm/hazards.h b/trunk/arch/mips/include/asm/hazards.h
index 134e1fc8f4d6..a12d971db4f9 100644
--- a/trunk/arch/mips/include/asm/hazards.h
+++ b/trunk/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do {									\
 	: "=r" (tmp));							\
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,7 +139,7 @@ do {									\
 } while (0)
 
 #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
-      defined(CONFIG_CPU_R5500)
+      defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c
index 122c9c12e75a..0615b62efd6d 100644
--- a/trunk/arch/mips/mm/tlbex.c
+++ b/trunk/arch/mips/mm/tlbex.c
@@ -292,7 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_R4300:
 	case CPU_5KC:
 	case CPU_TX49XX:
-	case CPU_ALCHEMY:
 	case CPU_PR4450:
 		uasm_i_nop(p);
 		tlbw(p);
@@ -315,6 +314,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_R5500:
 		if (m4kc_tlbp_war())
 			uasm_i_nop(p);
+	case CPU_ALCHEMY:
 		tlbw(p);
 		break;