From 5776864af8f35ef317ec9f7efdc35bd788b313ce Mon Sep 17 00:00:00 2001
From: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Date: Tue, 3 Mar 2009 18:05:51 +0900
Subject: [PATCH] --- yaml --- r: 132211 b: refs/heads/master c:
 a644b2774d41409519bb33a16bd577cb41bb3095 h: refs/heads/master i:   132209:
 077280b7c40cb947fefe82949c812d29248b759f   132207:
 615c39fbd6554f668cb1a5ddf0742233f87db053 v: v3

---
 [refs]                                 | 2 +-
 trunk/arch/mips/include/asm/hazards.h  | 3 ++-
 trunk/arch/mips/include/asm/prefetch.h | 2 +-
 trunk/arch/mips/kernel/cpu-probe.c     | 1 +
 trunk/arch/mips/mm/page.c              | 3 ++-
 trunk/arch/mips/mm/tlbex.c             | 1 +
 6 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 4485e0023b08..549cc8992d27 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c189846ecf900cd6b3ad7d3cef5b45a746ce646b
+refs/heads/master: a644b2774d41409519bb33a16bd577cb41bb3095
diff --git a/trunk/arch/mips/include/asm/hazards.h b/trunk/arch/mips/include/asm/hazards.h
index 43baed16a109..134e1fc8f4d6 100644
--- a/trunk/arch/mips/include/asm/hazards.h
+++ b/trunk/arch/mips/include/asm/hazards.h
@@ -138,7 +138,8 @@ do {									\
 		__instruction_hazard();					\
 } while (0)
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
+      defined(CONFIG_CPU_R5500)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/trunk/arch/mips/include/asm/prefetch.h b/trunk/arch/mips/include/asm/prefetch.h
index 17850834ccb0..a56594f360ee 100644
--- a/trunk/arch/mips/include/asm/prefetch.h
+++ b/trunk/arch/mips/include/asm/prefetch.h
@@ -26,7 +26,7 @@
  * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
  * current versions due to erratum G105.
  *
- * VR7701 only implements the Load prefetch.
+ * VR5500 (including VR5701 and VR7701) only implement load prefetch.
  *
  * Finally MIPS32 and MIPS64 implement all of the following hints.
  */
diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c
index a7162a4484cf..1bdbcad3bb74 100644
--- a/trunk/arch/mips/kernel/cpu-probe.c
+++ b/trunk/arch/mips/kernel/cpu-probe.c
@@ -149,6 +149,7 @@ void __init check_wait(void)
 	case CPU_R4650:
 	case CPU_R4700:
 	case CPU_R5000:
+	case CPU_R5500:
 	case CPU_NEVADA:
 	case CPU_4KC:
 	case CPU_4KEC:
diff --git a/trunk/arch/mips/mm/page.c b/trunk/arch/mips/mm/page.c
index 1417c6494858..48060c635acd 100644
--- a/trunk/arch/mips/mm/page.c
+++ b/trunk/arch/mips/mm/page.c
@@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void)
 		 */
 		cache_line_size = cpu_dcache_line_size();
 		switch (current_cpu_type()) {
+		case CPU_R5500:
 		case CPU_TX49XX:
-			/* TX49 supports only Pref_Load */
+			/* These processors only support the Pref_Load. */
 			pref_bias_copy_load = 256;
 			break;
 
diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c
index 42942038d0fd..f335cf6cdd78 100644
--- a/trunk/arch/mips/mm/tlbex.c
+++ b/trunk/arch/mips/mm/tlbex.c
@@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_BCM4710:
 	case CPU_LOONGSON2:
 	case CPU_CAVIUM_OCTEON:
+	case CPU_R5500:
 		if (m4kc_tlbp_war())
 			uasm_i_nop(p);
 		tlbw(p);