From 5895f4c0109c10bcfcb87c594df11dd8d1b87f9c Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 1 Jun 2009 12:50:33 +0100 Subject: [PATCH] --- yaml --- r: 145529 b: refs/heads/master c: 1946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7 h: refs/heads/master i: 145527: eeed1fe2f9f8e9c0f3e6884798648b28c6bee886 v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/proc-v7.S | 36 +++++++++++++++++++++++++----------- 2 files changed, 26 insertions(+), 12 deletions(-) diff --git a/[refs] b/[refs] index 46d425c2579a..4d8796394b0e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: eb5f4ca9536ba297c98721ecbbdf41ec5b987bd5 +refs/heads/master: 1946d6ef9d7bd4ba97094fe6eb68a9b877bde6b7 diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index 3397f1e64d76..a08d9d2380d3 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -184,23 +184,37 @@ __v7_setup: stmia r12, {r0-r5, r7, r9, r11, lr} bl v7_flush_dcache_all ldmia r12, {r0-r5, r7, r9, r11, lr} + + mrc p15, 0, r0, c0, c0, 0 @ read main ID register + and r10, r0, #0xff000000 @ ARM? + teq r10, #0x41000000 + bne 2f + and r5, r0, #0x00f00000 @ variant + and r6, r0, #0x0000000f @ revision + orr r0, r6, r5, lsr #20-4 @ combine variant and revision + #ifdef CONFIG_ARM_ERRATA_430973 - mrc p15, 0, r10, c1, c0, 1 @ read aux control register - orr r10, r10, #(1 << 6) @ set IBE to 1 - mcr p15, 0, r10, c1, c0, 1 @ write aux control register + teq r5, #0x00100000 @ only present in r1p* + mrceq p15, 0, r10, c1, c0, 1 @ read aux control register + orreq r10, r10, #(1 << 6) @ set IBE to 1 + mcreq p15, 0, r10, c1, c0, 1 @ write aux control register #endif #ifdef CONFIG_ARM_ERRATA_458693 - mrc p15, 0, r10, c1, c0, 1 @ read aux control register - orr r10, r10, #(1 << 5) @ set L1NEON to 1 - orr r10, r10, #(1 << 9) @ set PLDNOP to 1 - mcr p15, 0, r10, c1, c0, 1 @ write aux control register + teq r0, #0x20 @ only present in r2p0 + mrceq p15, 0, r10, c1, c0, 1 @ read aux control register + orreq r10, r10, #(1 << 5) @ set L1NEON to 1 + orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 + mcreq p15, 0, r10, c1, c0, 1 @ write aux control register #endif #ifdef CONFIG_ARM_ERRATA_460075 - mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register - orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit - mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register + teq r0, #0x20 @ only present in r2p0 + mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register + tsteq r10, #1 << 22 + orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit + mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register #endif - mov r10, #0 + +2: mov r10, #0 #ifdef HARVARD_CACHE mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate #endif