From 594e35771cbe1817bf72e333f3b3ac5cc945bf95 Mon Sep 17 00:00:00 2001
From: Dave Jones <davej@redhat.com>
Date: Wed, 14 Oct 2009 16:31:39 -0400
Subject: [PATCH] --- yaml --- r: 174738 b: refs/heads/master c:
 76b1a87b217927f905f4b01c586452b2a1d33913 h: refs/heads/master v: v3

---
 [refs]                      |  2 +-
 trunk/arch/x86/pci/common.c | 18 +++++++++++-------
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/[refs] b/[refs]
index 01dc4da10aea..6d46cd18ff2c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 98e724c791924c0dfc5b1dcf053ed3841cc89c78
+refs/heads/master: 76b1a87b217927f905f4b01c586452b2a1d33913
diff --git a/trunk/arch/x86/pci/common.c b/trunk/arch/x86/pci/common.c
index fbeec31316cf..d2552c68e94d 100644
--- a/trunk/arch/x86/pci/common.c
+++ b/trunk/arch/x86/pci/common.c
@@ -420,15 +420,19 @@ int __init pcibios_init(void)
 	}
 
 	/*
-	 * Assume PCI cacheline size of 32 bytes for all x86s except K7/K8
-	 * and P4. It's also good for 386/486s (which actually have 16)
+	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
+	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
+	 * It's also good for 386/486s (which actually have 16)
 	 * as quite a few PCI devices do not support smaller values.
 	 */
-	pci_dfl_cache_line_size = 32 >> 2;
-	if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
-		pci_dfl_cache_line_size = 64 >> 2;	/* K7 & K8 */
-	else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
-		pci_dfl_cache_line_size = 128 >> 2;	/* P4 */
+	if (c->x86_clflush_size > 0) {
+		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
+		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
+			pci_dfl_cache_line_size << 2);
+	} else {
+ 		pci_dfl_cache_line_size = 32 >> 2;
+		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
+	}
 
 	pcibios_resource_survey();