From 59d85a1260b1c5b5940b3be11f39be77e1a79981 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Fri, 6 Jan 2006 00:11:36 -0800 Subject: [PATCH] --- yaml --- r: 16353 b: refs/heads/master c: db674ed450f113518285f410c93abecd93e71a2f h: refs/heads/master i: 16351: eb75807eeac19a8f8c38f54ae02cc347008e4928 v: v3 --- [refs] | 2 +- trunk/arch/ppc/syslib/mpc52xx_pci.c | 83 ++++++++++++++++++++++++----- 2 files changed, 70 insertions(+), 15 deletions(-) diff --git a/[refs] b/[refs] index 077daf6db412..1937ca6d321b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: dbeb198d9366eb3d3ad64444ceecb5b1d5b5d7ef +refs/heads/master: db674ed450f113518285f410c93abecd93e71a2f diff --git a/trunk/arch/ppc/syslib/mpc52xx_pci.c b/trunk/arch/ppc/syslib/mpc52xx_pci.c index e6cb3e26615a..2c5e6ddaf2c5 100644 --- a/trunk/arch/ppc/syslib/mpc52xx_pci.c +++ b/trunk/arch/ppc/syslib/mpc52xx_pci.c @@ -24,6 +24,12 @@ #include +/* This macro is defined to activate the workaround for the bug + 435 of the MPC5200 (L25R). With it activated, we don't do any + 32 bits configuration access during type-1 cycles */ +#define MPC5200_BUG_435_WORKAROUND + + static int mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) @@ -40,17 +46,39 @@ mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ((bus->number - hose->bus_offset) << 16) | (devfn << 8) | (offset & 0xfc)); + mb(); + +#ifdef MPC5200_BUG_435_WORKAROUND + if (bus->number != hose->bus_offset) { + switch (len) { + case 1: + value = in_8(((u8 __iomem *)hose->cfg_data) + (offset & 3)); + break; + case 2: + value = in_le16(((u16 __iomem *)hose->cfg_data) + ((offset>>1) & 1)); + break; + + default: + value = in_le16((u16 __iomem *)hose->cfg_data) | + (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16); + break; + } + } + else +#endif + { + value = in_le32(hose->cfg_data); - value = in_le32(hose->cfg_data); - - if (len != 4) { - value >>= ((offset & 0x3) << 3); - value &= 0xffffffff >> (32 - (len << 3)); + if (len != 4) { + value >>= ((offset & 0x3) << 3); + value &= 0xffffffff >> (32 - (len << 3)); + } } *val = value; out_be32(hose->cfg_addr, 0); + mb(); return PCIBIOS_SUCCESSFUL; } @@ -71,21 +99,48 @@ mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ((bus->number - hose->bus_offset) << 16) | (devfn << 8) | (offset & 0xfc)); + mb(); + +#ifdef MPC5200_BUG_435_WORKAROUND + if (bus->number != hose->bus_offset) { + switch (len) { + case 1: + out_8(((u8 __iomem *)hose->cfg_data) + + (offset & 3), val); + break; + case 2: + out_le16(((u16 __iomem *)hose->cfg_data) + + ((offset>>1) & 1), val); + break; + + default: + out_le16((u16 __iomem *)hose->cfg_data, + (u16)val); + out_le16(((u16 __iomem *)hose->cfg_data) + 1, + (u16)(val>>16)); + break; + } + } + else +#endif + { + if (len != 4) { + value = in_le32(hose->cfg_data); - if (len != 4) { - value = in_le32(hose->cfg_data); + offset = (offset & 0x3) << 3; + mask = (0xffffffff >> (32 - (len << 3))); + mask <<= offset; - offset = (offset & 0x3) << 3; - mask = (0xffffffff >> (32 - (len << 3))); - mask <<= offset; + value &= ~mask; + val = value | ((val << offset) & mask); + } - value &= ~mask; - val = value | ((val << offset) & mask); + out_le32(hose->cfg_data, val); } - - out_le32(hose->cfg_data, val); + mb(); out_be32(hose->cfg_addr, 0); + mb(); return PCIBIOS_SUCCESSFUL; }