From 5a284ec5ca3e2d43dc8f449e9fdd71bcf2de57ca Mon Sep 17 00:00:00 2001
From: Hong Liu <hong.liu@intel.com>
Date: Mon, 26 Jul 2010 10:06:12 +0100
Subject: [PATCH] --- yaml --- r: 202514 b: refs/heads/master c:
 77e01d6d177f060f466417fa32fc3e1381a73502 h: refs/heads/master v: v3

---
 [refs]                                     | 2 +-
 trunk/drivers/platform/x86/intel_scu_ipc.c | 5 ++++-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index ffb244e18b21..3e9ea6d1939f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 215c330fe92be8d9f74bc292ea085dbe2ace6bf5
+refs/heads/master: 77e01d6d177f060f466417fa32fc3e1381a73502
diff --git a/trunk/drivers/platform/x86/intel_scu_ipc.c b/trunk/drivers/platform/x86/intel_scu_ipc.c
index 84a2d4bfdec8..23b6d46a4b8f 100644
--- a/trunk/drivers/platform/x86/intel_scu_ipc.c
+++ b/trunk/drivers/platform/x86/intel_scu_ipc.c
@@ -148,7 +148,10 @@ static inline int busy_loop(void) /* Wait till scu status is busy */
 			return -ETIMEDOUT;
 		}
 	}
-	return (status >> 1) & 1;
+	if ((status >> 1) & 1)
+		return -EIO;
+
+	return 0;
 }
 
 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */