From 5a357295fdc99529c71d0c6eff68a965fd6dce6d Mon Sep 17 00:00:00 2001 From: Giuseppe CAVALLARO Date: Fri, 17 Sep 2010 03:23:41 +0000 Subject: [PATCH] --- yaml --- r: 214568 b: refs/heads/master c: c629882ac73cab2cd41d9948caeed633fc570fc0 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/net/stmmac/dwmac1000_dma.c | 10 +++++++++- trunk/drivers/net/stmmac/dwmac100_dma.c | 10 +++++++++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 60f9f27731a6..367a14647e28 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06a +refs/heads/master: c629882ac73cab2cd41d9948caeed633fc570fc0 diff --git a/trunk/drivers/net/stmmac/dwmac1000_dma.c b/trunk/drivers/net/stmmac/dwmac1000_dma.c index 2ef5a56370e9..ce6163e39cd5 100644 --- a/trunk/drivers/net/stmmac/dwmac1000_dma.c +++ b/trunk/drivers/net/stmmac/dwmac1000_dma.c @@ -33,10 +33,18 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx) { u32 value = readl(ioaddr + DMA_BUS_MODE); + int limit; + /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); + limit = 15000; + while (limit--) { + if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) + break; + } + if (limit < 0) + return -EBUSY; value = /* DMA_BUS_MODE_FB | */ DMA_BUS_MODE_4PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) | diff --git a/trunk/drivers/net/stmmac/dwmac100_dma.c b/trunk/drivers/net/stmmac/dwmac100_dma.c index c7279d2b946b..96aac93b789b 100644 --- a/trunk/drivers/net/stmmac/dwmac100_dma.c +++ b/trunk/drivers/net/stmmac/dwmac100_dma.c @@ -35,10 +35,18 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx) { u32 value = readl(ioaddr + DMA_BUS_MODE); + int limit; + /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - do {} while ((readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)); + limit = 15000; + while (limit--) { + if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) + break; + } + if (limit < 0) + return -EBUSY; /* Enable Application Access by writing to DMA CSR0 */ writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),