From 5b19b767db315ea91d18778ac0341bee2c34539e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 28 Feb 2013 19:19:44 +0200 Subject: [PATCH] --- yaml --- r: 371169 b: refs/heads/master c: f4808ab86eed9b829c60b02a9ac5e86f06df0bcf h: refs/heads/master i: 371167: dc46c67aa5cc3a442b44122bc039ecae10d42f47 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index d4d5a94119d0..f93812964975 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2bb4629add2e648f1822872cce72f0fe163ce605 +refs/heads/master: f4808ab86eed9b829c60b02a9ac5e86f06df0bcf diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 878e1e3e0667..b4482b22a1ac 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -71,8 +71,24 @@ typedef struct intel_limit intel_limit_t; struct intel_limit { intel_range_t dot, vco, n, m, m1, m2, p, p1; intel_p2_t p2; - bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, - int, int, intel_clock_t *, intel_clock_t *); + /** + * find_pll() - Find the best values for the PLL + * @limit: limits for the PLL + * @crtc: current CRTC + * @target: target frequency in kHz + * @refclk: reference clock frequency in kHz + * @match_clock: if provided, @best_clock P divider must + * match the P divider from @match_clock + * used for LVDS downclocking + * @best_clock: best PLL values found + * + * Returns true on success, false on failure. + */ + bool (*find_pll)(const intel_limit_t *limit, + struct drm_crtc *crtc, + int target, int refclk, + intel_clock_t *match_clock, + intel_clock_t *best_clock); }; /* FDI */