From 5c3ea553e03567d849e8329a249bef9c37fb5cd9 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 11 Dec 2012 10:08:50 +0100 Subject: [PATCH] --- yaml --- r: 347402 b: refs/heads/master c: 69155fd66d340d47cf25eff0099b3e13548ed50c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/clk-imx51-imx53.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index a604d22e1650..58ac873546e2 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3e24b05ba3be5281c3fbf0b126953f5810f9d8ab +refs/heads/master: 69155fd66d340d47cf25eff0099b3e13548ed50c diff --git a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c index e8c0473c7568..579023f59dc1 100644 --- a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c @@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, unsigned long rate_ckih1, unsigned long rate_ckih2) { int i; + u32 val; struct device_node *np; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); @@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable_unprepare(clk[iim_gate]); + /* + * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no + * longer supported. Set to one for better power saving. + * + * The effect of not setting these bits is that MIPI clocks can't be + * enabled without the IPU clock being enabled aswell. + */ + val = readl(MXC_CCM_CCDR); + val |= 1 << 18; + writel(val, MXC_CCM_CCDR); + + val = readl(MXC_CCM_CLPCR); + val |= 1 << 23; + writel(val, MXC_CCM_CLPCR); + return 0; }