From 5c727ab4edabdd89dd0e126f852fc4de7d5c3c02 Mon Sep 17 00:00:00 2001
From: Sonic Zhang <sonic.zhang@analog.com>
Date: Wed, 21 Nov 2007 23:49:52 +0800
Subject: [PATCH] --- yaml --- r: 74127 b: refs/heads/master c:
 e40540b304d5d15c344585c4a7b3116e73add2db h: refs/heads/master i:   74125:
 d398380682277a39224ef948b822d3f89f37404a   74123:
 e879a8327610e0dd48e8e0c09f27737a6f37722b   74119:
 d18fec90fd4fb9e1c1bced86165b3d98531e822c   74111:
 d7e1dacc9d300fcff97010779846347556f68de5 v: v3

---
 [refs]                                |  2 +-
 trunk/arch/blackfin/Kconfig           | 14 ++++++++++++++
 trunk/arch/blackfin/mach-bf548/head.S | 21 +++++++++++++++++++++
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index fedea6c70ec9..9631239cb21c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 28a44d4bd6bdc7d013405bfc2aa7f126d39a7b2b
+refs/heads/master: e40540b304d5d15c344585c4a7b3116e73add2db
diff --git a/trunk/arch/blackfin/Kconfig b/trunk/arch/blackfin/Kconfig
index 2e5ce848513e..3bb25da8b505 100644
--- a/trunk/arch/blackfin/Kconfig
+++ b/trunk/arch/blackfin/Kconfig
@@ -866,6 +866,20 @@ config BANK_3
 	default 0x99B3
 endmenu
 
+config EBIU_MBSCTLVAL
+	hex "EBIU Bank Select Control Register"
+	depends on BF54x
+	default 0
+
+config EBIU_MODEVAL
+	hex "Flash Memory Mode Control Register"
+	depends on BF54x
+	default 1
+
+config EBIU_FCTLVAL
+	hex "Flash Memory Bank Control Register"
+	depends on BF54x
+	default 6
 endmenu
 
 #############################################################################
diff --git a/trunk/arch/blackfin/mach-bf548/head.S b/trunk/arch/blackfin/mach-bf548/head.S
index 3071c243d426..74b34c7f3629 100644
--- a/trunk/arch/blackfin/mach-bf548/head.S
+++ b/trunk/arch/blackfin/mach-bf548/head.S
@@ -158,6 +158,27 @@ ENTRY(__stext)
 	w[p2] = r0;
 	ssync;
 
+	p2.h = hi(EBIU_MBSCTL);
+	p2.l = lo(EBIU_MBSCTL);
+	r0.h = hi(CONFIG_EBIU_MBSCTLVAL);
+	r0.l = lo(CONFIG_EBIU_MBSCTLVAL);
+	[p2] = r0;
+	ssync;
+
+	p2.h = hi(EBIU_MODE);
+	p2.l = lo(EBIU_MODE);
+	r0.h = hi(CONFIG_EBIU_MODEVAL);
+	r0.l = lo(CONFIG_EBIU_MODEVAL);
+	[p2] = r0;
+	ssync;
+
+	p2.h = hi(EBIU_FCTL);
+	p2.l = lo(EBIU_FCTL);
+	r0.h = hi(CONFIG_EBIU_FCTLVAL);
+	r0.l = lo(CONFIG_EBIU_FCTLVAL);
+	[p2] = r0;
+	ssync;
+
 	/* This section keeps the processor in supervisor mode
 	 * during kernel boot.  Switches to user mode at end of boot.
 	 * See page 3-9 of Hardware Reference manual for documentation.