From 5c9a13bfb5e4fa5b81c5ca40d69162e5706dd976 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 18 Mar 2013 11:25:36 +0100 Subject: [PATCH] --- yaml --- r: 361547 b: refs/heads/master c: 9d1a455b0ca1c2c956b4d9ab212864a8695270f1 h: refs/heads/master i: 361545: ea4a807274ff7bcfcb927434245efd096eebcaee 361543: 99d82efa493e04946533f11d8b8c85c53a66f49d v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_dp.c | 12 +++++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index fa1d6f3b873f..9fdbd89276f8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3b4f819d5eac94ba8fe5e8c061f6dabfe8d7b22c +refs/heads/master: 9d1a455b0ca1c2c956b4d9ab212864a8695270f1 diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c index d46dde5a51e3..d7d4afe01341 100644 --- a/trunk/drivers/gpu/drm/i915/intel_dp.c +++ b/trunk/drivers/gpu/drm/i915/intel_dp.c @@ -820,6 +820,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, struct intel_link_m_n m_n; int pipe = intel_crtc->pipe; enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; + int target_clock; /* * Find the lane count in the intel_encoder private @@ -835,13 +836,22 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, } } + target_clock = mode->clock; + for_each_encoder_on_crtc(dev, crtc, intel_encoder) { + if (intel_encoder->type == INTEL_OUTPUT_EDP) { + target_clock = intel_edp_target_clock(intel_encoder, + mode); + break; + } + } + /* * Compute the GMCH and Link ratios. The '3' here is * the number of bytes_per_pixel post-LUT, which we always * set up for 8-bits of R/G/B, or 3 bytes total. */ intel_link_compute_m_n(intel_crtc->bpp, lane_count, - mode->clock, adjusted_mode->clock, &m_n); + target_clock, adjusted_mode->clock, &m_n); if (IS_HASWELL(dev)) { I915_WRITE(PIPE_DATA_M1(cpu_transcoder),