From 5cce18648f3a3abf19eb164b590ee60f2e674f8f Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier.adi@gmail.com>
Date: Wed, 7 Jan 2009 23:14:38 +0800
Subject: [PATCH] --- yaml --- r: 127069 b: refs/heads/master c:
 94106e0fb6b863348a566617ca6bf431c37ddc5e h: refs/heads/master i:   127067:
 d54f6c226d7264524a7bd0fe09ac51210f2452b7 v: v3

---
 [refs]                      | 2 +-
 trunk/arch/blackfin/Kconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 48963b204499..230a602c4074 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1ea9925553caad6ea5068b4652596f149e0be9c3
+refs/heads/master: 94106e0fb6b863348a566617ca6bf431c37ddc5e
diff --git a/trunk/arch/blackfin/Kconfig b/trunk/arch/blackfin/Kconfig
index b8bc5a402fa4..f8edfbe5faed 100644
--- a/trunk/arch/blackfin/Kconfig
+++ b/trunk/arch/blackfin/Kconfig
@@ -866,7 +866,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
 	bool "Cache L2 SRAM"
-	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+	depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
 	default n
 	help
 	  Select to make L2 SRAM cacheable in L1 data and instruction cache.