From 5d58eb2909a692cd117a40b9c56b38dfe3683fca Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 2 Nov 2009 07:52:30 +0000 Subject: [PATCH] --- yaml --- r: 168899 b: refs/heads/master c: d8a2d0e00c0d5a0d55e14b884bff034205015e51 h: refs/heads/master i: 168897: 1f48fabf6a594d9efb433f34f3164ce397c7efd6 168895: ad30c483eb35dcff1a7f3147b5d9fad3f0f1077c v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_hdmi.c | 26 +++++++++++++++++++++---- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index a85fcaa8a2e2..d8a504212216 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4bfe6b6876a036d26a960320f1ab0bbd752c19bf +refs/heads/master: d8a2d0e00c0d5a0d55e14b884bff034205015e51 diff --git a/trunk/drivers/gpu/drm/i915/intel_hdmi.c b/trunk/drivers/gpu/drm/i915/intel_hdmi.c index 663ab6de0b58..c33451aec1bd 100644 --- a/trunk/drivers/gpu/drm/i915/intel_hdmi.c +++ b/trunk/drivers/gpu/drm/i915/intel_hdmi.c @@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; u32 temp; - if (mode != DRM_MODE_DPMS_ON) { - temp = I915_READ(hdmi_priv->sdvox_reg); + temp = I915_READ(hdmi_priv->sdvox_reg); + + /* HW workaround, need to toggle enable bit off and on for 12bpc, but + * we do this anyway which shows more stable in testing. + */ + if (IS_IGDNG(dev)) { I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); + POSTING_READ(hdmi_priv->sdvox_reg); + } + + if (mode != DRM_MODE_DPMS_ON) { + temp &= ~SDVO_ENABLE; } else { - temp = I915_READ(hdmi_priv->sdvox_reg); - I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE); + temp |= SDVO_ENABLE; } + + I915_WRITE(hdmi_priv->sdvox_reg, temp); POSTING_READ(hdmi_priv->sdvox_reg); + + /* HW workaround, need to write this twice for issue that may result + * in first write getting masked. + */ + if (IS_IGDNG(dev)) { + I915_WRITE(hdmi_priv->sdvox_reg, temp); + POSTING_READ(hdmi_priv->sdvox_reg); + } } static void intel_hdmi_save(struct drm_connector *connector)