From 5e78f7b4ba0e78cad87461891ce3bf8118160f84 Mon Sep 17 00:00:00 2001 From: Troy Kisky Date: Thu, 18 Dec 2008 12:36:41 -0700 Subject: [PATCH] --- yaml --- r: 120322 b: refs/heads/master c: 664b4af859d43714fd2a90aa434e454355659d0e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/sound/soc/davinci/davinci-i2s.c | 36 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2f981312c4ab..530c13557c1f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1152a1959f8440db9536f6df758274443f9b5b37 +refs/heads/master: 664b4af859d43714fd2a90aa434e454355659d0e diff --git a/trunk/sound/soc/davinci/davinci-i2s.c b/trunk/sound/soc/davinci/davinci-i2s.c index 81ff5c37ab56..156e3e95d914 100644 --- a/trunk/sound/soc/davinci/davinci-i2s.c +++ b/trunk/sound/soc/davinci/davinci-i2s.c @@ -235,18 +235,45 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_NF: + /* CLKRP Receive clock polarity, + * 1 - sampled on rising edge of CLKR + * valid on rising edge + * CLKXP Transmit clock polarity, + * 1 - clocked on falling edge of CLKX + * valid on rising edge + * FSRP Receive frame sync pol, 0 - active high + * FSXP Transmit frame sync pol, 0 - active high + */ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP, 1); davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); break; case SND_SOC_DAIFMT_NB_IF: + /* CLKRP Receive clock polarity, + * 0 - sampled on falling edge of CLKR + * valid on falling edge + * CLKXP Transmit clock polarity, + * 0 - clocked on rising edge of CLKX + * valid on falling edge + * FSRP Receive frame sync pol, 1 - active low + * FSXP Transmit frame sync pol, 1 - active low + */ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP, 1); davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); break; case SND_SOC_DAIFMT_IB_IF: + /* CLKRP Receive clock polarity, + * 1 - sampled on rising edge of CLKR + * valid on rising edge + * CLKXP Transmit clock polarity, + * 1 - clocked on falling edge of CLKX + * valid on rising edge + * FSRP Receive frame sync pol, 1 - active low + * FSXP Transmit frame sync pol, 1 - active low + */ w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | @@ -255,6 +282,15 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); break; case SND_SOC_DAIFMT_NB_NF: + /* CLKRP Receive clock polarity, + * 0 - sampled on falling edge of CLKR + * valid on falling edge + * CLKXP Transmit clock polarity, + * 0 - clocked on rising edge of CLKX + * valid on falling edge + * FSRP Receive frame sync pol, 0 - active high + * FSXP Transmit frame sync pol, 0 - active high + */ break; default: return -EINVAL;