From 5e8247cd0e9980e713309ccce0103c6edb320e1c Mon Sep 17 00:00:00 2001
From: Magnus Damm <damm@opensource.se>
Date: Thu, 20 Jan 2011 08:11:11 +0000
Subject: [PATCH] --- yaml --- r: 232381 b: refs/heads/master c:
 71fc5099ed50d3699ba003042a721a0bf105369d h: refs/heads/master i:   232379:
 ea9c90e48be0c076cf1cecdb54e997984710b557 v: v3

---
 [refs]                                      |  2 +-
 trunk/arch/arm/mach-shmobile/clock-sh73a0.c | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index ba61a083fbd0..09aff5faa1bc 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2150dace47258722c67f297509bc6171e7b486ad
+refs/heads/master: 71fc5099ed50d3699ba003042a721a0bf105369d
diff --git a/trunk/arch/arm/mach-shmobile/clock-sh73a0.c b/trunk/arch/arm/mach-shmobile/clock-sh73a0.c
index 08fb878ef063..bcaf58a9c153 100644
--- a/trunk/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/trunk/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -118,8 +118,16 @@ static unsigned long pll_recalc(struct clk *clk)
 {
 	unsigned long mult = 1;
 
-	if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+	if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) {
 		mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+		/* handle CFG bit for PLL1 and PLL2 */
+		switch (clk->enable_bit) {
+		case 1:
+		case 2:
+			if (__raw_readl(clk->enable_reg) & (1 << 20))
+				mult *= 2;
+		}
+	}
 
 	return clk->parent->rate * mult;
 }