From 5ec2c57ed248ecd93dface8cad801f9744f86ddc Mon Sep 17 00:00:00 2001 From: Amit Daniel Kachhap Date: Thu, 8 Mar 2012 02:09:06 -0800 Subject: [PATCH] --- yaml --- r: 295864 b: refs/heads/master c: d0341c61a2f641c4f90f4ed4b0d538c9bcb63d18 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-exynos/pm.c | 15 --------------- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/[refs] b/[refs] index 2c67dd2dcd44..f5a079a76d4b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b756a50f7f47e1dee70921399dcb338e4d3bc183 +refs/heads/master: d0341c61a2f641c4f90f4ed4b0d538c9bcb63d18 diff --git a/trunk/arch/arm/mach-exynos/pm.c b/trunk/arch/arm/mach-exynos/pm.c index a4f61a43c7ba..2dd55a191abd 100644 --- a/trunk/arch/arm/mach-exynos/pm.c +++ b/trunk/arch/arm/mach-exynos/pm.c @@ -155,13 +155,6 @@ static struct sleep_save exynos4_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; -static struct sleep_save exynos4_l2cc_save[] = { - SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL), - SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), -}; /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -182,7 +175,6 @@ static void exynos4_pm_prepare(void) u32 tmp; s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save)); - s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save)); s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save)); @@ -386,13 +378,6 @@ static void exynos4_pm_resume(void) scu_enable(S5P_VA_SCU); -#ifdef CONFIG_CACHE_L2X0 - s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); - outer_inv_all(); - /* enable L2X0*/ - writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL); -#endif - early_wakeup: return; }