From 5f168bb1eceeee6f130a3bf5569fd45019152b6a Mon Sep 17 00:00:00 2001
From: Mark Lord <liml@rtr.ca>
Date: Mon, 6 Apr 2009 15:24:57 -0400
Subject: [PATCH] --- yaml --- r: 142682 b: refs/heads/master c:
 2009177329ae565d9e9efd31b399d2f4ed4f0c44 h: refs/heads/master v: v3

---
 [refs]                      |  2 +-
 trunk/drivers/ata/sata_mv.c | 20 +++++++++++++++++++-
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index bf25cda95c9c..e88d1073e1e8 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 65ad7fef10b50b6c06d6165fa847e2d3636b0a66
+refs/heads/master: 2009177329ae565d9e9efd31b399d2f4ed4f0c44
diff --git a/trunk/drivers/ata/sata_mv.c b/trunk/drivers/ata/sata_mv.c
index b0c929d36234..d689fb9ceb96 100644
--- a/trunk/drivers/ata/sata_mv.c
+++ b/trunk/drivers/ata/sata_mv.c
@@ -1296,7 +1296,25 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
 	unsigned int ofs = mv_scr_offset(sc_reg_in);
 
 	if (ofs != 0xffffffffU) {
-		writelfl(val, mv_ap_base(link->ap) + ofs);
+		void __iomem *addr = mv_ap_base(link->ap) + ofs;
+		if (sc_reg_in == SCR_CONTROL) {
+			/*
+			 * Workaround for 88SX60x1 FEr SATA#26:
+			 *
+			 * COMRESETs have to take care not to accidently
+			 * put the drive to sleep when writing SCR_CONTROL.
+			 * Setting bits 12..15 prevents this problem.
+			 *
+			 * So if we see an outbound COMMRESET, set those bits.
+			 * Ditto for the followup write that clears the reset.
+			 *
+			 * The proprietary driver does this for
+			 * all chip versions, and so do we.
+			 */
+			if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
+				val |= 0xf000;
+		}
+		writelfl(val, addr);
 		return 0;
 	} else
 		return -EINVAL;