From 5f1988712b5a4ba10d8a3f9193dfbe2f429dc746 Mon Sep 17 00:00:00 2001
From: "Steven J. Hill" <sjhill@mips.com>
Date: Tue, 28 Aug 2012 23:20:08 -0500
Subject: [PATCH] --- yaml --- r: 332262 b: refs/heads/master c:
 625c0a21700bdb90844d926a1508a17a77e369c9 h: refs/heads/master v: v3

---
 [refs]                     |  2 +-
 trunk/arch/mips/mm/tlbex.c | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index aea6d3588b44..190a8990b2d2 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3234f4466934f08136736790e3de3c6debc71271
+refs/heads/master: 625c0a21700bdb90844d926a1508a17a77e369c9
diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c
index 03eb0ef91580..22ba108d708d 100644
--- a/trunk/arch/mips/mm/tlbex.c
+++ b/trunk/arch/mips/mm/tlbex.c
@@ -449,8 +449,20 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	}
 
 	if (cpu_has_mips_r2) {
-		if (cpu_has_mips_r2_exec_hazard)
+		/*
+		 * The architecture spec says an ehb is required here,
+		 * but a number of cores do not have the hazard and
+		 * using an ehb causes an expensive pipeline stall.
+		 */
+		switch (current_cpu_type()) {
+		case CPU_M14KC:
+		case CPU_74K:
+			break;
+
+		default:
 			uasm_i_ehb(p);
+			break;
+		}
 		tlbw(p);
 		return;
 	}