From 614543d2189a3a230906bfb58713f1a9342e287e Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 13 Jul 2005 19:47:28 +0000
Subject: [PATCH] --- yaml --- r: 11157 b: refs/heads/master c:
 7a0fc58cd9b004672b38537de276f8f188d5e84a h: refs/heads/master i:   11155:
 5ad8fa5a2f63f5782769037c9a073c8fd467d650 v: v3

---
 [refs]                            |  2 +-
 trunk/include/asm-mips/mipsregs.h | 28 ++++++++++++++++++++++++++++
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 2b11a20f7872..25fd92272420 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 55d04dff0fcf5d1c3f0d6edf6df86d82fa4c053b
+refs/heads/master: 7a0fc58cd9b004672b38537de276f8f188d5e84a
diff --git a/trunk/include/asm-mips/mipsregs.h b/trunk/include/asm-mips/mipsregs.h
index 2a56929df9c2..802b1c41ff6a 100644
--- a/trunk/include/asm-mips/mipsregs.h
+++ b/trunk/include/asm-mips/mipsregs.h
@@ -95,6 +95,16 @@
 #define CP0_S1_DERRADDR1  $27
 #define CP0_S1_INTCONTROL $20
 
+/*
+ * Coprocessor 0 Set 2 register names
+ */
+#define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
+
+/*
+ * Coprocessor 0 Set 3 register names
+ */
+#define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
+
 /*
  *  TX39 Series
  */
@@ -984,6 +994,22 @@ do {									\
 #define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
 #define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
 
+/* MIPSR2 */
+#define read_c0_hwrena()	__read_32bit_c0_register($7,0)
+#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
+
+#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
+#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
+
+#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
+#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
+
+#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
+#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
+
+#define read_c0_ebase()		__read_32bit_c0_register($15,1)
+#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+
 /*
  * Macros to access the floating point coprocessor control registers
  */
@@ -1357,6 +1383,8 @@ __BUILD_SET_C0(status)
 __BUILD_SET_C0(cause)
 __BUILD_SET_C0(config)
 __BUILD_SET_C0(intcontrol)
+__BUILD_SET_C0(intctl)
+__BUILD_SET_C0(srsmap)
 
 #endif /* !__ASSEMBLY__ */