From 6149b77c738a5113a57557a6eea1c91335e831ef Mon Sep 17 00:00:00 2001
From: Paul Mundt <lethal@linux-sh.org>
Date: Fri, 25 Apr 2008 13:05:17 +0900
Subject: [PATCH] --- yaml --- r: 96268 b: refs/heads/master c:
 2a6b8148c050941dd61779cb0b49c5c3ea854ebf h: refs/heads/master v: v3

---
 [refs]                               | 2 +-
 trunk/arch/sh/kernel/cpu/sh5/probe.c | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index a62560702403..fd923d7ff39c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 640f7487a919dec4ea98b88a050331f6a4044ea9
+refs/heads/master: 2a6b8148c050941dd61779cb0b49c5c3ea854ebf
diff --git a/trunk/arch/sh/kernel/cpu/sh5/probe.c b/trunk/arch/sh/kernel/cpu/sh5/probe.c
index 31f8cb0f6374..92ad844b5c12 100644
--- a/trunk/arch/sh/kernel/cpu/sh5/probe.c
+++ b/trunk/arch/sh/kernel/cpu/sh5/probe.c
@@ -15,6 +15,7 @@
 #include <linux/string.h>
 #include <asm/processor.h>
 #include <asm/cache.h>
+#include <asm/tlb.h>
 
 int __init detect_cpu_and_cache_system(void)
 {
@@ -67,5 +68,8 @@ int __init detect_cpu_and_cache_system(void)
 	set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
 #endif
 
+	/* Setup some I/D TLB defaults */
+	sh64_tlb_init();
+
 	return 0;
 }