From 61799ec89a6c6e49aaaeccbcbdeb89c2f0900507 Mon Sep 17 00:00:00 2001
From: Thomas Abraham <thomas.ab@samsung.com>
Date: Thu, 13 May 2010 09:27:09 +0900
Subject: [PATCH] --- yaml --- r: 192015 b: refs/heads/master c:
 e4f44f82691e927a2f5eb582793454e052b920c7 h: refs/heads/master i:   192013:
 d9db9281b1707c8cd0425d3498d979feb9374cf6   192011:
 726d1ce55c78482af87d7293deae6650e9b1193e   192007:
 b90c573ba2e88421cecf17c323c325ed2bc5f2b3   191999:
 23a84c08838e8efac1447691f7c686fa692b3858 v: v3

---
 [refs]                              |  2 +-
 trunk/arch/arm/mach-s5p6440/clock.c | 14 ++++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 2d50c33790f8..659412ae0fa0 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9c72d016e2b556e7d8f739b21404f32333fbc5e4
+refs/heads/master: e4f44f82691e927a2f5eb582793454e052b920c7
diff --git a/trunk/arch/arm/mach-s5p6440/clock.c b/trunk/arch/arm/mach-s5p6440/clock.c
index 2c6dd544ff62..bc0458e6d420 100644
--- a/trunk/arch/arm/mach-s5p6440/clock.c
+++ b/trunk/arch/arm/mach-s5p6440/clock.c
@@ -266,6 +266,15 @@ static struct clksrc_clk clk_dout_mpll = {
 	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
 };
 
+static struct clksrc_clk clk_hclk = {
+	.clk	= {
+		.name	= "clk_hclk",
+		.id	= -1,
+		.parent	= &clk_armclk.clk,
+	},
+	.reg_div	= { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
+};
+
 int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
 {
 	unsigned long flags;
@@ -321,7 +330,7 @@ static struct clk init_clocks_disable[] = {
 	{
 		.name		= "nand",
 		.id		= -1,
-		.parent		= &clk_h,
+		.parent		= &clk_hclk.clk,
 		.enable		= s5p6440_mem_ctrl,
 		.ctrlbit	= S5P_CLKCON_MEM0_HCLK_NFCON,
 	}, {
@@ -580,6 +589,7 @@ static struct clksrc_clk *sysclks[] = {
 	&clk_mout_mpll,
 	&clk_dout_mpll,
 	&clk_armclk,
+	&clk_hclk,
 };
 
 void __init_or_cpufreq s5p6440_setup_clocks(void)
@@ -628,7 +638,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
 			print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 
 	fclk = clk_get_rate(&clk_armclk.clk);
-	hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
+	hclk = clk_get_rate(&clk_hclk.clk);
 	pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
 
 	if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {