diff --git a/[refs] b/[refs]
index 96248a7fa7ec..bc907e069510 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5c5d281a93e9816966b6131ccec19519dab0e103
+refs/heads/master: d7be828e03969ea7f922f299acb8daa0d8ce7006
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index f65ca3b2da6f..12de80884b1a 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -85,7 +85,8 @@
 /* hardware minimum and maximum for a single frame's data payload */
 #define TG3_MIN_MTU			60
 #define TG3_MAX_MTU(tp)	\
-	(!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
+	((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
+	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
 
 /* These numbers seem to be hard coded in the NIC firmware somehow.
  * You can't change the ring sizes, but you can change where you place
@@ -204,8 +205,6 @@ static struct pci_device_id tg3_pci_tbl[] = {
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
-	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
@@ -861,7 +860,8 @@ static int tg3_phy_reset(struct tg3 *tp)
 	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 		/* Cannot do read-modify-write on 5401 */
 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
-	} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
 		u32 phy_reg;
 
 		/* Set bit 14 with read-modify-write to preserve other bits */
@@ -873,7 +873,8 @@ static int tg3_phy_reset(struct tg3 *tp)
 	/* Set phy register 0x10 bit 0 to high fifo elasticity to support
 	 * jumbo frames transmission.
 	 */
-	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
+	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
 		u32 phy_reg;
 
 		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -1005,13 +1006,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
 		pci_write_config_word(tp->pdev,
 				      pm + PCI_PM_CTRL,
 				      power_control);
-		udelay(100);	/* Delay after power state change */
-
-		/* Switch out of Vaux if it is not a LOM */
-		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
-			tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
-			udelay(100);
-		}
+		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
+		udelay(100);
 
 		return 0;
 
@@ -1072,7 +1068,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
 			mac_mode = MAC_MODE_PORT_MODE_TBI;
 		}
 
-		if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
 			tw32(MAC_LED_CTRL, tp->led_ctrl);
 
 		if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -1099,7 +1095,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
 		     CLOCK_CTRL_ALTCLK |
 		     CLOCK_CTRL_PWRDOWN_PLL133);
 		udelay(40);
-	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+	} else if (!((GET_ASIC_REV(tp->pci_chip_rev_id) == 5750) &&
 		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
 		u32 newbits1, newbits2;
 
@@ -1156,7 +1152,6 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
 
 	/* Finally, set the new power state. */
 	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
-	udelay(100);	/* Delay after power state change */
 
 	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
 
@@ -2907,43 +2902,6 @@ static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp)
 	return work_exists;
 }
 
-/* MSI ISR - No need to check for interrupt sharing and no need to
- * flush status block and interrupt mailbox. PCI ordering rules
- * guarantee that MSI will arrive after the status block.
- */
-static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
-{
-	struct net_device *dev = dev_id;
-	struct tg3 *tp = netdev_priv(dev);
-	struct tg3_hw_status *sblk = tp->hw_status;
-	unsigned long flags;
-
-	spin_lock_irqsave(&tp->lock, flags);
-
-	/*
-	 * writing any value to intr-mbox-0 clears PCI INTA# and
-	 * chip-internal interrupt pending events.
-	 * writing non-zero to intr-mbox-0 additional tells the
-	 * NIC to stop sending us irqs, engaging "in-intr-handler"
-	 * event coalescing.
-	 */
-	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
-	sblk->status &= ~SD_STATUS_UPDATED;
-
-	if (likely(tg3_has_work(dev, tp)))
-		netif_rx_schedule(dev);		/* schedule NAPI poll */
-	else {
-		/* no work, re-enable interrupts
-		 */
-		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
-			     0x00000000);
-	}
-
-	spin_unlock_irqrestore(&tp->lock, flags);
-
-	return IRQ_RETVAL(1);
-}
-
 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct net_device *dev = dev_id;
@@ -2996,31 +2954,13 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	return IRQ_RETVAL(handled);
 }
 
-/* ISR for interrupt test */
-static irqreturn_t tg3_test_isr(int irq, void *dev_id,
-		struct pt_regs *regs)
-{
-	struct net_device *dev = dev_id;
-	struct tg3 *tp = netdev_priv(dev);
-	struct tg3_hw_status *sblk = tp->hw_status;
-
-	if (sblk->status & SD_STATUS_UPDATED) {
-		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
-			     0x00000001);
-		return IRQ_RETVAL(1);
-	}
-	return IRQ_RETVAL(0);
-}
-
 static int tg3_init_hw(struct tg3 *);
 static int tg3_halt(struct tg3 *);
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void tg3_poll_controller(struct net_device *dev)
 {
-	struct tg3 *tp = netdev_priv(dev);
-
-	tg3_interrupt(tp->pdev->irq, dev, NULL);
+	tg3_interrupt(dev->irq, dev, NULL);
 }
 #endif
 
@@ -3786,28 +3726,6 @@ static void tg3_nvram_unlock(struct tg3 *tp)
 		tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
 }
 
-/* tp->lock is held. */
-static void tg3_enable_nvram_access(struct tg3 *tp)
-{
-	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
-		u32 nvaccess = tr32(NVRAM_ACCESS);
-
-		tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-	}
-}
-
-/* tp->lock is held. */
-static void tg3_disable_nvram_access(struct tg3 *tp)
-{
-	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
-		u32 nvaccess = tr32(NVRAM_ACCESS);
-
-		tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-	}
-}
-
 /* tp->lock is held. */
 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
 {
@@ -4049,7 +3967,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 	}
@@ -5123,7 +5041,7 @@ static int tg3_reset_hw(struct tg3 *tp)
 	tw32(GRC_MISC_CFG, val);
 
 	/* Initialize MBUF/DESC pool. */
-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 		/* Do nothing.  */
 	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
 		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -5320,8 +5238,6 @@ static int tg3_reset_hw(struct tg3 *tp)
 		      RDMAC_MODE_LNGREAD_ENAB);
 	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
 		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
-
-	/* If statement applies to 5705 and 5750 PCI devices only */
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
 	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
 	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
@@ -5335,9 +5251,6 @@ static int tg3_reset_hw(struct tg3 *tp)
 		}
 	}
 
-	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
-		rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
-
 #if TG3_TSO_SUPPORT != 0
 	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
 		rdmac_mode |= (1 << 27);
@@ -5419,28 +5332,10 @@ static int tg3_reset_hw(struct tg3 *tp)
 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
 	udelay(40);
 
-	/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
-	 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
-	 * register to preserve the GPIO settings for LOMs. The GPIOs,
-	 * whether used as inputs or outputs, are set by boot code after
-	 * reset.
-	 */
-	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-		u32 gpio_mask;
-
-		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
-			    GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
-
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
-			gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
-				     GRC_LCLCTRL_GPIO_OUTPUT3;
-
-		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
-
-		/* GPIO1 must be driven high for eeprom write protect */
+	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
 		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
 				       GRC_LCLCTRL_GPIO_OUTPUT1);
-	}
 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
 	udelay(100);
 
@@ -5458,7 +5353,6 @@ static int tg3_reset_hw(struct tg3 *tp)
 	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
 	       WDMAC_MODE_LNGREAD_ENAB);
 
-	/* If statement applies to 5705 and 5750 PCI devices only */
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
 	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
@@ -5812,118 +5706,6 @@ static void tg3_timer(unsigned long __opaque)
 	add_timer(&tp->timer);
 }
 
-static int tg3_test_interrupt(struct tg3 *tp)
-{
-	struct net_device *dev = tp->dev;
-	int err, i;
-	u32 int_mbox = 0;
-
-	tg3_disable_ints(tp);
-
-	free_irq(tp->pdev->irq, dev);
-
-	err = request_irq(tp->pdev->irq, tg3_test_isr,
-			  SA_SHIRQ, dev->name, dev);
-	if (err)
-		return err;
-
-	tg3_enable_ints(tp);
-
-	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
-	       HOSTCC_MODE_NOW);
-
-	for (i = 0; i < 5; i++) {
-		int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
-		if (int_mbox != 0)
-			break;
-		msleep(10);
-	}
-
-	tg3_disable_ints(tp);
-
-	free_irq(tp->pdev->irq, dev);
-	
-	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
-		err = request_irq(tp->pdev->irq, tg3_msi,
-				  0, dev->name, dev);
-	else
-		err = request_irq(tp->pdev->irq, tg3_interrupt,
-				  SA_SHIRQ, dev->name, dev);
-
-	if (err)
-		return err;
-
-	if (int_mbox != 0)
-		return 0;
-
-	return -EIO;
-}
-
-/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
- * successfully restored
- */
-static int tg3_test_msi(struct tg3 *tp)
-{
-	struct net_device *dev = tp->dev;
-	int err;
-	u16 pci_cmd;
-
-	if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
-		return 0;
-
-	/* Turn off SERR reporting in case MSI terminates with Master
-	 * Abort.
-	 */
-	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
-	pci_write_config_word(tp->pdev, PCI_COMMAND,
-			      pci_cmd & ~PCI_COMMAND_SERR);
-
-	err = tg3_test_interrupt(tp);
-
-	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
-
-	if (!err)
-		return 0;
-
-	/* other failures */
-	if (err != -EIO)
-		return err;
-
-	/* MSI test failed, go back to INTx mode */
-	printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
-	       "switching to INTx mode. Please report this failure to "
-	       "the PCI maintainer and include system chipset information.\n",
-		       tp->dev->name);
-
-	free_irq(tp->pdev->irq, dev);
-	pci_disable_msi(tp->pdev);
-
-	tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
-
-	err = request_irq(tp->pdev->irq, tg3_interrupt,
-			  SA_SHIRQ, dev->name, dev);
-
-	if (err)
-		return err;
-
-	/* Need to reset the chip because the MSI cycle may have terminated
-	 * with Master Abort.
-	 */
-	spin_lock_irq(&tp->lock);
-	spin_lock(&tp->tx_lock);
-
-	tg3_halt(tp);
-	err = tg3_init_hw(tp);
-
-	spin_unlock(&tp->tx_lock);
-	spin_unlock_irq(&tp->lock);
-
-	if (err)
-		free_irq(tp->pdev->irq, dev);
-
-	return err;
-}
-
 static int tg3_open(struct net_device *dev)
 {
 	struct tg3 *tp = netdev_priv(dev);
@@ -5945,29 +5727,10 @@ static int tg3_open(struct net_device *dev)
 	if (err)
 		return err;
 
-	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
-	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
-		if (pci_enable_msi(tp->pdev) == 0) {
-			u32 msi_mode;
-
-			msi_mode = tr32(MSGINT_MODE);
-			tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
-			tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
-		}
-	}
-	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
-		err = request_irq(tp->pdev->irq, tg3_msi,
-				  0, dev->name, dev);
-	else
-		err = request_irq(tp->pdev->irq, tg3_interrupt,
-				  SA_SHIRQ, dev->name, dev);
+	err = request_irq(dev->irq, tg3_interrupt,
+			  SA_SHIRQ, dev->name, dev);
 
 	if (err) {
-		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-			pci_disable_msi(tp->pdev);
-			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
-		}
 		tg3_free_consistent(tp);
 		return err;
 	}
@@ -5988,47 +5751,23 @@ static int tg3_open(struct net_device *dev)
 		tp->timer.expires = jiffies + tp->timer_offset;
 		tp->timer.data = (unsigned long) tp;
 		tp->timer.function = tg3_timer;
+		add_timer(&tp->timer);
+
+		tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
 	}
 
 	spin_unlock(&tp->tx_lock);
 	spin_unlock_irq(&tp->lock);
 
 	if (err) {
-		free_irq(tp->pdev->irq, dev);
-		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-			pci_disable_msi(tp->pdev);
-			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
-		}
+		free_irq(dev->irq, dev);
 		tg3_free_consistent(tp);
 		return err;
 	}
 
-	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-		err = tg3_test_msi(tp);
-		if (err) {
-			spin_lock_irq(&tp->lock);
-			spin_lock(&tp->tx_lock);
-
-			if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-				pci_disable_msi(tp->pdev);
-				tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
-			}
-			tg3_halt(tp);
-			tg3_free_rings(tp);
-			tg3_free_consistent(tp);
-
-			spin_unlock(&tp->tx_lock);
-			spin_unlock_irq(&tp->lock);
-
-			return err;
-		}
-	}
-
 	spin_lock_irq(&tp->lock);
 	spin_lock(&tp->tx_lock);
 
-	add_timer(&tp->timer);
-	tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
 	tg3_enable_ints(tp);
 
 	spin_unlock(&tp->tx_lock);
@@ -6296,11 +6035,7 @@ static int tg3_close(struct net_device *dev)
 	spin_unlock(&tp->tx_lock);
 	spin_unlock_irq(&tp->lock);
 
-	free_irq(tp->pdev->irq, dev);
-	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
-		pci_disable_msi(tp->pdev);
-		tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
-	}
+	free_irq(dev->irq, dev);
 
 	memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
 	       sizeof(tp->net_stats_prev));
@@ -6774,12 +6509,10 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
 		start = cpu_to_le32(start);
 		len += b_offset;
 		offset &= ~3;
-		if (len < 4)
-			len = 4;
 	}
 
 	odd_len = 0;
-	if (len & 3) {
+	if ((len & 3) && ((len > 4) || (b_offset == 0))) {
 		/* adjustments to end on required 4 byte boundary */
 		odd_len = 1;
 		len = (len + 3) & ~3;
@@ -7334,67 +7067,6 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
 	}
 }
 
-static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
-{
-	u32 nvcfg1;
-
-	nvcfg1 = tr32(NVRAM_CFG1);
-
-	/* NVRAM protection for TPM */
-	if (nvcfg1 & (1 << 27))
-		tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
-
-	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
-		case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
-		case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
-			tp->nvram_jedecnum = JEDEC_ATMEL;
-			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-			break;
-		case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
-			tp->nvram_jedecnum = JEDEC_ATMEL;
-			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-			tp->tg3_flags2 |= TG3_FLG2_FLASH;
-			break;
-		case FLASH_5752VENDOR_ST_M45PE10:
-		case FLASH_5752VENDOR_ST_M45PE20:
-		case FLASH_5752VENDOR_ST_M45PE40:
-			tp->nvram_jedecnum = JEDEC_ST;
-			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
-			tp->tg3_flags2 |= TG3_FLG2_FLASH;
-			break;
-	}
-
-	if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
-		switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
-			case FLASH_5752PAGE_SIZE_256:
-				tp->nvram_pagesize = 256;
-				break;
-			case FLASH_5752PAGE_SIZE_512:
-				tp->nvram_pagesize = 512;
-				break;
-			case FLASH_5752PAGE_SIZE_1K:
-				tp->nvram_pagesize = 1024;
-				break;
-			case FLASH_5752PAGE_SIZE_2K:
-				tp->nvram_pagesize = 2048;
-				break;
-			case FLASH_5752PAGE_SIZE_4K:
-				tp->nvram_pagesize = 4096;
-				break;
-			case FLASH_5752PAGE_SIZE_264:
-				tp->nvram_pagesize = 264;
-				break;
-		}
-	}
-	else {
-		/* For eeprom, set pagesize to maximum eeprom size */
-		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
-
-		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
-		tw32(NVRAM_CFG1, nvcfg1);
-	}
-}
-
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void __devinit tg3_nvram_init(struct tg3 *tp)
 {
@@ -7421,16 +7093,20 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 		tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-		tg3_enable_nvram_access(tp);
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+			u32 nvaccess = tr32(NVRAM_ACCESS);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
-			tg3_get_5752_nvram_info(tp);
-		else
-			tg3_get_nvram_info(tp);
+			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+		}
 
+		tg3_get_nvram_info(tp);
 		tg3_get_nvram_size(tp);
 
-		tg3_disable_nvram_access(tp);
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+			u32 nvaccess = tr32(NVRAM_ACCESS);
+
+			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+		}
 
 	} else {
 		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -7519,7 +7195,11 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
 
 	tg3_nvram_lock(tp);
 
-	tg3_enable_nvram_access(tp);
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		u32 nvaccess = tr32(NVRAM_ACCESS);
+
+		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+	}
 
 	tw32(NVRAM_ADDR, offset);
 	ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
@@ -7530,7 +7210,11 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
 
 	tg3_nvram_unlock(tp);
 
-	tg3_disable_nvram_access(tp);
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		u32 nvaccess = tr32(NVRAM_ACCESS);
+
+		tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+	}
 
 	return ret;
 }
@@ -7593,7 +7277,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
 
 	while (len) {
 		int j;
-		u32 phy_addr, page_off, size;
+		u32 phy_addr, page_off, size, nvaccess;
 
 		phy_addr = offset & ~pagemask;
 	
@@ -7616,7 +7300,8 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
 
 		offset = offset + (pagesize - page_off);
 
-		tg3_enable_nvram_access(tp);
+		nvaccess = tr32(NVRAM_ACCESS);
+		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
 
 		/*
 		 * Before we can erase the flash page, we need
@@ -7740,8 +7425,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 	}
 
 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
-		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
+		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+		       GRC_LCLCTRL_GPIO_OE1);
 		udelay(40);
 	}
 
@@ -7753,10 +7438,13 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 
 		tg3_nvram_lock(tp);
 
-		tg3_enable_nvram_access(tp);
-		if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
-		    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+			u32 nvaccess = tr32(NVRAM_ACCESS);
+
+			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+
 			tw32(NVRAM_WRITE1, 0x406);
+		}
 
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
@@ -7775,12 +7463,17 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-		tg3_disable_nvram_access(tp);
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+			u32 nvaccess = tr32(NVRAM_ACCESS);
+
+			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+		}
 		tg3_nvram_unlock(tp);
 	}
 
 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
+		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
+		       GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OUTPUT1);
 		udelay(40);
 	}
 
@@ -7844,27 +7537,21 @@ static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
 	return NULL;
 }
 
-/* Since this function may be called in D3-hot power state during
- * tg3_init_one(), only config cycles are allowed.
- */
-static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
+static int __devinit tg3_phy_probe(struct tg3 *tp)
 {
+	u32 eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
+	u32 hw_phy_id, hw_phy_id_masked;
 	u32 val;
-
-	/* Make sure register accesses (indirect or otherwise)
-	 * will function correctly.
-	 */
-	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
-			       tp->misc_host_ctrl);
+	int eeprom_signature_found, eeprom_phy_serdes, err;
 
 	tp->phy_id = PHY_ID_INVALID;
-	tp->led_ctrl = LED_CTRL_MODE_PHY_1;
-
+	eeprom_phy_id = PHY_ID_INVALID;
+	eeprom_phy_serdes = 0;
+	eeprom_signature_found = 0;
 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
 	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
 		u32 nic_cfg, led_cfg;
-		u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
-		int eeprom_phy_serdes = 0;
+		u32 nic_phy_id, ver, cfg2 = 0;
 
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		tp->nic_sram_data_cfg = nic_cfg;
@@ -7877,6 +7564,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 		    (ver > 0) && (ver < 0x100))
 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
 
+		eeprom_signature_found = 1;
+
 		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
 		    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
 			eeprom_phy_serdes = 1;
@@ -7892,14 +7581,10 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 		} else
 			eeprom_phy_id = 0;
 
-		tp->phy_id = eeprom_phy_id;
-		if (eeprom_phy_serdes)
-			tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
-
-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
 				    SHASTA_EXT_LED_MODE_MASK);
-		else
+		} else
 			led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
 
 		switch (led_cfg) {
@@ -7949,7 +7634,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
@@ -7963,13 +7648,6 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 		if (cfg2 & (1 << 18))
 			tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
 	}
-}
-
-static int __devinit tg3_phy_probe(struct tg3 *tp)
-{
-	u32 hw_phy_id_1, hw_phy_id_2;
-	u32 hw_phy_id, hw_phy_id_masked;
-	int err;
 
 	/* Reading the PHY ID register can conflict with ASF
 	 * firwmare access to the PHY hardware.
@@ -7998,10 +7676,10 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
 		if (hw_phy_id_masked == PHY_ID_BCM8002)
 			tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
 	} else {
-		if (tp->phy_id != PHY_ID_INVALID) {
-			/* Do nothing, phy ID already set up in
-			 * tg3_get_eeprom_hw_cfg().
-			 */
+		if (eeprom_signature_found) {
+			tp->phy_id = eeprom_phy_id;
+			if (eeprom_phy_serdes)
+				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
 		} else {
 			struct subsys_tbl_ent *p;
 
@@ -8072,6 +7750,9 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
 		err = tg3_init_5401phy_dsp(tp);
 	}
 
+	if (!eeprom_signature_found)
+		tp->led_ctrl = LED_CTRL_MODE_PHY_1;
+
 	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
 		tp->link_config.advertising =
 			(ADVERTISED_1000baseT_Half |
@@ -8236,12 +7917,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 	tp->pci_chip_rev_id = (misc_ctrl_reg >>
 			       MISC_HOST_CTRL_CHIPREV_SHIFT);
 
-	/* Wrong chip ID in 5752 A0. This code can be removed later
-	 * as A0 is not in production.
-	 */
-	if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
-		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
-
 	/* Initialize misc host control in PCI block. */
 	tp->misc_host_ctrl |= (misc_ctrl_reg &
 			       MISC_HOST_CTRL_CHIPREV);
@@ -8256,15 +7931,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 	tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
 	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
-		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
-
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
-	    (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
 		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
 
-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
 
 	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
@@ -8342,31 +8013,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
 	}
 
-	/* Get eeprom hw config before calling tg3_set_power_state().
-	 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
-	 * determined before calling tg3_set_power_state() so that
-	 * we know whether or not to switch out of Vaux power.
-	 * When the flag is set, it means that GPIO1 is used for eeprom
-	 * write protect and also implies that it is a LOM where GPIOs
-	 * are not used to switch power.
-	 */ 
-	tg3_get_eeprom_hw_cfg(tp);
-
-	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
-	 * GPIO1 driven high will bring 5700's external PHY out of reset.
-	 * It is also used as eeprom write protect on LOMs.
-	 */
-	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
-	    (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
-		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
-				       GRC_LCLCTRL_GPIO_OUTPUT1);
-	/* Unused GPIO3 must be driven as output on 5752 because there
-	 * are no pull-up resistors on unused GPIO pins.
-	 */
-	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
-		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
-
 	/* Force the chip into D0. */
 	err = tg3_set_power_state(tp, 0);
 	if (err) {
@@ -8419,7 +8065,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
 		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
 
-	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
 
 	/* Only 5701 and later support tagged irq status mode.
@@ -8981,7 +8628,6 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
 	case PHY_ID_BCM5704:	return "5704";
 	case PHY_ID_BCM5705:	return "5705";
 	case PHY_ID_BCM5750:	return "5750";
-	case PHY_ID_BCM5752:	return "5752";
 	case PHY_ID_BCM8002:	return "8002/serdes";
 	case 0:			return "serdes";
 	default:		return "unknown";
diff --git a/trunk/drivers/net/tg3.h b/trunk/drivers/net/tg3.h
index 8de6f21037ba..d48887d90325 100644
--- a/trunk/drivers/net/tg3.h
+++ b/trunk/drivers/net/tg3.h
@@ -125,9 +125,6 @@
 #define  CHIPREV_ID_5750_A0		 0x4000
 #define  CHIPREV_ID_5750_A1		 0x4001
 #define  CHIPREV_ID_5750_A3		 0x4003
-#define  CHIPREV_ID_5752_A0_HW		 0x5000
-#define  CHIPREV_ID_5752_A0		 0x6000
-#define  CHIPREV_ID_5752_A1		 0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700			 0x07
 #define   ASIC_REV_5701			 0x00
@@ -135,7 +132,6 @@
 #define   ASIC_REV_5704			 0x02
 #define   ASIC_REV_5705			 0x03
 #define   ASIC_REV_5750			 0x04
-#define   ASIC_REV_5752			 0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX		 0x70
 #define   CHIPREV_5700_BX		 0x71
@@ -1311,9 +1307,6 @@
 #define  GRC_LCLCTRL_CLEARINT		0x00000002
 #define  GRC_LCLCTRL_SETINT		0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008
-#define  GRC_LCLCTRL_GPIO_INPUT3	0x00000020
-#define  GRC_LCLCTRL_GPIO_OE3		0x00000040
-#define  GRC_LCLCTRL_GPIO_OUTPUT3	0x00000080
 #define  GRC_LCLCTRL_GPIO_INPUT0	0x00000100
 #define  GRC_LCLCTRL_GPIO_INPUT1	0x00000200
 #define  GRC_LCLCTRL_GPIO_INPUT2	0x00000400
@@ -1399,20 +1392,6 @@
 #define  FLASH_VENDOR_SAIFUN		 0x01000003
 #define  FLASH_VENDOR_SST_SMALL		 0x00000001
 #define  FLASH_VENDOR_SST_LARGE		 0x02000001
-#define  NVRAM_CFG1_5752VENDOR_MASK	 0x03c00003
-#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ	 0x00000000
-#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ	 0x02000000
-#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED	 0x02000003
-#define  FLASH_5752VENDOR_ST_M45PE10	 0x02400000
-#define  FLASH_5752VENDOR_ST_M45PE20	 0x02400002
-#define  FLASH_5752VENDOR_ST_M45PE40	 0x02400001
-#define  NVRAM_CFG1_5752PAGE_SIZE_MASK	 0x70000000
-#define  FLASH_5752PAGE_SIZE_256	 0x00000000
-#define  FLASH_5752PAGE_SIZE_512	 0x10000000
-#define  FLASH_5752PAGE_SIZE_1K		 0x20000000
-#define  FLASH_5752PAGE_SIZE_2K		 0x30000000
-#define  FLASH_5752PAGE_SIZE_4K		 0x40000000
-#define  FLASH_5752PAGE_SIZE_264	 0x50000000
 #define NVRAM_CFG2			0x00007018
 #define NVRAM_CFG3			0x0000701c
 #define NVRAM_SWARB			0x00007020
@@ -2121,9 +2100,6 @@ struct tg3 {
 #define TG3_FLG2_HW_TSO			0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS	0x00020000
 #define TG3_FLG2_5705_PLUS		0x00040000
-#define TG3_FLG2_5750_PLUS		0x00080000
-#define TG3_FLG2_PROTECTED_NVRAM	0x00100000
-#define TG3_FLG2_USING_MSI		0x00200000
 
 	u32				split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ		3
@@ -2169,7 +2145,6 @@ struct tg3 {
 #define PHY_ID_BCM5704			0x60008190
 #define PHY_ID_BCM5705			0x600081a0
 #define PHY_ID_BCM5750			0x60008180
-#define PHY_ID_BCM5752			0x60008100
 #define PHY_ID_BCM8002			0x60010140
 #define PHY_ID_INVALID			0xffffffff
 #define PHY_ID_REV_MASK			0x0000000f
diff --git a/trunk/include/asm-sparc64/pgtable.h b/trunk/include/asm-sparc64/pgtable.h
index af9bf175a223..ae2cd5b09a7c 100644
--- a/trunk/include/asm-sparc64/pgtable.h
+++ b/trunk/include/asm-sparc64/pgtable.h
@@ -416,6 +416,11 @@ extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
 			       unsigned long pfn,
 			       unsigned long size, pgprot_t prot);
 
+/* Clear virtual and physical cachability, set side-effect bit.  */
+#define pgprot_noncached(prot) \
+	(__pgprot((pgprot_val(prot) & ~(_PAGE_CP | _PAGE_CV)) | \
+	 _PAGE_E))
+
 /*
  * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
  * its high 4 bits.  These macros/functions put it there or get it from there.
diff --git a/trunk/include/linux/pci_ids.h b/trunk/include/linux/pci_ids.h
index 6a1897481942..f1f75fde8cd4 100644
--- a/trunk/include/linux/pci_ids.h
+++ b/trunk/include/linux/pci_ids.h
@@ -2062,7 +2062,6 @@
 #define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
 
 #define PCI_VENDOR_ID_BROADCOM		0x14e4
-#define PCI_DEVICE_ID_TIGON3_5752	0x1600
 #define PCI_DEVICE_ID_TIGON3_5700	0x1644
 #define PCI_DEVICE_ID_TIGON3_5701	0x1645
 #define PCI_DEVICE_ID_TIGON3_5702	0x1646
diff --git a/trunk/include/net/ax25.h b/trunk/include/net/ax25.h
index 875edbba396d..fb95ecb6fe03 100644
--- a/trunk/include/net/ax25.h
+++ b/trunk/include/net/ax25.h
@@ -305,7 +305,7 @@ extern ax25_cb *ax25_send_frame(struct sk_buff *, int, ax25_address *, ax25_addr
 extern void ax25_output(ax25_cb *, int, struct sk_buff *);
 extern void ax25_kick(ax25_cb *);
 extern void ax25_transmit_buffer(ax25_cb *, struct sk_buff *, int);
-extern void ax25_queue_xmit(struct sk_buff *skb, struct net_device *dev);
+extern void ax25_queue_xmit(struct sk_buff *);
 extern int  ax25_check_iframes_acked(ax25_cb *, unsigned short);
 
 /* ax25_route.c */
diff --git a/trunk/net/atm/resources.c b/trunk/net/atm/resources.c
index a57a9268bd24..33f1685dbb77 100644
--- a/trunk/net/atm/resources.c
+++ b/trunk/net/atm/resources.c
@@ -44,6 +44,11 @@ static struct atm_dev *__alloc_atm_dev(const char *type)
 	return dev;
 }
 
+static void __free_atm_dev(struct atm_dev *dev)
+{
+	kfree(dev);
+}
+
 static struct atm_dev *__atm_dev_lookup(int number)
 {
 	struct atm_dev *dev;
@@ -85,7 +90,7 @@ struct atm_dev *atm_dev_register(const char *type, const struct atmdev_ops *ops,
 		if ((inuse = __atm_dev_lookup(number))) {
 			atm_dev_put(inuse);
 			spin_unlock(&atm_dev_lock);
-			kfree(dev);
+			__free_atm_dev(dev);
 			return NULL;
 		}
 		dev->number = number;
@@ -114,7 +119,7 @@ struct atm_dev *atm_dev_register(const char *type, const struct atmdev_ops *ops,
 		spin_lock(&atm_dev_lock);
 		list_del(&dev->dev_list);
 		spin_unlock(&atm_dev_lock);
-		kfree(dev);
+		__free_atm_dev(dev);
 		return NULL;
 	}
 
@@ -143,7 +148,7 @@ void atm_dev_deregister(struct atm_dev *dev)
                 }
         }
 
-	kfree(dev);
+	__free_atm_dev(dev);
 }
 
 void shutdown_atm_dev(struct atm_dev *dev)
diff --git a/trunk/net/atm/signaling.c b/trunk/net/atm/signaling.c
index f7c449ac1800..6ff803154c04 100644
--- a/trunk/net/atm/signaling.c
+++ b/trunk/net/atm/signaling.c
@@ -134,7 +134,6 @@ static int sigd_send(struct atm_vcc *vcc,struct sk_buff *skb)
 			break;
 		case as_indicate:
 			vcc = *(struct atm_vcc **) &msg->listen_vcc;
-			sk = sk_atm(vcc);
 			DPRINTK("as_indicate!!!\n");
 			lock_sock(sk);
 			if (sk_acceptq_is_full(sk)) {
diff --git a/trunk/net/ax25/af_ax25.c b/trunk/net/ax25/af_ax25.c
index 707097deac3d..33b1a3763027 100644
--- a/trunk/net/ax25/af_ax25.c
+++ b/trunk/net/ax25/af_ax25.c
@@ -1587,7 +1587,9 @@ static int ax25_sendmsg(struct kiocb *iocb, struct socket *sock,
 	*asmptr = AX25_UI;
 
 	/* Datagram frames go straight out of the door as UI */
-	ax25_queue_xmit(skb, ax25->ax25_dev->dev);
+	skb->dev = ax25->ax25_dev->dev;
+
+	ax25_queue_xmit(skb);
 
 	err = len;
 
diff --git a/trunk/net/ax25/ax25_ip.c b/trunk/net/ax25/ax25_ip.c
index bba0173e2d65..04d711344d55 100644
--- a/trunk/net/ax25/ax25_ip.c
+++ b/trunk/net/ax25/ax25_ip.c
@@ -199,7 +199,9 @@ int ax25_rebuild_header(struct sk_buff *skb)
 		skb = ourskb;
 	}
 
-	ax25_queue_xmit(skb, dev);
+	skb->dev      = dev;
+
+	ax25_queue_xmit(skb);
 
 put:
 	ax25_put_route(route);
diff --git a/trunk/net/ax25/ax25_out.c b/trunk/net/ax25/ax25_out.c
index 94557b1a1fa2..3475a3ac9343 100644
--- a/trunk/net/ax25/ax25_out.c
+++ b/trunk/net/ax25/ax25_out.c
@@ -340,19 +340,21 @@ void ax25_transmit_buffer(ax25_cb *ax25, struct sk_buff *skb, int type)
 
 	ax25_addr_build(ptr, &ax25->source_addr, &ax25->dest_addr, ax25->digipeat, type, ax25->modulus);
 
-	ax25_queue_xmit(skb, ax25->ax25_dev->dev);
+	skb->dev = ax25->ax25_dev->dev;
+
+	ax25_queue_xmit(skb);
 }
 
 /*
  *	A small shim to dev_queue_xmit to add the KISS control byte, and do
  *	any packet forwarding in operation.
  */
-void ax25_queue_xmit(struct sk_buff *skb, struct net_device *dev)
+void ax25_queue_xmit(struct sk_buff *skb)
 {
 	unsigned char *ptr;
 
 	skb->protocol = htons(ETH_P_AX25);
-	skb->dev      = ax25_fwd_dev(dev);
+	skb->dev      = ax25_fwd_dev(skb->dev);
 
 	ptr  = skb_push(skb, 1);
 	*ptr = 0x00;			/* KISS */
diff --git a/trunk/net/ax25/ax25_subr.c b/trunk/net/ax25/ax25_subr.c
index 99694b57f6f5..8cf72707af8b 100644
--- a/trunk/net/ax25/ax25_subr.c
+++ b/trunk/net/ax25/ax25_subr.c
@@ -220,7 +220,9 @@ void ax25_return_dm(struct net_device *dev, ax25_address *src, ax25_address *des
 	dptr  = skb_push(skb, ax25_addr_size(digi));
 	dptr += ax25_addr_build(dptr, dest, src, &retdigi, AX25_RESPONSE, AX25_MODULUS);
 
-	ax25_queue_xmit(skb, dev);
+	skb->dev      = dev;
+
+	ax25_queue_xmit(skb);
 }
 
 /*
diff --git a/trunk/net/core/skbuff.c b/trunk/net/core/skbuff.c
index f65b3de590a9..1b64817d7de6 100644
--- a/trunk/net/core/skbuff.c
+++ b/trunk/net/core/skbuff.c
@@ -86,10 +86,8 @@ static kmem_cache_t *skbuff_head_cache;
  */
 void skb_over_panic(struct sk_buff *skb, int sz, void *here)
 {
-	printk(KERN_EMERG "skb_over_panic: text:%p len:%d put:%d head:%p "
-	                  "data:%p tail:%p end:%p dev:%s\n",
-	       here, skb->len, sz, skb->head, skb->data, skb->tail, skb->end,
-	       skb->dev ? skb->dev->name : "<NULL>");
+	printk(KERN_INFO "skput:over: %p:%d put:%d dev:%s",
+		here, skb->len, sz, skb->dev ? skb->dev->name : "<NULL>");
 	BUG();
 }
 
@@ -104,10 +102,8 @@ void skb_over_panic(struct sk_buff *skb, int sz, void *here)
 
 void skb_under_panic(struct sk_buff *skb, int sz, void *here)
 {
-	printk(KERN_EMERG "skb_under_panic: text:%p len:%d put:%d head:%p "
-	                  "data:%p tail:%p end:%p dev:%s\n",
-	       here, skb->len, sz, skb->head, skb->data, skb->tail, skb->end,
-	       skb->dev ? skb->dev->name : "<NULL>");
+	printk(KERN_INFO "skput:under: %p:%d put:%d dev:%s",
+               here, skb->len, sz, skb->dev ? skb->dev->name : "<NULL>");
 	BUG();
 }
 
diff --git a/trunk/net/xfrm/xfrm_state.c b/trunk/net/xfrm/xfrm_state.c
index d11747c2a763..1db59f11f37d 100644
--- a/trunk/net/xfrm/xfrm_state.c
+++ b/trunk/net/xfrm/xfrm_state.c
@@ -357,9 +357,8 @@ xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr,
 
 	x = best;
 	if (!x && !error && !acquire_in_progress) {
-		if (tmpl->id.spi &&
-		    (x0 = afinfo->state_lookup(daddr, tmpl->id.spi,
-		                               tmpl->id.proto)) != NULL) {
+		x0 = afinfo->state_lookup(&tmpl->id.daddr, tmpl->id.spi, tmpl->id.proto);
+		if (x0 != NULL) {
 			xfrm_state_put(x0);
 			error = -EEXIST;
 			goto out;