From 623a8bb0c7384ee341a818dec4ec7cbae8d95a2d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 11 Nov 2010 23:10:30 +0000 Subject: [PATCH] --- yaml --- r: 221883 b: refs/heads/master c: 9395f6ea3c61d80ccc7a13668d27afbb8d9436ba h: refs/heads/master i: 221881: 8161e9ba83cf384c293ebf7ad130ae8d011463da 221879: a384c626c2739d33fdd2eda708e40317d45d32ab v: v3 --- [refs] | 2 +- trunk/arch/arm/common/gic.c | 28 ++++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 57b4123310e0..a6175523115f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e56c010f0d08bbecd05074eded7805d555da29b6 +refs/heads/master: 9395f6ea3c61d80ccc7a13668d27afbb8d9436ba diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index ada6359160eb..772f95f1aecd 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -251,15 +251,16 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); /* - * Set priority on all interrupts. + * Set priority on all global interrupts. */ - for (i = 0; i < max_irq; i += 4) + for (i = 32; i < max_irq; i += 4) writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); /* - * Disable all interrupts. + * Disable all interrupts. Leave the PPI and SGIs alone + * as these enables are banked registers. */ - for (i = 0; i < max_irq; i += 32) + for (i = 32; i < max_irq; i += 32) writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); /* @@ -277,11 +278,30 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) { + void __iomem *dist_base; + int i; + if (gic_nr >= MAX_GIC_NR) BUG(); + dist_base = gic_data[gic_nr].dist_base; + BUG_ON(!dist_base); + gic_data[gic_nr].cpu_base = base; + /* + * Deal with the banked PPI and SGI interrupts - disable all + * PPI interrupts, ensure all SGI interrupts are enabled. + */ + writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); + writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); + + /* + * Set priority on PPI and SGI interrupts + */ + for (i = 0; i < 32; i += 4) + writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); + writel(0xf0, base + GIC_CPU_PRIMASK); writel(1, base + GIC_CPU_CTRL); }