From 629c9e1fe165f279b67b7262a62f25e338d997e4 Mon Sep 17 00:00:00 2001
From: Daniel Cotey <puff65537@bansheeslibrary.com>
Date: Sat, 15 Sep 2012 06:06:20 -0700
Subject: [PATCH] --- yaml --- r: 325336 b: refs/heads/master c:
 d5b4f42f8f87ad2f58cea6fd8b3ce419056132ed h: refs/heads/master v: v3

---
 [refs]                                 |  2 +-
 trunk/drivers/staging/silicom/bp_mod.h | 44 +++++++++++++-------------
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/[refs] b/[refs]
index 0a9080b18307..38cab1fb56aa 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 97ef0a461ba82cb641ae53314997ce44161b749a
+refs/heads/master: d5b4f42f8f87ad2f58cea6fd8b3ce419056132ed
diff --git a/trunk/drivers/staging/silicom/bp_mod.h b/trunk/drivers/staging/silicom/bp_mod.h
index 2862c5790c28..f59c061660fe 100644
--- a/trunk/drivers/staging/silicom/bp_mod.h
+++ b/trunk/drivers/staging/silicom/bp_mod.h
@@ -463,28 +463,28 @@ static inline unsigned int jiffies_to_msecs(const unsigned long j)
 	 (pid == SILICOM_PE2G4BPFi35ZX_SSID))
 
 #define BP10G9_IF_SERIES(pid) \
-((pid==INTEL_PE210G2SPI9_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9CX4_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9SR_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9LR_SSID)|| \
-(pid==SILICOM_M1E10G2BPI9T_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9CX4_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9SR_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9LR_SSID)|| \
-(pid==SILICOM_M2E10G2BPI9T_SSID)|| \
-(pid==SILICOM_PE210G2BPI9CX4_SSID)|| \
-(pid==SILICOM_PE210G2BPI9SR_SSID)|| \
-(pid==SILICOM_PE210G2BPI9LR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9SR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9SRRB_SSID)|| \
-(pid==SILICOM_PE210G2DBi9LR_SSID)|| \
-(pid==SILICOM_PE210G2DBi9LRRB_SSID)|| \
-(pid==SILICOM_PE310G4DBi940SR_SSID)|| \
-(pid==SILICOM_PEG2BISC6_SSID)|| \
-(pid==SILICOM_PE310G4BPi9T_SSID)|| \
-(pid==SILICOM_PE310G4BPi9SR_SSID)|| \
-(pid==SILICOM_PE310G4BPi9LR_SSID)|| \
-(pid==SILICOM_PE210G2BPI9T_SSID))
+	((pid == INTEL_PE210G2SPI9_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9SR_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9LR_SSID) || \
+	 (pid == SILICOM_M1E10G2BPI9T_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9SR_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9LR_SSID) || \
+	 (pid == SILICOM_M2E10G2BPI9T_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9CX4_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9SR_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9LR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9SR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9SRRB_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9LR_SSID) || \
+	 (pid == SILICOM_PE210G2DBi9LRRB_SSID) || \
+	 (pid == SILICOM_PE310G4DBi940SR_SSID) || \
+	 (pid == SILICOM_PEG2BISC6_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9T_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9SR_SSID) || \
+	 (pid == SILICOM_PE310G4BPi9LR_SSID) || \
+	 (pid == SILICOM_PE210G2BPI9T_SSID))
 
 /*******************************************************/
 /* 1G INTERFACE ****************************************/