From 630b77c95ff63eea3ed69e6e14cd7df76b5916bf Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:08:14 -0700 Subject: [PATCH] --- yaml --- r: 226628 b: refs/heads/master c: 1124d2f9186ec9e42e1c3f78c20199ba2cb597e2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/sram242x.S | 6 ++++++ trunk/arch/arm/mach-omap2/sram243x.S | 6 ++++++ trunk/arch/arm/mach-omap2/sram34xx.S | 6 ++++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 19ae2536be1f..a2b13b42875a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f1f4b7703f8fd165ece458ae97ebddb2b62b2ce3 +refs/heads/master: 1124d2f9186ec9e42e1c3f78c20199ba2cb597e2 diff --git a/trunk/arch/arm/mach-omap2/sram242x.S b/trunk/arch/arm/mach-omap2/sram242x.S index 8e7e6fef09ef..055310cc77de 100644 --- a/trunk/arch/arm/mach-omap2/sram242x.S +++ b/trunk/arch/arm/mach-omap2/sram242x.S @@ -21,6 +21,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ #include #include diff --git a/trunk/arch/arm/mach-omap2/sram243x.S b/trunk/arch/arm/mach-omap2/sram243x.S index 9ea87f68524f..f9007580aea3 100644 --- a/trunk/arch/arm/mach-omap2/sram243x.S +++ b/trunk/arch/arm/mach-omap2/sram243x.S @@ -21,6 +21,12 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ #include #include diff --git a/trunk/arch/arm/mach-omap2/sram34xx.S b/trunk/arch/arm/mach-omap2/sram34xx.S index b7aba60f8325..7f893a29d500 100644 --- a/trunk/arch/arm/mach-omap2/sram34xx.S +++ b/trunk/arch/arm/mach-omap2/sram34xx.S @@ -104,6 +104,12 @@ * touching the SDRAM. Until that time, users who know that their use case * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING * option. + * + * Richard Woodruff notes that any changes to this code must be carefully + * audited and tested to ensure that they don't cause a TLB miss while + * the SDRAM is inaccessible. Such a situation will crash the system + * since it will cause the ARM MMU to attempt to walk the page tables. + * These crashes may be intermittent. */ ENTRY(omap3_sram_configure_core_dpll) stmfd sp!, {r1-r12, lr} @ store regs to stack