From 6318f378c590eba72aa3faab1b82cc338c3568e5 Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Thu, 1 Jul 2010 13:22:48 +0100
Subject: [PATCH] --- yaml --- r: 200806 b: refs/heads/master c:
 42c4dafe803dcad82980fd8b0831a89032156f93 h: refs/heads/master v: v3

---
 [refs]                    | 2 +-
 trunk/arch/arm/mm/Kconfig | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index ffa4679a58a1..68b4afe44ad7 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2503a5ecd86c002506001eba432c524ea009fe7f
+refs/heads/master: 42c4dafe803dcad82980fd8b0831a89032156f93
diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig
index fc1b2fa59429..101105e52610 100644
--- a/trunk/arch/arm/mm/Kconfig
+++ b/trunk/arch/arm/mm/Kconfig
@@ -813,6 +813,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to