From 6388b227bdb7906140f98f136aa774fcb90bb7c5 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 19 Jul 2011 22:43:28 +0100 Subject: [PATCH] --- yaml --- r: 270121 b: refs/heads/master c: ecf5a893211c26e02b9d4cfd6ba2183473ac0203 h: refs/heads/master i: 270119: 11542e4734f228efff8cf0ea02075e8c9a78d724 v: v3 --- [refs] | 2 +- trunk/arch/arm/kernel/perf_event.c | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 4f49729f7603..79831264ddde 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d2b41f7456223ba6abd3b38d7b54be97914f3aa5 +refs/heads/master: ecf5a893211c26e02b9d4cfd6ba2183473ac0203 diff --git a/trunk/arch/arm/kernel/perf_event.c b/trunk/arch/arm/kernel/perf_event.c index d507fe148e00..c668c91d0c0a 100644 --- a/trunk/arch/arm/kernel/perf_event.c +++ b/trunk/arch/arm/kernel/perf_event.c @@ -35,7 +35,7 @@ static struct platform_device *pmu_device; static DEFINE_RAW_SPINLOCK(pmu_lock); /* - * ARMv6 supports a maximum of 3 events, starting from index 1. If we add + * ARMv6 supports a maximum of 3 events, starting from index 0. If we add * another platform that supports more, we need to increase this to be the * largest of all platforms. * @@ -43,13 +43,12 @@ static DEFINE_RAW_SPINLOCK(pmu_lock); * cycle counter CCNT + 31 events counters CNT0..30. * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. */ -#define ARMPMU_MAX_HWEVENTS 33 +#define ARMPMU_MAX_HWEVENTS 32 /* The events for a given CPU. */ struct cpu_hw_events { /* - * The events that are active on the CPU for the given index. Index 0 - * is reserved. + * The events that are active on the CPU for the given index. */ struct perf_event *events[ARMPMU_MAX_HWEVENTS]; @@ -597,7 +596,7 @@ static void armpmu_enable(struct pmu *pmu) if (!armpmu) return; - for (idx = 0; idx <= armpmu->num_events; ++idx) { + for (idx = 0; idx < armpmu->num_events; ++idx) { struct perf_event *event = cpuc->events[idx]; if (!event)