From 63d8d0410a1bf20d246d466758da45c646a4c2e4 Mon Sep 17 00:00:00 2001
From: Marcelo Tosatti <marcelo@kvack.org>
Date: Fri, 5 May 2006 17:09:29 -0300
Subject: [PATCH] --- yaml --- r: 26569 b: refs/heads/master c:
 c51e078f82096a7d35ac8ec2416272e843a0e1c4 h: refs/heads/master i:   26567:
 ac4757b2110a3d3f98c9d960a5a8a0938c6e3427 v: v3

---
 [refs]                           | 2 +-
 trunk/arch/ppc/kernel/head_8xx.S | 4 ----
 2 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/[refs] b/[refs]
index c84a9f9004e1..0373c87fee1f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e4de00215c3af02116db3d486bf53700dfe10619
+refs/heads/master: c51e078f82096a7d35ac8ec2416272e843a0e1c4
diff --git a/trunk/arch/ppc/kernel/head_8xx.S b/trunk/arch/ppc/kernel/head_8xx.S
index ec53c7d65f2b..7a2f20583be4 100644
--- a/trunk/arch/ppc/kernel/head_8xx.S
+++ b/trunk/arch/ppc/kernel/head_8xx.S
@@ -355,9 +355,7 @@ InstructionTLBMiss:
 
 	. = 0x1200
 DataStoreTLBMiss:
-#ifdef CONFIG_8xx_CPU6
 	stw	r3, 8(r0)
-#endif
 	DO_8xx_CPU6(0x3f80, r3)
 	mtspr	SPRN_M_TW, r10	/* Save a couple of working registers */
 	mfcr	r10
@@ -417,9 +415,7 @@ DataStoreTLBMiss:
 	lwz	r11, 0(r0)
 	mtcr	r11
 	lwz	r11, 4(r0)
-#ifdef CONFIG_8xx_CPU6
 	lwz	r3, 8(r0)
-#endif
 	rfi
 
 /* This is an instruction TLB error on the MPC8xx.  This could be due