From 642633b06d62d22ca68c7700bbff68f4c84246c0 Mon Sep 17 00:00:00 2001
From: Catalin Marinas <catalin.marinas@arm.com>
Date: Wed, 24 Mar 2010 16:47:53 +0100
Subject: [PATCH] --- yaml --- r: 189405 b: refs/heads/master c:
 319f551a0a167b49b5bbb4a9ff4802046a572bc5 h: refs/heads/master i:   189403:
 b8e41687025d8799b167b481100ae4cb9c40bcb1 v: v3

---
 [refs]                                  |  2 +-
 trunk/arch/arm/include/asm/outercache.h | 14 ++++++++++++++
 trunk/arch/arm/mm/Kconfig               |  6 ++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 0d52f0d837d3..3876e78b969a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 33f663ff9186da1bcc88dc7830b3a632bd472da5
+refs/heads/master: 319f551a0a167b49b5bbb4a9ff4802046a572bc5
diff --git a/trunk/arch/arm/include/asm/outercache.h b/trunk/arch/arm/include/asm/outercache.h
index c8571cbb5574..25f76bae57ab 100644
--- a/trunk/arch/arm/include/asm/outercache.h
+++ b/trunk/arch/arm/include/asm/outercache.h
@@ -25,6 +25,9 @@ struct outer_cache_fns {
 	void (*inv_range)(unsigned long, unsigned long);
 	void (*clean_range)(unsigned long, unsigned long);
 	void (*flush_range)(unsigned long, unsigned long);
+#ifdef CONFIG_OUTER_CACHE_SYNC
+	void (*sync)(void);
+#endif
 };
 
 #ifdef CONFIG_OUTER_CACHE
@@ -58,4 +61,15 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
 
 #endif
 
+#ifdef CONFIG_OUTER_CACHE_SYNC
+static inline void outer_sync(void)
+{
+	if (outer_cache.sync)
+		outer_cache.sync();
+}
+#else
+static inline void outer_sync(void)
+{ }
+#endif
+
 #endif	/* __ASM_OUTERCACHE_H */
diff --git a/trunk/arch/arm/mm/Kconfig b/trunk/arch/arm/mm/Kconfig
index c4ed9f93f646..88a24de55aaf 100644
--- a/trunk/arch/arm/mm/Kconfig
+++ b/trunk/arch/arm/mm/Kconfig
@@ -736,6 +736,12 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 config OUTER_CACHE
 	bool
 
+config OUTER_CACHE_SYNC
+	bool
+	help
+	  The outer cache has a outer_cache_fns.sync function pointer
+	  that can be used to drain the write buffer of the outer cache.
+
 config CACHE_FEROCEON_L2
 	bool "Enable the Feroceon L2 cache controller"
 	depends on ARCH_KIRKWOOD || ARCH_MV78XX0