From 6447b5eadd2f26e99e766b1eeb42aa355360cffd Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 6 Sep 2011 09:56:17 +0100 Subject: [PATCH] --- yaml --- r: 279822 b: refs/heads/master c: 562e0027d21bf64838178e2f5157df3d5833972e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/common/gic.c | 27 +++++++++++++++++++++++ trunk/arch/arm/include/asm/hardware/gic.h | 1 + 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2d06cc5a6f39..f54c5a05811f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: baeeb8229cace91c10c856d91e5ca861d3c44968 +refs/heads/master: 562e0027d21bf64838178e2f5157df3d5833972e diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index 43cb6f1a7cf2..3c78b7c60691 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -40,6 +40,7 @@ #include #include +#include #include #include @@ -272,6 +273,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) #define gic_set_wake NULL #endif +asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ + u32 irqstat, irqnr; + struct gic_chip_data *gic = &gic_data[0]; + void __iomem *cpu_base = gic_data_cpu_base(gic); + + do { + irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); + irqnr = irqstat & ~0x1c00; + + if (likely(irqnr > 15 && irqnr < 1021)) { + irqnr = irq_domain_to_irq(&gic->domain, irqnr); + handle_IRQ(irqnr, regs); + continue; + } + if (irqnr < 16) { + writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); +#ifdef CONFIG_SMP + handle_IPI(irqnr, regs); +#endif + continue; + } + break; + } while (1); +} + static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = irq_get_handler_data(irq); diff --git a/trunk/arch/arm/include/asm/hardware/gic.h b/trunk/arch/arm/include/asm/hardware/gic.h index 2721d90625e5..ecf7c02fa16c 100644 --- a/trunk/arch/arm/include/asm/hardware/gic.h +++ b/trunk/arch/arm/include/asm/hardware/gic.h @@ -43,6 +43,7 @@ void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, u32 offset); int gic_of_init(struct device_node *node, struct device_node *parent); void gic_secondary_init(unsigned int); +void gic_handle_irq(struct pt_regs *regs); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);