From 64883d24807f4d9d55d31765b0d424cb9bd985f8 Mon Sep 17 00:00:00 2001
From: Philipp Zabel <p.zabel@pengutronix.de>
Date: Thu, 28 Mar 2013 16:23:32 +0100
Subject: [PATCH] --- yaml --- r: 373921 b: refs/heads/master c:
 32f3b8da222b0817e0544acd888071aff674b629 h: refs/heads/master i:   373919:
 2b2e645cda6d7f48cec60922ced0130f33c49109 v: v3

---
 [refs]                              | 2 +-
 trunk/arch/arm/mach-imx/clk-imx6q.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 6cb2103e46e3..12353fc619c3 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 2df1d026edc11e88ad0a2216e79232737f5939e2
+refs/heads/master: 32f3b8da222b0817e0544acd888071aff674b629
diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c
index 2b230f83170b..43dbcd618be3 100644
--- a/trunk/arch/arm/mach-imx/clk-imx6q.c
+++ b/trunk/arch/arm/mach-imx/clk-imx6q.c
@@ -547,6 +547,11 @@ int __init mx6q_clocks_init(void)
 	clk_register_clkdev(clk[cko1], "cko1", NULL);
 	clk_register_clkdev(clk[arm], NULL, "cpu0");
 
+	if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
+		clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+		clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+	}
+
 	/*
 	 * The gpmi needs 100MHz frequency in the EDO/Sync mode,
 	 * We can not get the 100MHz from the pll2_pfd0_352m.