From 64f14006bb1aab82dcc2f6464fea22750f6a300d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?St=C3=A9phane=20Marchesin?= Date: Tue, 29 Jan 2013 19:41:59 -0800 Subject: [PATCH] --- yaml --- r: 360917 b: refs/heads/master c: 0920a48719f1ceefc909387a64f97563848c7854 h: refs/heads/master i: 360915: d99d3c0d51128d7419ba7a445088ec6580502f9a v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 1ad8dc4545a1..024330512600 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 61bc95c1fbbb6a08b55bbe161fdf1ea5493fc595 +refs/heads/master: 0920a48719f1ceefc909387a64f97563848c7854 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index 61fee7fcdc2c..a1794c6df1bf 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -2574,7 +2574,7 @@ static void gen6_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP, 0); I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); I915_WRITE(GEN6_RC6_THRESHOLD, 50000); - I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); + I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ /* Check if we are enabling RC6 */