From 654cd01af9e20648861dab9b625e71fbee15e039 Mon Sep 17 00:00:00 2001 From: Paolo Ciarrocchi Date: Tue, 19 Feb 2008 23:20:45 +0100 Subject: [PATCH] --- yaml --- r: 88617 b: refs/heads/master c: 1577720524bab104eeb605c810963a2106cf4575 h: refs/heads/master i: 88615: 0b0b4f6c4162e136fc0f785028408a15e5189270 v: v3 --- [refs] | 2 +- trunk/arch/x86/kernel/cpu/mcheck/p5.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 560de2b29ba9..ff3bc2f0ed31 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8cf36d2bc5832da17a58c5f10adf2d92d138c992 +refs/heads/master: 1577720524bab104eeb605c810963a2106cf4575 diff --git a/trunk/arch/x86/kernel/cpu/mcheck/p5.c b/trunk/arch/x86/kernel/cpu/mcheck/p5.c index a18310aaae0c..bfa5817afdda 100644 --- a/trunk/arch/x86/kernel/cpu/mcheck/p5.c +++ b/trunk/arch/x86/kernel/cpu/mcheck/p5.c @@ -9,20 +9,20 @@ #include #include -#include +#include #include #include #include "mce.h" /* Machine check handler for Pentium class Intel */ -static void pentium_machine_check(struct pt_regs * regs, long error_code) +static void pentium_machine_check(struct pt_regs *regs, long error_code) { u32 loaddr, hi, lotype; rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); printk(KERN_EMERG "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype); - if(lotype&(1<<5)) + if (lotype&(1<<5)) printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id()); add_taint(TAINT_MACHINE_CHECK); } @@ -31,13 +31,13 @@ static void pentium_machine_check(struct pt_regs * regs, long error_code) void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { u32 l, h; - + /*Check for MCE support */ - if( !cpu_has(c, X86_FEATURE_MCE) ) - return; + if (!cpu_has(c, X86_FEATURE_MCE)) + return; /* Default P5 to off as its often misconnected */ - if(mce_disabled != -1) + if (mce_disabled != -1) return; machine_check_vector = pentium_machine_check; wmb(); @@ -47,7 +47,7 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) rdmsr(MSR_IA32_P5_MC_TYPE, l, h); printk(KERN_INFO "Intel old style machine check architecture supported.\n"); - /* Enable MCE */ + /* Enable MCE */ set_in_cr4(X86_CR4_MCE); printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id()); }