From 67da230238222acdd213878ba73be8ef56fcc791 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 24 Jan 2013 15:29:38 +0200 Subject: [PATCH] --- yaml --- r: 358035 b: refs/heads/master c: 8f6d8ee9f6884b8fea026b614d0475177975d066 h: refs/heads/master i: 358033: a5a574a904ce83175ae7db0beb4f15888cce1a43 358031: e41f67adca43e00a1fcab45a020ae4755ea5f1c5 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 56ba095b277a..da6bcd13f44e 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9dc33f31f2ed609eb77ddebb82f93c7cdf348879 +refs/heads/master: 8f6d8ee9f6884b8fea026b614d0475177975d066 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 896946812e74..3540a06743ee 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -2773,13 +2773,13 @@ /* drain latency register values*/ #define DRAIN_LATENCY_PRECISION_32 32 #define DRAIN_LATENCY_PRECISION_16 16 -#define VLV_DDL1 0x70050 +#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050) #define DDL_CURSORA_PRECISION_32 (1<<31) #define DDL_CURSORA_PRECISION_16 (0<<31) #define DDL_CURSORA_SHIFT 24 #define DDL_PLANEA_PRECISION_32 (1<<7) #define DDL_PLANEA_PRECISION_16 (0<<7) -#define VLV_DDL2 0x70054 +#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054) #define DDL_CURSORB_PRECISION_32 (1<<31) #define DDL_CURSORB_PRECISION_16 (0<<31) #define DDL_CURSORB_SHIFT 24