From 67fba44060b940f1d7d70d3d492ab9f6415cfc11 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 12 Oct 2011 10:49:14 -0700 Subject: [PATCH] --- yaml --- r: 269843 b: refs/heads/master c: f7cb34d47d2e30a8eb6201390ad81e232541c6d0 h: refs/heads/master i: 269841: eb65de052441705ca96aaa296c20cc9c90bf3712 269839: d0674b897303fd36283825a471f0addb24d2169b v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index a53640f6cced..903cb818252a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4b645f14021871e06ce96c359bbdf0b48248c26e +refs/heads/master: f7cb34d47d2e30a8eb6201390ad81e232541c6d0 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index c9bbf5e8fbe8..880d44e38353 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -5549,7 +5549,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; - DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); + DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); drm_mode_debug_printmodeline(mode); /* PCH eDP needs FDI, but CPU eDP does not */