From 68312e73345201be34779d8c239e8e3a2908ca3a Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 24 Aug 2012 15:20:59 +0100 Subject: [PATCH] --- yaml --- r: 322627 b: refs/heads/master c: dbece45894d3ab1baac15a96dc4e1e8e23f64a93 h: refs/heads/master i: 322625: 4b3c5b208ccfb2bee285f226ec39a229fbf925e8 322623: 8b6359d9a96e5769dd0e9bd377be4b04d9ac2b86 v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/compressed/head.S | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index ed9323ed8260..84f164fa5420 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d968d2b801d877601d54e35e6dd0f52d9c797c99 +refs/heads/master: dbece45894d3ab1baac15a96dc4e1e8e23f64a93 diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S index b8c64b80bafc..81769c1341fa 100644 --- a/trunk/arch/arm/boot/compressed/head.S +++ b/trunk/arch/arm/boot/compressed/head.S @@ -659,10 +659,14 @@ __armv7_mmu_cache_on: #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables #endif + mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client + bic r6, r6, #1 << 31 @ 32-bit translation system + bic r6, r6, #3 << 0 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control + mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register