From 68385a54f7fbf8259cfd074bdc27fcc1079a2955 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sun, 13 May 2012 22:29:25 +0200 Subject: [PATCH] --- yaml --- r: 307457 b: refs/heads/master c: a9dcf84b14ef4e9a609910367576995e6f32f3dc h: refs/heads/master i: 307455: a04b7ef5d79a7caee997218753b197a217654c50 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 413ae52a2471..98888029d8f2 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 83ee9e645846f0c56bd9b33ee28ead03b416bb25 +refs/heads/master: a9dcf84b14ef4e9a609910367576995e6f32f3dc diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 391439fa17b2..956b22899b71 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -6253,10 +6253,11 @@ static void intel_sanitize_modesetting(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; u32 reg, val; + int i; /* Clear any frame start delays used for debugging left by the BIOS */ - for_each_pipe(pipe) { - reg = PIPECONF(pipe); + for_each_pipe(i) { + reg = PIPECONF(i); I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); }