From 683e5af688b63284768005231a237e15390e90fe Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sat, 28 Jan 2012 20:03:05 +0100 Subject: [PATCH] --- yaml --- r: 295659 b: refs/heads/master c: 55256f0e483f66b94cb5b358fc2a57bb75ae6f05 h: refs/heads/master i: 295657: ae4bc4215e66dff7528a455e2cc281515e2d30c8 295655: 5faa99eed069f1445623c3ff3f95bfb2c0e156ce v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/tegra-paz00.dts | 4 ++-- trunk/arch/arm/mach-tegra/board-paz00.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index 34d0431586d0..cf6dd1451819 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 61ffca53ccabdb91a41574335792b7ab4de30b10 +refs/heads/master: 55256f0e483f66b94cb5b358fc2a57bb75ae6f05 diff --git a/trunk/arch/arm/boot/dts/tegra-paz00.dts b/trunk/arch/arm/boot/dts/tegra-paz00.dts index a94e92c98829..825d2957da0b 100644 --- a/trunk/arch/arm/boot/dts/tegra-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra-paz00.dts @@ -46,11 +46,11 @@ }; serial@70006200 { - status = "disable"; + clock-frequency = <216000000>; }; serial@70006300 { - clock-frequency = <216000000>; + status = "disable"; }; serial@70006400 { diff --git a/trunk/arch/arm/mach-tegra/board-paz00.c b/trunk/arch/arm/mach-tegra/board-paz00.c index fcf4f377b1dc..330afdfa2475 100644 --- a/trunk/arch/arm/mach-tegra/board-paz00.c +++ b/trunk/arch/arm/mach-tegra/board-paz00.c @@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .uartclk = 216000000, }, { /* serial port on mini-pcie */ - .membase = IO_ADDRESS(TEGRA_UARTD_BASE), - .mapbase = TEGRA_UARTD_BASE, - .irq = INT_UARTD, + .membase = IO_ADDRESS(TEGRA_UARTC_BASE), + .mapbase = TEGRA_UARTC_BASE, + .irq = INT_UARTC, .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, .type = PORT_TEGRA, .iotype = UPIO_MEM, @@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 216000000, true }, - { "uartd", "pll_p", 216000000, true }, + { "uartc", "pll_p", 216000000, true }, { "pll_p_out4", "pll_p", 24000000, true }, { "usbd", "clk_m", 12000000, false },