From 68ba6e50ab7e9d0db9b6fcccebc3211addc2ce73 Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Wed, 8 Aug 2012 13:57:01 +0000
Subject: [PATCH] --- yaml --- r: 329300 b: refs/heads/master c:
 9a9f5786fcccda3cc61eaa8f537690327eff6853 h: refs/heads/master v: v3

---
 [refs]                                       |  2 +-
 trunk/drivers/gpu/drm/gma500/cdv_intel_dp.c  | 24 ++++++++++++++++++++
 trunk/drivers/gpu/drm/gma500/psb_intel_reg.h |  4 ++++
 3 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index cf62226a34b8..83a212fca57a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d112a8163f83752361dd639a9a579ae5cc05c6cf
+refs/heads/master: 9a9f5786fcccda3cc61eaa8f537690327eff6853
diff --git a/trunk/drivers/gpu/drm/gma500/cdv_intel_dp.c b/trunk/drivers/gpu/drm/gma500/cdv_intel_dp.c
index 0571ef9b889b..9bacce3ce53c 100644
--- a/trunk/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/trunk/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -1778,6 +1778,28 @@ static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
 	return false;
 }
 
+/* Cedarview display clock gating
+
+   We need this disable dot get correct behaviour while enabling
+   DP/eDP. TODO - investigate if we can turn it back to normality
+   after enabling */
+static void cdv_disable_intel_clock_gating(struct drm_device *dev)
+{
+	u32 reg_value;
+	reg_value = REG_READ(DSPCLK_GATE_D);
+
+	reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
+			DPUNIT_PIPEA_GATE_DISABLE |
+			DPCUNIT_CLOCK_GATE_DISABLE |
+			DPLSUNIT_CLOCK_GATE_DISABLE |
+			DPOUNIT_CLOCK_GATE_DISABLE |
+		 	DPIOUNIT_CLOCK_GATE_DISABLE);	
+
+	REG_WRITE(DSPCLK_GATE_D, reg_value);
+
+	udelay(500);		
+}
+
 void
 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
 {
@@ -1841,6 +1863,8 @@ cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev
 			break;
 	}
 
+	cdv_disable_intel_clock_gating(dev);
+
 	cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
         /* FIXME:fail check */
 	cdv_intel_dp_add_properties(connector);
diff --git a/trunk/drivers/gpu/drm/gma500/psb_intel_reg.h b/trunk/drivers/gpu/drm/gma500/psb_intel_reg.h
index 389e969e8986..d914719c4b60 100644
--- a/trunk/drivers/gpu/drm/gma500/psb_intel_reg.h
+++ b/trunk/drivers/gpu/drm/gma500/psb_intel_reg.h
@@ -1313,6 +1313,10 @@ No status bits are changed.
 # define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* Fixed value on CDV */
 # define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6)
+# define DPUNIT_PIPEB_GATE_DISABLE		(1 << 30)
+# define DPUNIT_PIPEA_GATE_DISABLE		(1 << 25)
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24)
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13)
 
 #define RAMCLK_GATE_D		0x6210