From 693891b1a21a8c82200fddd2101bb63f28992d9a Mon Sep 17 00:00:00 2001 From: Vitaly Bordug Date: Thu, 8 Dec 2005 13:56:12 -0200 Subject: [PATCH] --- yaml --- r: 16263 b: refs/heads/master c: 1371d3be045a6a1a8b828b838069b5fe6e0ab4c6 h: refs/heads/master i: 16261: 487a595c70604b5913e2a03251b38702e22c78b8 16259: 3e488a90da85d7333286d8fb63aab25e8b2e1f2e 16255: b69fd24aa9cbdb9b4815ace69380b43f323a2f12 v: v3 --- [refs] | 2 +- trunk/drivers/pcmcia/m8xx_pcmcia.c | 97 ++++++++++++++++++++++++++++-- 2 files changed, 92 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index 5b3d8494daed..d5a62b7566b1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a94515fa1f1609249dbebcfb93181ad0ba4b285a +refs/heads/master: 1371d3be045a6a1a8b828b838069b5fe6e0ab4c6 diff --git a/trunk/drivers/pcmcia/m8xx_pcmcia.c b/trunk/drivers/pcmcia/m8xx_pcmcia.c index ddaab13d21bd..0e07d9535116 100644 --- a/trunk/drivers/pcmcia/m8xx_pcmcia.c +++ b/trunk/drivers/pcmcia/m8xx_pcmcia.c @@ -9,6 +9,9 @@ * * Further fixes, v2.6 kernel port * + * + * Some fixes, additions (C) 2005 Montavista Software, Inc. + * * * "The ExCA standard specifies that socket controllers should provide * two IO and five memory windows per socket, which can be independently @@ -97,6 +100,11 @@ MODULE_LICENSE("Dual MPL/GPL"); #endif #endif +#if defined(CONFIG_MPC885ADS) +#define CONFIG_PCMCIA_SLOT_A +#define PCMCIA_GLITCHY_CD +#endif + /* Cyclades ACS uses both slots */ #ifdef CONFIG_PRxK #define CONFIG_PCMCIA_SLOT_A @@ -374,11 +382,80 @@ static int voltage_set(int slot, int vcc, int vpp) } /* first, turn off all power */ - out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); + out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); + + /* enable new powersettings */ + out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg); + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V + +static void hardware_enable(int slot) +{ + out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN); +} + +static void hardware_disable(int slot) +{ + out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN); +} + +#endif + +/* MPC885ADS Boards */ + +#if defined(CONFIG_MPC885ADS) + +#define PCMCIA_BOARD_MSG "MPC885ADS" + +static int voltage_set(int slot, int vcc, int vpp) +{ + u32 reg = 0; + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + + switch(vcc) { + case 0: + break; + case 33: + reg |= BCSR1_PCCVCC0; + break; + case 50: + reg |= BCSR1_PCCVCC1; + break; + default: + return 1; + } + + switch(vpp) { + case 0: + break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCCVPP1; + else + return 1; + break; + case 120: + if ((vcc == 33) || (vcc == 50)) + reg |= BCSR1_PCCVPP0; + else + return 1; + default: + return 1; + } + + /* first, turn off all power */ + out_be32(bcsr_io, in_be32(bcsr_io) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); /* enable new powersettings */ - out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg); + out_be32(bcsr_io, in_be32(bcsr_io) | reg); + iounmap(bcsr_io); return 0; } @@ -386,12 +463,20 @@ static int voltage_set(int slot, int vcc, int vpp) static void hardware_enable(int slot) { - out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN); + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_PCCEN); + iounmap(bcsr_io); } static void hardware_disable(int slot) { - out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN); + unsigned *bcsr_io; + + bcsr_io = ioremap(BCSR1, sizeof(unsigned long)); + out_be32(bcsr_io, in_be32(bcsr_io) | BCSR1_PCCEN); + iounmap(bcsr_io); } #endif @@ -440,10 +525,10 @@ static int voltage_set(int slot, int vcc, int vpp) } /* first, turn off all power */ - out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); + out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); /* enable new powersettings */ - out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg); + out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg); return 0; }