From 697cc6fad58947c163b91dc130c6d6cdb9c52d88 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Wed, 30 Jan 2008 16:43:28 +0800 Subject: [PATCH] --- yaml --- r: 82063 b: refs/heads/master c: 9f24e82d07e2c64467d0c0c04a798de56461fd4a h: refs/heads/master i: 82061: 0318d569ac5bc9ebb71c817ba3e682ce8c18d96f 82059: 4fb5c35bebebfad55386bb31fbf68d2d5511531c 82055: 112f34679ef473b3235e8273ba0bcb7e1f700fe2 82047: d446442d3ad667d601c4fab9bd1a7821295f2f63 v: v3 --- [refs] | 2 +- trunk/drivers/ata/pata_bf54x.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 509e57c36cc8..6c929870829d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 30d849c95f0598309ca6451900b1fd0d2c0384e6 +refs/heads/master: 9f24e82d07e2c64467d0c0c04a798de56461fd4a diff --git a/trunk/drivers/ata/pata_bf54x.c b/trunk/drivers/ata/pata_bf54x.c index d66f7733b796..7f87f105c2f6 100644 --- a/trunk/drivers/ata/pata_bf54x.c +++ b/trunk/drivers/ata/pata_bf54x.c @@ -299,7 +299,7 @@ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev) */ n6 = num_clocks_min(t6min, fsclk); if (mode >= 0 && mode <= 4 && n6 >= 1) { - dev_dbg(adev->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); + dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk); /* calculate the timing values for register transfers. */ while (mode > 0 && pio_fsclk[mode] > fsclk) mode--; @@ -376,7 +376,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) mode = adev->dma_mode - XFER_UDMA_0; if (mode >= 0 && mode <= 5) { - dev_dbg(adev->ap->dev, "set udmamode: mode=%d\n", mode); + dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode); /* the most restrictive timing value is t6 and tc, * the DIOW - data hold. If one SCLK pulse is longer * than this minimum value then register @@ -433,7 +433,7 @@ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) mode = adev->dma_mode - XFER_MW_DMA_0; if (mode >= 0 && mode <= 2) { - dev_dbg(adev->ap->dev, "set mdmamode: mode=%d\n", mode); + dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode); /* the most restrictive timing value is tf, the DMACK to * read data released. If one SCLK pulse is longer than * this maximum value then the MDMA mode