From 699ac5f23362926988aad47ab62fd4e922237a57 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 5 Jan 2010 09:41:05 +1000 Subject: [PATCH] --- yaml --- r: 179874 b: refs/heads/master c: 7fb8ec8e2bedc8381243cf4bdc4cfa8e657397a8 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nv50_fifo.c | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index bdcd5903c037..c7581d7f0cf0 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 846975a97b098bbbf1232a01a3a5723a4bddd9e7 +refs/heads/master: 7fb8ec8e2bedc8381243cf4bdc4cfa8e657397a8 diff --git a/trunk/drivers/gpu/drm/nouveau/nv50_fifo.c b/trunk/drivers/gpu/drm/nouveau/nv50_fifo.c index b7282284f080..39caf167587d 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv50_fifo.c +++ b/trunk/drivers/gpu/drm/nouveau/nv50_fifo.c @@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan) nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr), nv_ro32(dev, cache, (ptr * 2) + 1)); } - nv_wr32(dev, 0x3210, cnt << 2); - nv_wr32(dev, 0x3270, 0); + nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2); + nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0); /* guessing that all the 0x34xx regs aren't on NV50 */ if (!IS_G80) { @@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan) dev_priv->engine.instmem.finish_access(dev); - nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0); - nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0); nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16)); return 0; }