From 69a81a24c222d60c61df0d27d5913dd5872a79dc Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sun, 11 Jan 2009 18:44:49 +0000 Subject: [PATCH] --- yaml --- r: 130553 b: refs/heads/master c: a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d h: refs/heads/master i: 130551: 71d1176ea435bb94133b652c70926922fdb08ef2 v: v3 --- [refs] | 2 +- trunk/arch/mips/mm/c-r4k.c | 22 +++++++++++++++++++++- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 6752c77b312a..1047f31d57e6 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 012703e0fc9fb1d6cdf778c49f45b796a85ef5bc +refs/heads/master: a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index 6e99665ae860..c43f4b26a690 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (cpu_has_inclusive_pcaches) { if (size >= scache_size) r4k_blast_scache(); - else + else { + unsigned long lsize = cpu_scache_line_size(); + unsigned long almask = ~(lsize - 1); + + /* + * There is no clearly documented alignment requirement + * for the cache instruction on MIPS processors and + * some processors, among them the RM5200 and RM7000 + * QED processors will throw an address error for cache + * hit ops with insufficient alignment. Solved by + * aligning the address to cache line size. + */ + cache_op(Hit_Writeback_Inv_SD, addr & almask); + cache_op(Hit_Writeback_Inv_SD, + (addr + size - 1) & almask); blast_inv_scache_range(addr, addr + size); + } return; } if (cpu_has_safe_index_cacheops && size >= dcache_size) { r4k_blast_dcache(); } else { + unsigned long lsize = cpu_dcache_line_size(); + unsigned long almask = ~(lsize - 1); + R4600_HIT_CACHEOP_WAR_IMPL; + cache_op(Hit_Writeback_Inv_D, addr & almask); + cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask); blast_inv_dcache_range(addr, addr + size); }