From 6a4f09113c39f7d30d83cadfae6def95e7d4d122 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon, 20 Dec 2010 09:45:15 +0000
Subject: [PATCH] --- yaml --- r: 228819 b: refs/heads/master c:
 5909a77ac62cc042f94bd262016cf468a2f96022 h: refs/heads/master i:   228817:
 c3d9a095a92130aa068f1c2ede6927bf82ba3a94   228815:
 5ed290db52e333ff601628398492ca43dcac24bf v: v3

---
 [refs]                                    | 2 +-
 trunk/drivers/gpu/drm/i915/i915_suspend.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index b720335f7db4..52628df90bf5 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 72bfa19c8deb4d1db5ad068c34fd580cb295cbe8
+refs/heads/master: 5909a77ac62cc042f94bd262016cf468a2f96022
diff --git a/trunk/drivers/gpu/drm/i915/i915_suspend.c b/trunk/drivers/gpu/drm/i915/i915_suspend.c
index f623efdb1151..410772466fa7 100644
--- a/trunk/drivers/gpu/drm/i915/i915_suspend.c
+++ b/trunk/drivers/gpu/drm/i915/i915_suspend.c
@@ -822,7 +822,9 @@ int i915_save_state(struct drm_device *dev)
 	if (IS_GEN6(dev))
 		gen6_disable_rps(dev);
 
+	/* XXX disabling the clock gating breaks suspend on gm45
 	intel_disable_clock_gating(dev);
+	 */
 
 	/* Cache mode state */
 	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);