From 6a6e8e4a8e8c36232a5436ec0b511048977e50ff Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 28 May 2012 16:42:52 -0300 Subject: [PATCH] --- yaml --- r: 318525 b: refs/heads/master c: 5cde2a62e8adf12b02e47cf15630e87d4ba8ad5e h: refs/heads/master i: 318523: 6fdb347fd2798405d5cc50a14f16c5ffb63d5c27 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_hdmi.c | 8 -------- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 60443175025b..ceafc9b0b867 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 822974aea875348e69fb6b6d2078ae8372eeec66 +refs/heads/master: 5cde2a62e8adf12b02e47cf15630e87d4ba8ad5e diff --git a/trunk/drivers/gpu/drm/i915/intel_hdmi.c b/trunk/drivers/gpu/drm/i915/intel_hdmi.c index de6f4c2c82ac..614d83fb6738 100644 --- a/trunk/drivers/gpu/drm/i915/intel_hdmi.c +++ b/trunk/drivers/gpu/drm/i915/intel_hdmi.c @@ -158,8 +158,6 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); - intel_wait_for_vblank(dev, intel_crtc->pipe); - val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(frame); @@ -192,8 +190,6 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); - intel_wait_for_vblank(dev, intel_crtc->pipe); - val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(frame); @@ -229,8 +225,6 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); - intel_wait_for_vblank(dev, intel_crtc->pipe); - val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(frame); @@ -265,8 +259,6 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, if (data_reg == 0) return; - intel_wait_for_vblank(dev, intel_crtc->pipe); - val &= ~hsw_infoframe_enable(frame); I915_WRITE(ctl_reg, val);