From 6b4b228048284e0c8365941845d4203ea12fc1e0 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 15 Oct 2012 15:51:32 -0300 Subject: [PATCH] --- yaml --- r: 345132 b: refs/heads/master c: a836bdf9ae5aa3b100c8cdd04aae5bb9c0340145 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 48752d801929..2aa1931ec47c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 247d89f62230f3369aeaab85dca34978f79dcb86 +refs/heads/master: a836bdf9ae5aa3b100c8cdd04aae5bb9c0340145 diff --git a/trunk/drivers/gpu/drm/i915/intel_ddi.c b/trunk/drivers/gpu/drm/i915/intel_ddi.c index 510317270ad1..601ffc277a35 100644 --- a/trunk/drivers/gpu/drm/i915/intel_ddi.c +++ b/trunk/drivers/gpu/drm/i915/intel_ddi.c @@ -1138,14 +1138,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder) struct drm_i915_private *dev_priv = encoder->dev->dev_private; enum port port = intel_ddi_get_encoder_port(intel_encoder); uint32_t val; + bool wait = false; val = I915_READ(DDI_BUF_CTL(port)); if (val & DDI_BUF_CTL_ENABLE) { val &= ~DDI_BUF_CTL_ENABLE; I915_WRITE(DDI_BUF_CTL(port), val); - intel_wait_ddi_buf_idle(dev_priv, port); + wait = true; } + val = I915_READ(DP_TP_CTL(port)); + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); + val |= DP_TP_CTL_LINK_TRAIN_PAT1; + I915_WRITE(DP_TP_CTL(port), val); + + if (wait) + intel_wait_ddi_buf_idle(dev_priv, port); + I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); }