From 6bb40b03bd17e384a3911500ae53b3b560c0f01b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 13 Jun 2011 10:42:19 +0200 Subject: [PATCH] --- yaml --- r: 254868 b: refs/heads/master c: a065685d2f0b4bb69d0f64d2cd396a5c463db2a9 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-davinci/irq.c | 2 +- trunk/arch/arm/mach-vt8500/irq.c | 21 +++++++++------------ trunk/arch/arm/plat-orion/gpio.c | 2 +- trunk/arch/arm/plat-pxa/gpio.c | 10 +++++----- trunk/arch/arm/plat-s5p/irq-gpioint.c | 2 +- trunk/arch/arm/plat-samsung/irq-uart.c | 2 +- trunk/include/linux/irq.h | 3 +-- trunk/kernel/irq/generic-chip.c | 18 ++---------------- 9 files changed, 22 insertions(+), 40 deletions(-) diff --git a/[refs] b/[refs] index e16a417b2ab2..a34e0393db25 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5 +refs/heads/master: a065685d2f0b4bb69d0f64d2cd396a5c463db2a9 diff --git a/trunk/arch/arm/mach-davinci/irq.c b/trunk/arch/arm/mach-davinci/irq.c index d8c1af025931..bfe68ec4e1a6 100644 --- a/trunk/arch/arm/mach-davinci/irq.c +++ b/trunk/arch/arm/mach-davinci/irq.c @@ -53,7 +53,7 @@ davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; diff --git a/trunk/arch/arm/mach-vt8500/irq.c b/trunk/arch/arm/mach-vt8500/irq.c index 642de0408f25..245140c0df10 100644 --- a/trunk/arch/arm/mach-vt8500/irq.c +++ b/trunk/arch/arm/mach-vt8500/irq.c @@ -39,10 +39,9 @@ static void __iomem *ic_regbase; static void __iomem *sic_regbase; -static void vt8500_irq_mask(struct irq_data *d) +static void vt8500_irq_mask(unsigned int irq) { void __iomem *base = ic_regbase; - unsigned irq = d->irq; u8 edge; if (irq >= 64) { @@ -65,10 +64,9 @@ static void vt8500_irq_mask(struct irq_data *d) } } -static void vt8500_irq_unmask(struct irq_data *d) +static void vt8500_irq_unmask(unsigned int irq) { void __iomem *base = ic_regbase; - unsigned irq = d->irq; u8 dctr; if (irq >= 64) { @@ -80,11 +78,10 @@ static void vt8500_irq_unmask(struct irq_data *d) writeb(dctr, base + VT8500_IC_DCTR + irq); } -static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) +static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type) { void __iomem *base = ic_regbase; - unsigned irq = d->irq; - unsigned orig_irq = irq; + unsigned int orig_irq = irq; u8 dctr; if (irq >= 64) { @@ -117,11 +114,11 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type) } static struct irq_chip vt8500_irq_chip = { - .name = "vt8500", - .irq_ack = vt8500_irq_mask, - .irq_mask = vt8500_irq_mask, - .irq_unmask = vt8500_irq_unmask, - .irq_set_type = vt8500_irq_set_type, + .name = "vt8500", + .ack = vt8500_irq_mask, + .mask = vt8500_irq_mask, + .unmask = vt8500_irq_unmask, + .set_type = vt8500_irq_set_type, }; void __init vt8500_init_irq(void) diff --git a/trunk/arch/arm/plat-orion/gpio.c b/trunk/arch/arm/plat-orion/gpio.c index 41ab97ebe4cf..5b4fffab1eb4 100644 --- a/trunk/arch/arm/plat-orion/gpio.c +++ b/trunk/arch/arm/plat-orion/gpio.c @@ -432,7 +432,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio, ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; ct->regs.ack = GPIO_EDGE_CAUSE_OFF; ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - ct->chip.irq_ack = irq_gc_ack_clr_bit; + ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_clr_bit; ct->chip.irq_unmask = irq_gc_mask_set_bit; ct->chip.irq_set_type = gpio_irq_set_type; diff --git a/trunk/arch/arm/plat-pxa/gpio.c b/trunk/arch/arm/plat-pxa/gpio.c index 48ebb9479b61..a11dc3670505 100644 --- a/trunk/arch/arm/plat-pxa/gpio.c +++ b/trunk/arch/arm/plat-pxa/gpio.c @@ -50,7 +50,7 @@ static inline void __iomem *gpio_chip_base(struct gpio_chip *c) return container_of(c, struct pxa_gpio_chip, chip)->regbase; } -static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) +static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) { return &pxa_gpio_chips[gpio_to_bank(gpio)]; } @@ -161,7 +161,7 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) int gpio = irq_to_gpio(d->irq); unsigned long gpdr, mask = GPIO_bit(gpio); - c = gpio_to_chip(gpio); + c = gpio_to_pxachip(gpio); if (type == IRQ_TYPE_PROBE) { /* Don't mess with enabled GPIOs using preconfigured edges or @@ -230,7 +230,7 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) static void pxa_ack_muxed_gpio(struct irq_data *d) { int gpio = irq_to_gpio(d->irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); + struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); } @@ -238,7 +238,7 @@ static void pxa_ack_muxed_gpio(struct irq_data *d) static void pxa_mask_muxed_gpio(struct irq_data *d) { int gpio = irq_to_gpio(d->irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); + struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); uint32_t grer, gfer; c->irq_mask &= ~GPIO_bit(gpio); @@ -252,7 +252,7 @@ static void pxa_mask_muxed_gpio(struct irq_data *d) static void pxa_unmask_muxed_gpio(struct irq_data *d) { int gpio = irq_to_gpio(d->irq); - struct pxa_gpio_chip *c = gpio_to_chip(gpio); + struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); c->irq_mask |= GPIO_bit(gpio); update_edge_detect(c); diff --git a/trunk/arch/arm/plat-s5p/irq-gpioint.c b/trunk/arch/arm/plat-s5p/irq-gpioint.c index 327ab9f662e8..135abda31c9a 100644 --- a/trunk/arch/arm/plat-s5p/irq-gpioint.c +++ b/trunk/arch/arm/plat-s5p/irq-gpioint.c @@ -152,7 +152,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) if (!gc) return -ENOMEM; ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_set_type = s5p_gpioint_set_type, diff --git a/trunk/arch/arm/plat-samsung/irq-uart.c b/trunk/arch/arm/plat-samsung/irq-uart.c index 0e46588d847b..32582c0958e3 100644 --- a/trunk/arch/arm/plat-samsung/irq-uart.c +++ b/trunk/arch/arm/plat-samsung/irq-uart.c @@ -55,7 +55,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base, handle_level_irq); ct = gc->chip_types; - ct->chip.irq_ack = irq_gc_ack_set_bit; + ct->chip.irq_ack = irq_gc_ack; ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->regs.ack = S3C64XX_UINTP; diff --git a/trunk/include/linux/irq.h b/trunk/include/linux/irq.h index baa397eb9c33..8b4538446636 100644 --- a/trunk/include/linux/irq.h +++ b/trunk/include/linux/irq.h @@ -676,8 +676,7 @@ void irq_gc_mask_disable_reg(struct irq_data *d); void irq_gc_mask_set_bit(struct irq_data *d); void irq_gc_mask_clr_bit(struct irq_data *d); void irq_gc_unmask_enable_reg(struct irq_data *d); -void irq_gc_ack_set_bit(struct irq_data *d); -void irq_gc_ack_clr_bit(struct irq_data *d); +void irq_gc_ack(struct irq_data *d); void irq_gc_mask_disable_reg_and_ack(struct irq_data *d); void irq_gc_eoi(struct irq_data *d); int irq_gc_set_wake(struct irq_data *d, unsigned int on); diff --git a/trunk/kernel/irq/generic-chip.c b/trunk/kernel/irq/generic-chip.c index 3a2cab407b93..31a9db711906 100644 --- a/trunk/kernel/irq/generic-chip.c +++ b/trunk/kernel/irq/generic-chip.c @@ -101,10 +101,10 @@ void irq_gc_unmask_enable_reg(struct irq_data *d) } /** - * irq_gc_ack_set_bit - Ack pending interrupt via setting bit + * irq_gc_ack - Ack pending interrupt * @d: irq_data */ -void irq_gc_ack_set_bit(struct irq_data *d) +void irq_gc_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); u32 mask = 1 << (d->irq - gc->irq_base); @@ -114,20 +114,6 @@ void irq_gc_ack_set_bit(struct irq_data *d) irq_gc_unlock(gc); } -/** - * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit - * @d: irq_data - */ -void irq_gc_ack_clr_bit(struct irq_data *d) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - u32 mask = ~(1 << (d->irq - gc->irq_base)); - - irq_gc_lock(gc); - irq_reg_writel(mask, gc->reg_base + cur_regs(d)->ack); - irq_gc_unlock(gc); -} - /** * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt * @d: irq_data