From 6be5aa4e08e82f5e6a4d8e0a259c827396889336 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Sat, 21 Apr 2012 13:15:37 +0530 Subject: [PATCH] --- yaml --- r: 308273 b: refs/heads/master c: 30551c0108e0d2fed48778a6bbd52843088bcb7b h: refs/heads/master i: 308271: e81065fac622534c26122c1657b8427ba866940b v: v3 --- [refs] | 2 +- .../DocBook/media/v4l/pixfmt-nv12m.xml | 2 +- .../DocBook/media/v4l/pixfmt-yuv420m.xml | 2 +- .../devicetree/bindings/arm/spear-timer.txt | 18 + .../bindings/pinctrl/fsl,imx-pinctrl.txt | 95 - .../bindings/pinctrl/fsl,imx6q-pinctrl.txt | 1628 -------- .../bindings/pinctrl/fsl,mxs-pinctrl.txt | 918 ----- .../pinctrl/nvidia,tegra20-pinmux.txt | 132 - .../pinctrl/nvidia,tegra30-pinmux.txt | 132 - .../bindings/pinctrl/pinctrl-bindings.txt | 128 - .../bindings/pinctrl/pinctrl_spear.txt | 108 - .../bindings/pinmux/pinmux_nvidia.txt | 5 + trunk/Documentation/driver-model/devres.txt | 8 - trunk/Documentation/pinctrl.txt | 94 +- trunk/MAINTAINERS | 41 +- trunk/Makefile | 2 +- trunk/arch/arm/Kconfig | 1 - trunk/arch/arm/boot/dts/spear300-evb.dts | 200 +- trunk/arch/arm/boot/dts/spear300.dtsi | 5 - trunk/arch/arm/boot/dts/spear310-evb.dts | 61 - trunk/arch/arm/boot/dts/spear310.dtsi | 5 - trunk/arch/arm/boot/dts/spear320-evb.dts | 61 - trunk/arch/arm/boot/dts/spear320.dtsi | 7 +- trunk/arch/arm/boot/dts/spear3xx.dtsi | 6 + trunk/arch/arm/boot/dts/spear600.dtsi | 6 + trunk/arch/arm/configs/imx_v4_v5_defconfig | 1 - trunk/arch/arm/configs/u8500_defconfig | 9 +- trunk/arch/arm/mach-at91/at91rm9200_devices.c | 1 + trunk/arch/arm/mach-at91/at91rm9200_time.c | 2 - trunk/arch/arm/mach-at91/board-rm9200ek.c | 2 +- trunk/arch/arm/mach-at91/board-sam9261ek.c | 5 +- trunk/arch/arm/mach-at91/clock.c | 1 - .../arm/mach-at91/include/mach/at91_pmc.h | 2 +- trunk/arch/arm/mach-at91/setup.c | 2 - trunk/arch/arm/mach-bcmring/core.c | 4 +- trunk/arch/arm/mach-imx/imx27-dt.c | 6 +- trunk/arch/arm/mach-imx/mm-imx5.c | 2 +- trunk/arch/arm/mach-omap1/mux.c | 1 - trunk/arch/arm/mach-omap1/timer.c | 4 +- trunk/arch/arm/mach-omap2/board-4430sdp.c | 12 +- trunk/arch/arm/mach-omap2/board-generic.c | 2 +- trunk/arch/arm/mach-omap2/board-omap4panda.c | 13 +- trunk/arch/arm/mach-omap2/omap_hwmod.c | 17 +- .../arm/mach-omap2/omap_hwmod_2420_data.c | 1 + .../arm/mach-omap2/omap_hwmod_2430_data.c | 1 + .../arm/mach-omap2/omap_hwmod_3xxx_data.c | 1 + .../arm/mach-omap2/omap_hwmod_44xx_data.c | 9 - trunk/arch/arm/mach-omap2/serial.c | 124 +- trunk/arch/arm/mach-omap2/twl-common.c | 37 +- trunk/arch/arm/mach-omap2/twl-common.h | 10 +- trunk/arch/arm/mach-spear3xx/Kconfig | 3 - trunk/arch/arm/mach-spear3xx/Makefile | 2 +- trunk/arch/arm/mach-spear3xx/clock.c | 892 +++++ .../arm/mach-spear3xx/include/mach/generic.h | 158 +- .../arm/mach-spear3xx/include/mach/hardware.h | 21 +- .../arm/mach-spear3xx/include/mach/irqs.h | 131 +- .../mach-spear3xx/include/mach/misc_regs.h | 4 +- .../arm/mach-spear3xx/include/mach/spear.h | 50 +- .../arm/mach-spear3xx/include/mach/spear300.h | 54 - .../arm/mach-spear3xx/include/mach/spear310.h | 58 - .../arm/mach-spear3xx/include/mach/spear320.h | 67 - trunk/arch/arm/mach-spear3xx/spear300.c | 430 +- trunk/arch/arm/mach-spear3xx/spear310.c | 223 +- trunk/arch/arm/mach-spear3xx/spear320.c | 464 ++- trunk/arch/arm/mach-spear3xx/spear3xx.c | 431 +- trunk/arch/arm/mach-spear6xx/Makefile | 2 +- trunk/arch/arm/mach-spear6xx/clock.c | 789 ++++ .../arm/mach-spear6xx/include/mach/generic.h | 29 +- .../arm/mach-spear6xx/include/mach/hardware.h | 24 +- .../arm/mach-spear6xx/include/mach/irqs.h | 76 +- .../mach-spear6xx/include/mach/misc_regs.h | 4 +- .../arm/mach-spear6xx/include/mach/spear.h | 56 +- .../arm/mach-spear6xx/include/mach/spear600.h | 21 - trunk/arch/arm/mach-spear6xx/spear6xx.c | 54 +- trunk/arch/arm/mach-ux500/Kconfig | 1 - trunk/arch/arm/mach-ux500/platsmp.c | 2 +- .../arm/plat-omap/include/plat/omap_hwmod.h | 4 +- trunk/arch/arm/plat-omap/sram.c | 12 +- trunk/arch/arm/plat-spear/Kconfig | 1 - trunk/arch/arm/plat-spear/Makefile | 4 +- trunk/arch/arm/plat-spear/clock.c | 1005 +++++ .../arch/arm/plat-spear/include/plat/clock.h | 249 ++ .../arm/plat-spear/include/plat/debug-macro.S | 2 +- .../arm/plat-spear/include/plat/hardware.h | 17 - .../arch/arm/plat-spear/include/plat/padmux.h | 92 + .../arm/plat-spear/include/plat/uncompress.h | 2 +- trunk/arch/arm/plat-spear/padmux.c | 164 + trunk/arch/arm/plat-spear/pl080.c | 1 + trunk/arch/arm/plat-spear/restart.c | 2 +- trunk/arch/arm/plat-spear/time.c | 48 +- trunk/arch/ia64/include/asm/futex.h | 9 +- trunk/arch/ia64/kernel/perfmon.c | 18 +- trunk/arch/m68k/configs/m5275evb_defconfig | 1 + trunk/arch/m68k/platform/527x/config.c | 2 + trunk/arch/m68k/platform/68EZ328/Makefile | 6 + .../platform/{68VZ328 => 68EZ328}/bootlogo.h | 2 +- trunk/arch/m68k/platform/68VZ328/Makefile | 9 +- trunk/arch/m68k/platform/coldfire/device.c | 2 +- trunk/arch/s390/Kconfig | 1 + trunk/arch/s390/defconfig | 37 +- trunk/arch/s390/include/asm/facility.h | 3 +- trunk/arch/s390/include/asm/pgalloc.h | 3 + trunk/arch/s390/include/asm/swab.h | 2 +- trunk/arch/s390/include/asm/tlb.h | 22 +- trunk/arch/s390/kernel/head.S | 2 +- trunk/arch/s390/kernel/irq.c | 9 +- trunk/arch/s390/kernel/perf_cpum_cf.c | 4 +- trunk/arch/s390/mm/maccess.c | 27 +- trunk/arch/s390/mm/pgtable.c | 63 +- trunk/arch/sparc/kernel/leon_smp.c | 3 - trunk/arch/sparc/kernel/sys_sparc_64.c | 7 +- trunk/arch/tile/kernel/single_step.c | 4 +- trunk/arch/x86/ia32/ia32_aout.c | 32 +- trunk/arch/x86/kvm/pmu.c | 18 +- trunk/arch/x86/kvm/vmx.c | 5 +- trunk/arch/x86/kvm/x86.c | 8 +- trunk/arch/x86/lib/insn.c | 53 +- trunk/crypto/sha512_generic.c | 2 +- trunk/drivers/acpi/acpica/hwxface.c | 3 +- trunk/drivers/acpi/osl.c | 3 +- trunk/drivers/acpi/reboot.c | 3 +- trunk/drivers/ata/ata_piix.c | 2 - trunk/drivers/ata/libata-core.c | 4 +- trunk/drivers/ata/libata-scsi.c | 4 +- trunk/drivers/ata/libata-transport.c | 1 - trunk/drivers/ata/libata.h | 2 +- trunk/drivers/ata/sata_mv.c | 3 +- trunk/drivers/block/virtio_blk.c | 41 +- trunk/drivers/block/xen-blkback/xenbus.c | 2 +- trunk/drivers/clk/Kconfig | 12 +- trunk/drivers/clk/Makefile | 5 +- trunk/drivers/clk/clk-divider.c | 68 +- trunk/drivers/clk/clk-fixed-factor.c | 95 - trunk/drivers/clk/clk-fixed-rate.c | 49 +- trunk/drivers/clk/clk-gate.c | 104 +- trunk/drivers/clk/clk-mux.c | 27 +- trunk/drivers/clk/clk.c | 270 +- trunk/drivers/clk/clkdev.c | 142 +- trunk/drivers/clk/spear/Makefile | 8 - trunk/drivers/clk/spear/clk-aux-synth.c | 198 - trunk/drivers/clk/spear/clk-frac-synth.c | 165 - trunk/drivers/clk/spear/clk-gpt-synth.c | 154 - trunk/drivers/clk/spear/clk-vco-pll.c | 363 -- trunk/drivers/clk/spear/clk.c | 36 - trunk/drivers/clk/spear/clk.h | 134 - trunk/drivers/clk/spear/spear3xx_clock.c | 612 --- trunk/drivers/clk/spear/spear6xx_clock.c | 342 -- trunk/drivers/crypto/ixp4xx_crypto.c | 1 - trunk/drivers/crypto/talitos.c | 20 +- trunk/drivers/dma/Kconfig | 5 +- trunk/drivers/gpu/drm/drm_bufs.c | 12 +- trunk/drivers/gpu/drm/drm_crtc.c | 10 +- trunk/drivers/gpu/drm/drm_fops.c | 6 +- trunk/drivers/gpu/drm/drm_usb.c | 6 +- trunk/drivers/gpu/drm/exynos/exynos_drm_gem.c | 4 +- .../drivers/gpu/drm/gma500/mdfld_dsi_output.h | 1 + trunk/drivers/gpu/drm/i810/i810_dma.c | 6 +- trunk/drivers/gpu/drm/i915/i915_gem.c | 4 +- trunk/drivers/gpu/drm/i915/intel_display.c | 15 +- trunk/drivers/gpu/drm/i915/intel_drv.h | 4 - trunk/drivers/gpu/drm/i915/intel_fb.c | 4 - trunk/drivers/gpu/drm/i915/intel_lvds.c | 6 - trunk/drivers/gpu/drm/i915/intel_panel.c | 2 + trunk/drivers/gpu/drm/nouveau/nouveau_pm.c | 1 - trunk/drivers/gpu/drm/nouveau/nv50_sor.c | 2 +- trunk/drivers/gpu/drm/radeon/r600.c | 4 +- .../gpu/drm/radeon/radeon_connectors.c | 4 +- trunk/drivers/gpu/drm/radeon/radeon_irq_kms.c | 6 - trunk/drivers/gpu/drm/radeon/rv770.c | 4 +- trunk/drivers/gpu/drm/radeon/si.c | 5 +- trunk/drivers/hid/Kconfig | 2 +- trunk/drivers/hid/hid-tivo.c | 2 +- trunk/drivers/hwmon/ads1015.c | 33 +- trunk/drivers/hwmon/fam15h_power.c | 39 - trunk/drivers/input/misc/Kconfig | 3 +- trunk/drivers/input/misc/twl6040-vibra.c | 4 +- trunk/drivers/leds/leds-atmel-pwm.c | 2 +- trunk/drivers/media/common/tuners/xc5000.c | 39 +- trunk/drivers/media/common/tuners/xc5000.h | 1 - .../drivers/media/dvb/dvb-core/dvb_frontend.c | 25 +- trunk/drivers/media/dvb/frontends/drxk_hard.c | 6 +- trunk/drivers/media/rc/winbond-cir.c | 1 - trunk/drivers/media/video/Kconfig | 2 +- trunk/drivers/media/video/mt9m032.c | 5 +- trunk/drivers/mfd/Kconfig | 11 +- trunk/drivers/mfd/asic3.c | 4 +- trunk/drivers/mfd/omap-usb-host.c | 44 + trunk/drivers/mfd/rc5t583.c | 39 +- trunk/drivers/mfd/twl6040-core.c | 114 +- trunk/drivers/mmc/card/block.c | 56 +- trunk/drivers/mmc/card/queue.c | 2 +- trunk/drivers/mmc/core/bus.c | 24 +- trunk/drivers/mmc/core/cd-gpio.c | 1 - trunk/drivers/mmc/core/core.c | 64 +- trunk/drivers/mmc/host/dw_mmc.c | 7 +- trunk/drivers/mmc/host/omap_hsmmc.c | 6 +- trunk/drivers/mmc/host/sdhci-esdhc-imx.c | 3 +- trunk/drivers/mmc/host/sdhci.c | 2 +- trunk/drivers/of/address.c | 1 + trunk/drivers/of/base.c | 41 - trunk/drivers/pci/pci.c | 24 +- trunk/drivers/pinctrl/Kconfig | 31 +- trunk/drivers/pinctrl/Makefile | 10 - trunk/drivers/pinctrl/core.c | 263 +- trunk/drivers/pinctrl/core.h | 12 +- trunk/drivers/pinctrl/devicetree.c | 249 -- trunk/drivers/pinctrl/devicetree.h | 35 - trunk/drivers/pinctrl/pinconf.c | 52 +- trunk/drivers/pinctrl/pinconf.h | 17 +- trunk/drivers/pinctrl/pinctrl-coh901.c | 4 +- trunk/drivers/pinctrl/pinctrl-imx.c | 627 --- trunk/drivers/pinctrl/pinctrl-imx.h | 106 - trunk/drivers/pinctrl/pinctrl-imx23.c | 305 -- trunk/drivers/pinctrl/pinctrl-imx28.c | 421 -- trunk/drivers/pinctrl/pinctrl-imx6q.c | 2331 ----------- trunk/drivers/pinctrl/pinctrl-mxs.c | 508 --- trunk/drivers/pinctrl/pinctrl-mxs.h | 91 - trunk/drivers/pinctrl/pinctrl-pxa3xx.c | 24 +- trunk/drivers/pinctrl/pinctrl-sirf.c | 20 +- trunk/drivers/pinctrl/pinctrl-tegra.c | 245 +- trunk/drivers/pinctrl/pinctrl-u300.c | 20 +- trunk/drivers/pinctrl/pinmux.c | 93 +- trunk/drivers/pinctrl/pinmux.h | 18 +- trunk/drivers/pinctrl/spear/Kconfig | 34 - trunk/drivers/pinctrl/spear/Makefile | 7 - trunk/drivers/pinctrl/spear/pinctrl-spear.c | 354 -- trunk/drivers/pinctrl/spear/pinctrl-spear.h | 142 - .../drivers/pinctrl/spear/pinctrl-spear300.c | 708 ---- .../drivers/pinctrl/spear/pinctrl-spear310.c | 431 -- .../drivers/pinctrl/spear/pinctrl-spear320.c | 3468 ----------------- .../drivers/pinctrl/spear/pinctrl-spear3xx.c | 588 --- .../drivers/pinctrl/spear/pinctrl-spear3xx.h | 92 - trunk/drivers/s390/block/dasd_eckd.c | 24 +- trunk/drivers/s390/char/vmur.c | 2 +- trunk/drivers/tty/amiserial.c | 4 +- trunk/drivers/tty/serial/clps711x.c | 14 +- trunk/drivers/tty/serial/pch_uart.c | 4 +- trunk/drivers/usb/core/hub.c | 3 + trunk/drivers/usb/core/message.c | 6 +- trunk/drivers/usb/dwc3/core.c | 6 +- trunk/drivers/usb/dwc3/ep0.c | 12 +- trunk/drivers/usb/gadget/at91_udc.c | 8 +- trunk/drivers/usb/gadget/f_fs.c | 3 +- trunk/drivers/usb/gadget/f_rndis.c | 1 - trunk/drivers/usb/gadget/fsl_udc_core.c | 25 +- trunk/drivers/usb/gadget/g_ffs.c | 4 +- trunk/drivers/usb/gadget/s3c-hsotg.c | 17 +- trunk/drivers/usb/gadget/udc-core.c | 6 +- trunk/drivers/usb/gadget/uvc_queue.c | 4 +- trunk/drivers/usb/host/ehci-fsl.c | 7 +- trunk/drivers/usb/host/ehci-hcd.c | 9 +- trunk/drivers/usb/host/ehci-omap.c | 39 +- trunk/drivers/usb/host/ehci-tegra.c | 1 + trunk/drivers/usb/host/ohci-at91.c | 12 +- trunk/drivers/usb/misc/usbtest.c | 9 +- trunk/drivers/usb/misc/yurex.c | 10 +- trunk/drivers/usb/musb/musb_core.c | 40 +- trunk/drivers/usb/musb/musb_host.c | 2 +- trunk/drivers/usb/musb/omap2430.c | 31 +- trunk/drivers/usb/serial/cp210x.c | 9 +- trunk/drivers/usb/serial/sierra.c | 6 +- trunk/drivers/uwb/hwa-rc.c | 3 +- trunk/drivers/uwb/neh.c | 12 +- trunk/drivers/vhost/test.c | 2 +- trunk/drivers/virtio/virtio_balloon.c | 58 +- trunk/drivers/xen/gntdev.c | 2 +- trunk/drivers/xen/grant-table.c | 13 +- trunk/drivers/xen/manage.c | 1 - .../xen/xenbus/xenbus_probe_frontend.c | 69 +- trunk/fs/aio.c | 16 +- trunk/fs/binfmt_aout.c | 32 +- trunk/fs/binfmt_elf.c | 23 +- trunk/fs/binfmt_elf_fdpic.c | 18 +- trunk/fs/binfmt_flat.c | 12 +- trunk/fs/binfmt_som.c | 12 +- trunk/fs/btrfs/ctree.h | 2 +- trunk/fs/cifs/connect.c | 82 +- trunk/fs/ext4/ext4.h | 3 + trunk/fs/ext4/extents.c | 6 +- trunk/fs/ext4/super.c | 48 +- trunk/fs/fuse/dir.c | 25 +- trunk/fs/fuse/file.c | 129 +- trunk/fs/fuse/inode.c | 1 - trunk/fs/lockd/clnt4xdr.c | 2 +- trunk/fs/lockd/clntxdr.c | 2 +- trunk/fs/nfsd/nfs3xdr.c | 22 +- trunk/fs/nfsd/nfs4proc.c | 15 +- trunk/fs/nfsd/nfs4state.c | 23 +- trunk/fs/nfsd/nfs4xdr.c | 4 +- trunk/fs/nfsd/vfs.c | 2 +- trunk/fs/ocfs2/alloc.c | 2 +- trunk/fs/ocfs2/refcounttree.c | 12 +- trunk/fs/ocfs2/suballoc.c | 4 +- trunk/include/linux/clk-private.h | 99 +- trunk/include/linux/clk-provider.h | 118 +- trunk/include/linux/clk.h | 38 +- trunk/include/linux/clkdev.h | 3 - trunk/include/linux/fuse.h | 2 +- trunk/include/linux/i2c/twl.h | 12 + trunk/include/linux/kvm_host.h | 6 - trunk/include/linux/mfd/db5500-prcmu.h | 88 +- trunk/include/linux/mfd/rc5t583.h | 47 +- trunk/include/linux/mfd/twl6040.h | 27 - trunk/include/linux/mm.h | 27 +- trunk/include/linux/mmc/card.h | 2 +- trunk/include/linux/nfsd/Kbuild | 1 - trunk/include/linux/of.h | 51 - trunk/include/linux/pinctrl/consumer.h | 44 - trunk/include/linux/pinctrl/machine.h | 11 +- trunk/include/linux/pinctrl/pinconf.h | 6 +- trunk/include/linux/pinctrl/pinctrl.h | 22 +- trunk/include/linux/pinctrl/pinmux.h | 9 +- trunk/include/linux/usb/otg.h | 1 - trunk/lib/mpi/mpi-bit.c | 5 +- trunk/mm/memblock.c | 7 +- trunk/mm/memcontrol.c | 1 - trunk/mm/mmap.c | 59 +- trunk/mm/nommu.c | 41 +- trunk/scripts/checkpatch.pl | 6 + trunk/scripts/xz_wrap.sh | 4 +- trunk/security/commoncap.c | 6 - trunk/security/smack/smack_lsm.c | 44 +- trunk/security/smack/smackfs.c | 14 + trunk/sound/core/vmaster.c | 1 - trunk/sound/last.c | 2 +- trunk/sound/pci/hda/patch_conexant.c | 35 +- trunk/sound/pci/hda/patch_realtek.c | 49 +- trunk/sound/pci/hda/patch_sigmatel.c | 5 +- trunk/sound/soc/codecs/Kconfig | 3 +- trunk/sound/soc/codecs/twl6040.c | 3 +- trunk/sound/soc/omap/Kconfig | 2 +- trunk/tools/perf/.gitignore | 2 - trunk/tools/perf/Makefile | 21 +- trunk/tools/perf/perf-archive.sh | 3 +- trunk/tools/perf/util/session.c | 4 +- trunk/virt/kvm/iommu.c | 30 +- trunk/virt/kvm/kvm_main.c | 5 +- 337 files changed, 6912 insertions(+), 19865 deletions(-) create mode 100644 trunk/Documentation/devicetree/bindings/arm/spear-timer.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt delete mode 100644 trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt create mode 100644 trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt create mode 100644 trunk/arch/arm/mach-spear3xx/clock.c delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear300.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear310.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear320.h create mode 100644 trunk/arch/arm/mach-spear6xx/clock.c delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/spear600.h create mode 100644 trunk/arch/arm/plat-spear/clock.c create mode 100644 trunk/arch/arm/plat-spear/include/plat/clock.h delete mode 100644 trunk/arch/arm/plat-spear/include/plat/hardware.h create mode 100644 trunk/arch/arm/plat-spear/include/plat/padmux.h create mode 100644 trunk/arch/arm/plat-spear/padmux.c rename trunk/arch/m68k/platform/{68VZ328 => 68EZ328}/bootlogo.h (99%) delete mode 100644 trunk/drivers/clk/clk-fixed-factor.c delete mode 100644 trunk/drivers/clk/spear/Makefile delete mode 100644 trunk/drivers/clk/spear/clk-aux-synth.c delete mode 100644 trunk/drivers/clk/spear/clk-frac-synth.c delete mode 100644 trunk/drivers/clk/spear/clk-gpt-synth.c delete mode 100644 trunk/drivers/clk/spear/clk-vco-pll.c delete mode 100644 trunk/drivers/clk/spear/clk.c delete mode 100644 trunk/drivers/clk/spear/clk.h delete mode 100644 trunk/drivers/clk/spear/spear3xx_clock.c delete mode 100644 trunk/drivers/clk/spear/spear6xx_clock.c delete mode 100644 trunk/drivers/pinctrl/devicetree.c delete mode 100644 trunk/drivers/pinctrl/devicetree.h delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx.h delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx23.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx28.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-imx6q.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-mxs.c delete mode 100644 trunk/drivers/pinctrl/pinctrl-mxs.h delete mode 100644 trunk/drivers/pinctrl/spear/Kconfig delete mode 100644 trunk/drivers/pinctrl/spear/Makefile delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear.h delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear300.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear310.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear320.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c delete mode 100644 trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h diff --git a/[refs] b/[refs] index b6611d06beaf..e0458058bac9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d2819f80d465672b09c2f4cb52303b7f951c4d0f +refs/heads/master: 30551c0108e0d2fed48778a6bbd52843088bcb7b diff --git a/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml b/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml index 5274c24d11e0..3fd3ce5df270 100644 --- a/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml +++ b/trunk/Documentation/DocBook/media/v4l/pixfmt-nv12m.xml @@ -1,6 +1,6 @@ - V4L2_PIX_FMT_NV12M ('NM12') + V4L2_PIX_FMT_NV12M ('NV12M') &manvol; diff --git a/trunk/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml b/trunk/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml index 60308f1eefdf..9957863daf18 100644 --- a/trunk/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml +++ b/trunk/Documentation/DocBook/media/v4l/pixfmt-yuv420m.xml @@ -1,6 +1,6 @@ - V4L2_PIX_FMT_YUV420M ('YM12') + V4L2_PIX_FMT_YUV420M ('YU12M') &manvol; diff --git a/trunk/Documentation/devicetree/bindings/arm/spear-timer.txt b/trunk/Documentation/devicetree/bindings/arm/spear-timer.txt new file mode 100644 index 000000000000..c0017221cf55 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/arm/spear-timer.txt @@ -0,0 +1,18 @@ +* SPEAr ARM Timer + +** Timer node required properties: + +- compatible : Should be: + "st,spear-timer" +- reg: Address range of the timer registers +- interrupt-parent: Should be the phandle for the interrupt controller + that services interrupts for this device +- interrupt: Should contain the timer interrupt number + +Example: + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt deleted file mode 100644 index ab19e6bc7d3b..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt +++ /dev/null @@ -1,95 +0,0 @@ -* Freescale IOMUX Controller (IOMUXC) for i.MX - -The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC -to share one PAD to several functional blocks. The sharing is done by -multiplexing the PAD input/output signals. For each PAD there are up to -8 muxing options (called ALT modes). Since different modules require -different PAD settings (like pull up, keeper, etc) the IOMUXC controls -also the PAD settings parameters. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Freescale IMX pin configuration node is a node of a group of pins which can be -used for a specific device or function. This node represents both mux and config -of the pins in that group. The 'mux' selects the function mode(also named mux -mode) this pin can work on and the 'config' configures various pad settings -such as pull-up, open drain, drive strength, etc. - -Required properties for iomux controller: -- compatible: "fsl,-iomuxc" - Please refer to each fsl,-pinctrl.txt binding doc for supported SoCs. - -Required properties for pin configuration node: -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up on this pin. Please refer to fsl,-pinctrl.txt for the valid - pins and functions of each SoC. - -Bits used for CONFIG: -NO_PAD_CTL(1 << 31): indicate this pin does not need config. - -SION(1 << 30): Software Input On Field. -Force the selected mux mode input path no matter of MUX_MODE functionality. -By default the input path is determined by functionality of the selected -mux mode (regular). - -Other bits are used for PAD setting. -Please refer to each fsl,-pinctrl,txt binding doc for SoC specific part -of bits definitions. - -NOTE: -Some requirements for using fsl,imx-pinctrl binding: -1. We have pin function node defined under iomux controller node to represent - what pinmux functions this SoC supports. -2. The pin configuration node intends to work on a specific function should - to be defined under that specific function node. - The function node's name should represent well about what function - this group of pins in this pin configuration node are working on. -3. The driver can use the function node's name and pin configuration node's - name describe the pin function and group hierarchy. - For example, Linux IMX pinctrl driver takes the function node's name - as the function name and pin configuration node's name as group name to - create the map table. -4. Each pin configuration node should have a phandle, devices can set pins - configurations by referring to the phandle of that pin configuration node. - -Examples: -usdhc@0219c000 { /* uSDHC4 */ - fsl,card-wired; - vmmc-supply = <®_3p3v>; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4_1>; -}; - -iomuxc@020e0000 { - compatible = "fsl,imx6q-iomuxc"; - reg = <0x020e0000 0x4000>; - - /* shared pinctrl settings */ - usdhc4 { - pinctrl_usdhc4_1: usdhc4grp-1 { - fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - }; - }; - .... -}; -Refer to the IOMUXC controller chapter in imx6q datasheet, -0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, -80Ohm driver strength and Fast Slew Rate. -User should refer to each SoC spec to set the correct value. - -TODO: when dtc macro support is available, we can change above raw data -to dt macro which can get better readability in dts file. diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt deleted file mode 100644 index 82b43f915857..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt +++ /dev/null @@ -1,1628 +0,0 @@ -* Freescale IMX6Q IOMUX Controller - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx6q-iomuxc" -- fsl,pins: two integers array, represents a group of pins mux and config - setting. The format is fsl,pins = , PIN_FUNC_ID is a - pin working on a specific function, CONFIG is the pad setting value like - pull-up for this pin. Please refer to imx6q datasheet for the valid pad - config settings. - -CONFIG bits definition: -PAD_CTL_HYS (1 << 16) -PAD_CTL_PUS_100K_DOWN (0 << 14) -PAD_CTL_PUS_47K_UP (1 << 14) -PAD_CTL_PUS_100K_UP (2 << 14) -PAD_CTL_PUS_22K_UP (3 << 14) -PAD_CTL_PUE (1 << 13) -PAD_CTL_PKE (1 << 12) -PAD_CTL_ODE (1 << 11) -PAD_CTL_SPEED_LOW (1 << 6) -PAD_CTL_SPEED_MED (2 << 6) -PAD_CTL_SPEED_HIGH (3 << 6) -PAD_CTL_DSE_DISABLE (0 << 3) -PAD_CTL_DSE_240ohm (1 << 3) -PAD_CTL_DSE_120ohm (2 << 3) -PAD_CTL_DSE_80ohm (3 << 3) -PAD_CTL_DSE_60ohm (4 << 3) -PAD_CTL_DSE_48ohm (5 << 3) -PAD_CTL_DSE_40ohm (6 << 3) -PAD_CTL_DSE_34ohm (7 << 3) -PAD_CTL_SRE_FAST (1 << 0) -PAD_CTL_SRE_SLOW (0 << 0) - -See below for available PIN_FUNC_ID for imx6q: -MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 0 -MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 1 -MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 2 -MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS 3 -MX6Q_PAD_SD2_DAT1__KPP_COL_7 4 -MX6Q_PAD_SD2_DAT1__GPIO_1_14 5 -MX6Q_PAD_SD2_DAT1__CCM_WAIT 6 -MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 7 -MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 8 -MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 9 -MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 10 -MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD 11 -MX6Q_PAD_SD2_DAT2__KPP_ROW_6 12 -MX6Q_PAD_SD2_DAT2__GPIO_1_13 13 -MX6Q_PAD_SD2_DAT2__CCM_STOP 14 -MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 15 -MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 16 -MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 17 -MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD 18 -MX6Q_PAD_SD2_DAT0__KPP_ROW_7 19 -MX6Q_PAD_SD2_DAT0__GPIO_1_15 20 -MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT 21 -MX6Q_PAD_SD2_DAT0__TESTO_2 22 -MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA 23 -MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC 24 -MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK 25 -MX6Q_PAD_RGMII_TXC__GPIO_6_19 26 -MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 27 -MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT 28 -MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY 29 -MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 30 -MX6Q_PAD_RGMII_TD0__GPIO_6_20 31 -MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 32 -MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG 33 -MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 34 -MX6Q_PAD_RGMII_TD1__GPIO_6_21 35 -MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 36 -MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP 37 -MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA 38 -MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 39 -MX6Q_PAD_RGMII_TD2__GPIO_6_22 40 -MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 41 -MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP 42 -MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK 43 -MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 44 -MX6Q_PAD_RGMII_TD3__GPIO_6_23 45 -MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 46 -MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA 47 -MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 48 -MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 49 -MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 50 -MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY 51 -MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 52 -MX6Q_PAD_RGMII_RD0__GPIO_6_25 53 -MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 54 -MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE 55 -MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 56 -MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 57 -MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 58 -MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT 59 -MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL 60 -MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 61 -MX6Q_PAD_RGMII_RD1__GPIO_6_27 62 -MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 63 -MX6Q_PAD_RGMII_RD1__SJC_FAIL 64 -MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA 65 -MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 66 -MX6Q_PAD_RGMII_RD2__GPIO_6_28 67 -MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 68 -MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK 69 -MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 70 -MX6Q_PAD_RGMII_RD3__GPIO_6_29 71 -MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 72 -MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE 73 -MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC 74 -MX6Q_PAD_RGMII_RXC__GPIO_6_30 75 -MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 76 -MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 77 -MX6Q_PAD_EIM_A25__ECSPI4_SS1 78 -MX6Q_PAD_EIM_A25__ECSPI2_RDY 79 -MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 80 -MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 81 -MX6Q_PAD_EIM_A25__GPIO_5_2 82 -MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 83 -MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 84 -MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 85 -MX6Q_PAD_EIM_EB2__ECSPI1_SS0 86 -MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK 87 -MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 88 -MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 89 -MX6Q_PAD_EIM_EB2__GPIO_2_30 90 -MX6Q_PAD_EIM_EB2__I2C2_SCL 91 -MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 92 -MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 93 -MX6Q_PAD_EIM_D16__ECSPI1_SCLK 94 -MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 95 -MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 96 -MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 97 -MX6Q_PAD_EIM_D16__GPIO_3_16 98 -MX6Q_PAD_EIM_D16__I2C2_SDA 99 -MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 100 -MX6Q_PAD_EIM_D17__ECSPI1_MISO 101 -MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 102 -MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 103 -MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT 104 -MX6Q_PAD_EIM_D17__GPIO_3_17 105 -MX6Q_PAD_EIM_D17__I2C3_SCL 106 -MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 107 -MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 108 -MX6Q_PAD_EIM_D18__ECSPI1_MOSI 109 -MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 110 -MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 111 -MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 112 -MX6Q_PAD_EIM_D18__GPIO_3_18 113 -MX6Q_PAD_EIM_D18__I2C3_SDA 114 -MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 115 -MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 116 -MX6Q_PAD_EIM_D19__ECSPI1_SS1 117 -MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 118 -MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 119 -MX6Q_PAD_EIM_D19__UART1_CTS 120 -MX6Q_PAD_EIM_D19__GPIO_3_19 121 -MX6Q_PAD_EIM_D19__EPIT1_EPITO 122 -MX6Q_PAD_EIM_D19__PL301_PER1_HRESP 123 -MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 124 -MX6Q_PAD_EIM_D20__ECSPI4_SS0 125 -MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 126 -MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 127 -MX6Q_PAD_EIM_D20__UART1_RTS 128 -MX6Q_PAD_EIM_D20__GPIO_3_20 129 -MX6Q_PAD_EIM_D20__EPIT2_EPITO 130 -MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 131 -MX6Q_PAD_EIM_D21__ECSPI4_SCLK 132 -MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 133 -MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 134 -MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC 135 -MX6Q_PAD_EIM_D21__GPIO_3_21 136 -MX6Q_PAD_EIM_D21__I2C1_SCL 137 -MX6Q_PAD_EIM_D21__SPDIF_IN1 138 -MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 139 -MX6Q_PAD_EIM_D22__ECSPI4_MISO 140 -MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 141 -MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 142 -MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR 143 -MX6Q_PAD_EIM_D22__GPIO_3_22 144 -MX6Q_PAD_EIM_D22__SPDIF_OUT1 145 -MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE 146 -MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 147 -MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 148 -MX6Q_PAD_EIM_D23__UART3_CTS 149 -MX6Q_PAD_EIM_D23__UART1_DCD 150 -MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 151 -MX6Q_PAD_EIM_D23__GPIO_3_23 152 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 153 -MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 154 -MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 155 -MX6Q_PAD_EIM_EB3__ECSPI4_RDY 156 -MX6Q_PAD_EIM_EB3__UART3_RTS 157 -MX6Q_PAD_EIM_EB3__UART1_RI 158 -MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 159 -MX6Q_PAD_EIM_EB3__GPIO_2_31 160 -MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 161 -MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 162 -MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 163 -MX6Q_PAD_EIM_D24__ECSPI4_SS2 164 -MX6Q_PAD_EIM_D24__UART3_TXD 165 -MX6Q_PAD_EIM_D24__ECSPI1_SS2 166 -MX6Q_PAD_EIM_D24__ECSPI2_SS2 167 -MX6Q_PAD_EIM_D24__GPIO_3_24 168 -MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS 169 -MX6Q_PAD_EIM_D24__UART1_DTR 170 -MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 171 -MX6Q_PAD_EIM_D25__ECSPI4_SS3 172 -MX6Q_PAD_EIM_D25__UART3_RXD 173 -MX6Q_PAD_EIM_D25__ECSPI1_SS3 174 -MX6Q_PAD_EIM_D25__ECSPI2_SS3 175 -MX6Q_PAD_EIM_D25__GPIO_3_25 176 -MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC 177 -MX6Q_PAD_EIM_D25__UART1_DSR 178 -MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 179 -MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 180 -MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 181 -MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 182 -MX6Q_PAD_EIM_D26__UART2_TXD 183 -MX6Q_PAD_EIM_D26__GPIO_3_26 184 -MX6Q_PAD_EIM_D26__IPU1_SISG_2 185 -MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 186 -MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 187 -MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 188 -MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 189 -MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 190 -MX6Q_PAD_EIM_D27__UART2_RXD 191 -MX6Q_PAD_EIM_D27__GPIO_3_27 192 -MX6Q_PAD_EIM_D27__IPU1_SISG_3 193 -MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 194 -MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 195 -MX6Q_PAD_EIM_D28__I2C1_SDA 196 -MX6Q_PAD_EIM_D28__ECSPI4_MOSI 197 -MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 198 -MX6Q_PAD_EIM_D28__UART2_CTS 199 -MX6Q_PAD_EIM_D28__GPIO_3_28 200 -MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 201 -MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 202 -MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 203 -MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 204 -MX6Q_PAD_EIM_D29__ECSPI4_SS0 205 -MX6Q_PAD_EIM_D29__UART2_RTS 206 -MX6Q_PAD_EIM_D29__GPIO_3_29 207 -MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 208 -MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 209 -MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 210 -MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 211 -MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 212 -MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 213 -MX6Q_PAD_EIM_D30__UART3_CTS 214 -MX6Q_PAD_EIM_D30__GPIO_3_30 215 -MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC 216 -MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 217 -MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 218 -MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 219 -MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 220 -MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 221 -MX6Q_PAD_EIM_D31__UART3_RTS 222 -MX6Q_PAD_EIM_D31__GPIO_3_31 223 -MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR 224 -MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 225 -MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 226 -MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 227 -MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 228 -MX6Q_PAD_EIM_A24__IPU2_SISG_2 229 -MX6Q_PAD_EIM_A24__IPU1_SISG_2 230 -MX6Q_PAD_EIM_A24__GPIO_5_4 231 -MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 232 -MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 233 -MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 234 -MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 235 -MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 236 -MX6Q_PAD_EIM_A23__IPU2_SISG_3 237 -MX6Q_PAD_EIM_A23__IPU1_SISG_3 238 -MX6Q_PAD_EIM_A23__GPIO_6_6 239 -MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 240 -MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 241 -MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 242 -MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 243 -MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 244 -MX6Q_PAD_EIM_A22__GPIO_2_16 245 -MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 246 -MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 247 -MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 248 -MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 249 -MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 250 -MX6Q_PAD_EIM_A21__RESERVED_RESERVED 251 -MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 252 -MX6Q_PAD_EIM_A21__GPIO_2_17 253 -MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 254 -MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 255 -MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 256 -MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 257 -MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 258 -MX6Q_PAD_EIM_A20__RESERVED_RESERVED 259 -MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 260 -MX6Q_PAD_EIM_A20__GPIO_2_18 261 -MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 262 -MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 263 -MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 264 -MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 265 -MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 266 -MX6Q_PAD_EIM_A19__RESERVED_RESERVED 267 -MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 268 -MX6Q_PAD_EIM_A19__GPIO_2_19 269 -MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 270 -MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 271 -MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 272 -MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 273 -MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 274 -MX6Q_PAD_EIM_A18__RESERVED_RESERVED 275 -MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 276 -MX6Q_PAD_EIM_A18__GPIO_2_20 277 -MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 278 -MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 279 -MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 280 -MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 281 -MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 282 -MX6Q_PAD_EIM_A17__RESERVED_RESERVED 283 -MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 284 -MX6Q_PAD_EIM_A17__GPIO_2_21 285 -MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 286 -MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 287 -MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 288 -MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 289 -MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 290 -MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 291 -MX6Q_PAD_EIM_A16__GPIO_2_22 292 -MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 293 -MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 294 -MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 295 -MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 296 -MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 297 -MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 298 -MX6Q_PAD_EIM_CS0__GPIO_2_23 299 -MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 300 -MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 301 -MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 302 -MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 303 -MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 304 -MX6Q_PAD_EIM_CS1__GPIO_2_24 305 -MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 306 -MX6Q_PAD_EIM_OE__WEIM_WEIM_OE 307 -MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 308 -MX6Q_PAD_EIM_OE__ECSPI2_MISO 309 -MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 310 -MX6Q_PAD_EIM_OE__GPIO_2_25 311 -MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 312 -MX6Q_PAD_EIM_RW__WEIM_WEIM_RW 313 -MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 314 -MX6Q_PAD_EIM_RW__ECSPI2_SS0 315 -MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 316 -MX6Q_PAD_EIM_RW__GPIO_2_26 317 -MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 318 -MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 319 -MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA 320 -MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 321 -MX6Q_PAD_EIM_LBA__ECSPI2_SS1 322 -MX6Q_PAD_EIM_LBA__GPIO_2_27 323 -MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 324 -MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 325 -MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 326 -MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 327 -MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 328 -MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 329 -MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY 330 -MX6Q_PAD_EIM_EB0__GPIO_2_28 331 -MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 332 -MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 333 -MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 334 -MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 335 -MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 336 -MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 337 -MX6Q_PAD_EIM_EB1__GPIO_2_29 338 -MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 339 -MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 340 -MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 341 -MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 342 -MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 343 -MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 344 -MX6Q_PAD_EIM_DA0__GPIO_3_0 345 -MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 346 -MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 347 -MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 348 -MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 349 -MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 350 -MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 351 -MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE 352 -MX6Q_PAD_EIM_DA1__GPIO_3_1 353 -MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 354 -MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 355 -MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 356 -MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 357 -MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 358 -MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 359 -MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE 360 -MX6Q_PAD_EIM_DA2__GPIO_3_2 361 -MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 362 -MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 363 -MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 364 -MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 365 -MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 366 -MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 367 -MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ 368 -MX6Q_PAD_EIM_DA3__GPIO_3_3 369 -MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 370 -MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 371 -MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 372 -MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 373 -MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 374 -MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 375 -MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN 376 -MX6Q_PAD_EIM_DA4__GPIO_3_4 377 -MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 378 -MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 379 -MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 380 -MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 381 -MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 382 -MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 383 -MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP 384 -MX6Q_PAD_EIM_DA5__GPIO_3_5 385 -MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 386 -MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 387 -MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 388 -MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 389 -MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 390 -MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 391 -MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN 392 -MX6Q_PAD_EIM_DA6__GPIO_3_6 393 -MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 394 -MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 395 -MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 396 -MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 397 -MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 398 -MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 399 -MX6Q_PAD_EIM_DA7__GPIO_3_7 400 -MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 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-MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 944 -MX6Q_PAD_KEY_ROW4__CAN2_RXCAN 945 -MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 946 -MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR 947 -MX6Q_PAD_KEY_ROW4__KPP_ROW_4 948 -MX6Q_PAD_KEY_ROW4__UART5_CTS 949 -MX6Q_PAD_KEY_ROW4__GPIO_4_15 950 -MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 951 -MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 952 -MX6Q_PAD_GPIO_0__CCM_CLKO 953 -MX6Q_PAD_GPIO_0__KPP_COL_5 954 -MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK 955 -MX6Q_PAD_GPIO_0__EPIT1_EPITO 956 -MX6Q_PAD_GPIO_0__GPIO_1_0 957 -MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR 958 -MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 959 -MX6Q_PAD_GPIO_1__ESAI1_SCKR 960 -MX6Q_PAD_GPIO_1__WDOG2_WDOG_B 961 -MX6Q_PAD_GPIO_1__KPP_ROW_5 962 -MX6Q_PAD_GPIO_1__PWM2_PWMO 963 -MX6Q_PAD_GPIO_1__GPIO_1_1 964 -MX6Q_PAD_GPIO_1__USDHC1_CD 965 -MX6Q_PAD_GPIO_1__SRC_TESTER_ACK 966 -MX6Q_PAD_GPIO_9__ESAI1_FSR 967 -MX6Q_PAD_GPIO_9__WDOG1_WDOG_B 968 -MX6Q_PAD_GPIO_9__KPP_COL_6 969 -MX6Q_PAD_GPIO_9__CCM_REF_EN_B 970 -MX6Q_PAD_GPIO_9__PWM1_PWMO 971 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--git a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index f7e8e8f4d9a3..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null @@ -1,918 +0,0 @@ -* Freescale MXS Pin Controller - -The pins controlled by mxs pin controller are organized in banks, each bank -has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th -function is GPIO. The configuration on the pins includes drive strength, -voltage and pull-up. - -Required properties: -- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" -- reg: Should contain the register physical address and length for the - pin controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -The node of mxs pin controller acts as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for -a group of pins, and only affects those parameters that are explicitly listed. -In other words, a subnode that describes a drive strength parameter implies no -information about pull-up. For this reason, even seemingly boolean values are -actually tristates in this binding: unspecified, off, or on. Unspecified is -represented as an absent property, and off/on are represented as integer -values 0 and 1. - -Those subnodes under mxs pin controller node will fall into two categories. -One is to set up a group of pins for a function, both mux selection and pin -configurations, and it's called group node in the binding document. The other -one is to adjust the pin configuration for some particular pins that need a -different configuration than what is defined in group node. The binding -document calls this type of node config node. - -On mxs, there is no hardware pin group. The pin group in this binding only -means a group of pins put together for particular peripheral to work in -particular function, like SSP0 functioning as mmc0-8bit. That said, the -group node should include all the pins needed for one function rather than -having these pins defined in several group nodes. It also means each of -"pinctrl-*" phandle in client device node should only have one group node -pointed in there, while the phandle can have multiple config node referenced -there to adjust configurations for some pins in the group. - -Required subnode-properties: -- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin - with given mux function, with bank, pin and mux packed as below. - - [15..12] : bank number - [11..4] : pin number - [3..0] : mux selection - - This integer with mux selection packed is used as an entity by both group - and config nodes to identify a pin. The mux selection in the integer takes - effects only on group node, and will get ignored by driver with config node, - since config node is only meant to set up pin configurations. - - Valid values for these integers are listed below. - -- reg: Should be the index of the group nodes for same function. This property - is required only for group nodes, and should not be present in any config - nodes. - -Optional subnode-properties: -- fsl,drive-strength: Integer. - 0: 4 mA - 1: 8 mA - 2: 12 mA - 3: 16 mA -- fsl,voltage: Integer. - 0: 1.8 V - 1: 3.3 V -- fsl,pull-up: Integer. - 0: Disable the internal pull-up - 1: Enable the internal pull-up - -Examples: - -pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; - reg = <0x80018000 2000>; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x2000 0x2010 0x2020 0x2030 - 0x2040 0x2050 0x2060 0x2070 - 0x2080 0x2090 0x20a0>; - fsl,drive-strength = <1>; - fsl,voltage = <1>; - fsl,pull-up = <1>; - }; - - mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = <0x2090>; - fsl,pull-up = <0>; - }; - - mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = <0x20a0>; - fsl,drive-strength = <2>; - fsl,pull-up = <0>; - }; -}; - -In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 -to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations -applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are -adjusting the configuration for pins card-detection and clock from what group -node mmc0-8bit defines. Only the configuration properties to be adjusted need -to be listed in the config nodes. - -Valid values for i.MX28 pinmux-id: - -pinmux id ------- -- -MX28_PAD_GPMI_D00__GPMI_D0 0x0000 -MX28_PAD_GPMI_D01__GPMI_D1 0x0010 -MX28_PAD_GPMI_D02__GPMI_D2 0x0020 -MX28_PAD_GPMI_D03__GPMI_D3 0x0030 -MX28_PAD_GPMI_D04__GPMI_D4 0x0040 -MX28_PAD_GPMI_D05__GPMI_D5 0x0050 -MX28_PAD_GPMI_D06__GPMI_D6 0x0060 -MX28_PAD_GPMI_D07__GPMI_D7 0x0070 -MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 -MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 -MX28_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX28_PAD_GPMI_CE3N__GPMI_CE3N 0x0130 -MX28_PAD_GPMI_RDY0__GPMI_READY0 0x0140 -MX28_PAD_GPMI_RDY1__GPMI_READY1 0x0150 -MX28_PAD_GPMI_RDY2__GPMI_READY2 0x0160 -MX28_PAD_GPMI_RDY3__GPMI_READY3 0x0170 -MX28_PAD_GPMI_RDN__GPMI_RDN 0x0180 -MX28_PAD_GPMI_WRN__GPMI_WRN 0x0190 -MX28_PAD_GPMI_ALE__GPMI_ALE 0x01a0 -MX28_PAD_GPMI_CLE__GPMI_CLE 0x01b0 -MX28_PAD_GPMI_RESETN__GPMI_RESETN 0x01c0 -MX28_PAD_LCD_D00__LCD_D0 0x1000 -MX28_PAD_LCD_D01__LCD_D1 0x1010 -MX28_PAD_LCD_D02__LCD_D2 0x1020 -MX28_PAD_LCD_D03__LCD_D3 0x1030 -MX28_PAD_LCD_D04__LCD_D4 0x1040 -MX28_PAD_LCD_D05__LCD_D5 0x1050 -MX28_PAD_LCD_D06__LCD_D6 0x1060 -MX28_PAD_LCD_D07__LCD_D7 0x1070 -MX28_PAD_LCD_D08__LCD_D8 0x1080 -MX28_PAD_LCD_D09__LCD_D9 0x1090 -MX28_PAD_LCD_D10__LCD_D10 0x10a0 -MX28_PAD_LCD_D11__LCD_D11 0x10b0 -MX28_PAD_LCD_D12__LCD_D12 0x10c0 -MX28_PAD_LCD_D13__LCD_D13 0x10d0 -MX28_PAD_LCD_D14__LCD_D14 0x10e0 -MX28_PAD_LCD_D15__LCD_D15 0x10f0 -MX28_PAD_LCD_D16__LCD_D16 0x1100 -MX28_PAD_LCD_D17__LCD_D17 0x1110 -MX28_PAD_LCD_D18__LCD_D18 0x1120 -MX28_PAD_LCD_D19__LCD_D19 0x1130 -MX28_PAD_LCD_D20__LCD_D20 0x1140 -MX28_PAD_LCD_D21__LCD_D21 0x1150 -MX28_PAD_LCD_D22__LCD_D22 0x1160 -MX28_PAD_LCD_D23__LCD_D23 0x1170 -MX28_PAD_LCD_RD_E__LCD_RD_E 0x1180 -MX28_PAD_LCD_WR_RWN__LCD_WR_RWN 0x1190 -MX28_PAD_LCD_RS__LCD_RS 0x11a0 -MX28_PAD_LCD_CS__LCD_CS 0x11b0 -MX28_PAD_LCD_VSYNC__LCD_VSYNC 0x11c0 -MX28_PAD_LCD_HSYNC__LCD_HSYNC 0x11d0 -MX28_PAD_LCD_DOTCLK__LCD_DOTCLK 0x11e0 -MX28_PAD_LCD_ENABLE__LCD_ENABLE 0x11f0 -MX28_PAD_SSP0_DATA0__SSP0_D0 0x2000 -MX28_PAD_SSP0_DATA1__SSP0_D1 0x2010 -MX28_PAD_SSP0_DATA2__SSP0_D2 0x2020 -MX28_PAD_SSP0_DATA3__SSP0_D3 0x2030 -MX28_PAD_SSP0_DATA4__SSP0_D4 0x2040 -MX28_PAD_SSP0_DATA5__SSP0_D5 0x2050 -MX28_PAD_SSP0_DATA6__SSP0_D6 0x2060 -MX28_PAD_SSP0_DATA7__SSP0_D7 0x2070 -MX28_PAD_SSP0_CMD__SSP0_CMD 0x2080 -MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 0x2090 -MX28_PAD_SSP0_SCK__SSP0_SCK 0x20a0 -MX28_PAD_SSP1_SCK__SSP1_SCK 0x20c0 -MX28_PAD_SSP1_CMD__SSP1_CMD 0x20d0 -MX28_PAD_SSP1_DATA0__SSP1_D0 0x20e0 -MX28_PAD_SSP1_DATA3__SSP1_D3 0x20f0 -MX28_PAD_SSP2_SCK__SSP2_SCK 0x2100 -MX28_PAD_SSP2_MOSI__SSP2_CMD 0x2110 -MX28_PAD_SSP2_MISO__SSP2_D0 0x2120 -MX28_PAD_SSP2_SS0__SSP2_D3 0x2130 -MX28_PAD_SSP2_SS1__SSP2_D4 0x2140 -MX28_PAD_SSP2_SS2__SSP2_D5 0x2150 -MX28_PAD_SSP3_SCK__SSP3_SCK 0x2180 -MX28_PAD_SSP3_MOSI__SSP3_CMD 0x2190 -MX28_PAD_SSP3_MISO__SSP3_D0 0x21a0 -MX28_PAD_SSP3_SS0__SSP3_D3 0x21b0 -MX28_PAD_AUART0_RX__AUART0_RX 0x3000 -MX28_PAD_AUART0_TX__AUART0_TX 0x3010 -MX28_PAD_AUART0_CTS__AUART0_CTS 0x3020 -MX28_PAD_AUART0_RTS__AUART0_RTS 0x3030 -MX28_PAD_AUART1_RX__AUART1_RX 0x3040 -MX28_PAD_AUART1_TX__AUART1_TX 0x3050 -MX28_PAD_AUART1_CTS__AUART1_CTS 0x3060 -MX28_PAD_AUART1_RTS__AUART1_RTS 0x3070 -MX28_PAD_AUART2_RX__AUART2_RX 0x3080 -MX28_PAD_AUART2_TX__AUART2_TX 0x3090 -MX28_PAD_AUART2_CTS__AUART2_CTS 0x30a0 -MX28_PAD_AUART2_RTS__AUART2_RTS 0x30b0 -MX28_PAD_AUART3_RX__AUART3_RX 0x30c0 -MX28_PAD_AUART3_TX__AUART3_TX 0x30d0 -MX28_PAD_AUART3_CTS__AUART3_CTS 0x30e0 -MX28_PAD_AUART3_RTS__AUART3_RTS 0x30f0 -MX28_PAD_PWM0__PWM_0 0x3100 -MX28_PAD_PWM1__PWM_1 0x3110 -MX28_PAD_PWM2__PWM_2 0x3120 -MX28_PAD_SAIF0_MCLK__SAIF0_MCLK 0x3140 -MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK 0x3150 -MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK 0x3160 -MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 0x3170 -MX28_PAD_I2C0_SCL__I2C0_SCL 0x3180 -MX28_PAD_I2C0_SDA__I2C0_SDA 0x3190 -MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 0x31a0 -MX28_PAD_SPDIF__SPDIF_TX 0x31b0 -MX28_PAD_PWM3__PWM_3 0x31c0 -MX28_PAD_PWM4__PWM_4 0x31d0 -MX28_PAD_LCD_RESET__LCD_RESET 0x31e0 -MX28_PAD_ENET0_MDC__ENET0_MDC 0x4000 -MX28_PAD_ENET0_MDIO__ENET0_MDIO 0x4010 -MX28_PAD_ENET0_RX_EN__ENET0_RX_EN 0x4020 -MX28_PAD_ENET0_RXD0__ENET0_RXD0 0x4030 -MX28_PAD_ENET0_RXD1__ENET0_RXD1 0x4040 -MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK 0x4050 -MX28_PAD_ENET0_TX_EN__ENET0_TX_EN 0x4060 -MX28_PAD_ENET0_TXD0__ENET0_TXD0 0x4070 -MX28_PAD_ENET0_TXD1__ENET0_TXD1 0x4080 -MX28_PAD_ENET0_RXD2__ENET0_RXD2 0x4090 -MX28_PAD_ENET0_RXD3__ENET0_RXD3 0x40a0 -MX28_PAD_ENET0_TXD2__ENET0_TXD2 0x40b0 -MX28_PAD_ENET0_TXD3__ENET0_TXD3 0x40c0 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK 0x40d0 -MX28_PAD_ENET0_COL__ENET0_COL 0x40e0 -MX28_PAD_ENET0_CRS__ENET0_CRS 0x40f0 -MX28_PAD_ENET_CLK__CLKCTRL_ENET 0x4100 -MX28_PAD_JTAG_RTCK__JTAG_RTCK 0x4140 -MX28_PAD_EMI_D00__EMI_DATA0 0x5000 -MX28_PAD_EMI_D01__EMI_DATA1 0x5010 -MX28_PAD_EMI_D02__EMI_DATA2 0x5020 -MX28_PAD_EMI_D03__EMI_DATA3 0x5030 -MX28_PAD_EMI_D04__EMI_DATA4 0x5040 -MX28_PAD_EMI_D05__EMI_DATA5 0x5050 -MX28_PAD_EMI_D06__EMI_DATA6 0x5060 -MX28_PAD_EMI_D07__EMI_DATA7 0x5070 -MX28_PAD_EMI_D08__EMI_DATA8 0x5080 -MX28_PAD_EMI_D09__EMI_DATA9 0x5090 -MX28_PAD_EMI_D10__EMI_DATA10 0x50a0 -MX28_PAD_EMI_D11__EMI_DATA11 0x50b0 -MX28_PAD_EMI_D12__EMI_DATA12 0x50c0 -MX28_PAD_EMI_D13__EMI_DATA13 0x50d0 -MX28_PAD_EMI_D14__EMI_DATA14 0x50e0 -MX28_PAD_EMI_D15__EMI_DATA15 0x50f0 -MX28_PAD_EMI_ODT0__EMI_ODT0 0x5100 -MX28_PAD_EMI_DQM0__EMI_DQM0 0x5110 -MX28_PAD_EMI_ODT1__EMI_ODT1 0x5120 -MX28_PAD_EMI_DQM1__EMI_DQM1 0x5130 -MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK 0x5140 -MX28_PAD_EMI_CLK__EMI_CLK 0x5150 -MX28_PAD_EMI_DQS0__EMI_DQS0 0x5160 -MX28_PAD_EMI_DQS1__EMI_DQS1 0x5170 -MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN 0x51a0 -MX28_PAD_EMI_A00__EMI_ADDR0 0x6000 -MX28_PAD_EMI_A01__EMI_ADDR1 0x6010 -MX28_PAD_EMI_A02__EMI_ADDR2 0x6020 -MX28_PAD_EMI_A03__EMI_ADDR3 0x6030 -MX28_PAD_EMI_A04__EMI_ADDR4 0x6040 -MX28_PAD_EMI_A05__EMI_ADDR5 0x6050 -MX28_PAD_EMI_A06__EMI_ADDR6 0x6060 -MX28_PAD_EMI_A07__EMI_ADDR7 0x6070 -MX28_PAD_EMI_A08__EMI_ADDR8 0x6080 -MX28_PAD_EMI_A09__EMI_ADDR9 0x6090 -MX28_PAD_EMI_A10__EMI_ADDR10 0x60a0 -MX28_PAD_EMI_A11__EMI_ADDR11 0x60b0 -MX28_PAD_EMI_A12__EMI_ADDR12 0x60c0 -MX28_PAD_EMI_A13__EMI_ADDR13 0x60d0 -MX28_PAD_EMI_A14__EMI_ADDR14 0x60e0 -MX28_PAD_EMI_BA0__EMI_BA0 0x6100 -MX28_PAD_EMI_BA1__EMI_BA1 0x6110 -MX28_PAD_EMI_BA2__EMI_BA2 0x6120 -MX28_PAD_EMI_CASN__EMI_CASN 0x6130 -MX28_PAD_EMI_RASN__EMI_RASN 0x6140 -MX28_PAD_EMI_WEN__EMI_WEN 0x6150 -MX28_PAD_EMI_CE0N__EMI_CE0N 0x6160 -MX28_PAD_EMI_CE1N__EMI_CE1N 0x6170 -MX28_PAD_EMI_CKE__EMI_CKE 0x6180 -MX28_PAD_GPMI_D00__SSP1_D0 0x0001 -MX28_PAD_GPMI_D01__SSP1_D1 0x0011 -MX28_PAD_GPMI_D02__SSP1_D2 0x0021 -MX28_PAD_GPMI_D03__SSP1_D3 0x0031 -MX28_PAD_GPMI_D04__SSP1_D4 0x0041 -MX28_PAD_GPMI_D05__SSP1_D5 0x0051 -MX28_PAD_GPMI_D06__SSP1_D6 0x0061 -MX28_PAD_GPMI_D07__SSP1_D7 0x0071 -MX28_PAD_GPMI_CE0N__SSP3_D0 0x0101 -MX28_PAD_GPMI_CE1N__SSP3_D3 0x0111 -MX28_PAD_GPMI_CE2N__CAN1_TX 0x0121 -MX28_PAD_GPMI_CE3N__CAN1_RX 0x0131 -MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT 0x0141 -MX28_PAD_GPMI_RDY1__SSP1_CMD 0x0151 -MX28_PAD_GPMI_RDY2__CAN0_TX 0x0161 -MX28_PAD_GPMI_RDY3__CAN0_RX 0x0171 -MX28_PAD_GPMI_RDN__SSP3_SCK 0x0181 -MX28_PAD_GPMI_WRN__SSP1_SCK 0x0191 -MX28_PAD_GPMI_ALE__SSP3_D1 0x01a1 -MX28_PAD_GPMI_CLE__SSP3_D2 0x01b1 -MX28_PAD_GPMI_RESETN__SSP3_CMD 0x01c1 -MX28_PAD_LCD_D03__ETM_DA8 0x1031 -MX28_PAD_LCD_D04__ETM_DA9 0x1041 -MX28_PAD_LCD_D08__ETM_DA3 0x1081 -MX28_PAD_LCD_D09__ETM_DA4 0x1091 -MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT 0x1141 -MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN 0x1151 -MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT 0x1161 -MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN 0x1171 -MX28_PAD_LCD_RD_E__LCD_VSYNC 0x1181 -MX28_PAD_LCD_WR_RWN__LCD_HSYNC 0x1191 -MX28_PAD_LCD_RS__LCD_DOTCLK 0x11a1 -MX28_PAD_LCD_CS__LCD_ENABLE 0x11b1 -MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 0x11c1 -MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 0x11d1 -MX28_PAD_LCD_DOTCLK__SAIF1_MCLK 0x11e1 -MX28_PAD_SSP0_DATA4__SSP2_D0 0x2041 -MX28_PAD_SSP0_DATA5__SSP2_D3 0x2051 -MX28_PAD_SSP0_DATA6__SSP2_CMD 0x2061 -MX28_PAD_SSP0_DATA7__SSP2_SCK 0x2071 -MX28_PAD_SSP1_SCK__SSP2_D1 0x20c1 -MX28_PAD_SSP1_CMD__SSP2_D2 0x20d1 -MX28_PAD_SSP1_DATA0__SSP2_D6 0x20e1 -MX28_PAD_SSP1_DATA3__SSP2_D7 0x20f1 -MX28_PAD_SSP2_SCK__AUART2_RX 0x2101 -MX28_PAD_SSP2_MOSI__AUART2_TX 0x2111 -MX28_PAD_SSP2_MISO__AUART3_RX 0x2121 -MX28_PAD_SSP2_SS0__AUART3_TX 0x2131 -MX28_PAD_SSP2_SS1__SSP2_D1 0x2141 -MX28_PAD_SSP2_SS2__SSP2_D2 0x2151 -MX28_PAD_SSP3_SCK__AUART4_TX 0x2181 -MX28_PAD_SSP3_MOSI__AUART4_RX 0x2191 -MX28_PAD_SSP3_MISO__AUART4_RTS 0x21a1 -MX28_PAD_SSP3_SS0__AUART4_CTS 0x21b1 -MX28_PAD_AUART0_RX__I2C0_SCL 0x3001 -MX28_PAD_AUART0_TX__I2C0_SDA 0x3011 -MX28_PAD_AUART0_CTS__AUART4_RX 0x3021 -MX28_PAD_AUART0_RTS__AUART4_TX 0x3031 -MX28_PAD_AUART1_RX__SSP2_CARD_DETECT 0x3041 -MX28_PAD_AUART1_TX__SSP3_CARD_DETECT 0x3051 -MX28_PAD_AUART1_CTS__USB0_OVERCURRENT 0x3061 -MX28_PAD_AUART1_RTS__USB0_ID 0x3071 -MX28_PAD_AUART2_RX__SSP3_D1 0x3081 -MX28_PAD_AUART2_TX__SSP3_D2 0x3091 -MX28_PAD_AUART2_CTS__I2C1_SCL 0x30a1 -MX28_PAD_AUART2_RTS__I2C1_SDA 0x30b1 -MX28_PAD_AUART3_RX__CAN0_TX 0x30c1 -MX28_PAD_AUART3_TX__CAN0_RX 0x30d1 -MX28_PAD_AUART3_CTS__CAN1_TX 0x30e1 -MX28_PAD_AUART3_RTS__CAN1_RX 0x30f1 -MX28_PAD_PWM0__I2C1_SCL 0x3101 -MX28_PAD_PWM1__I2C1_SDA 0x3111 -MX28_PAD_PWM2__USB0_ID 0x3121 -MX28_PAD_SAIF0_MCLK__PWM_3 0x3141 -MX28_PAD_SAIF0_LRCLK__PWM_4 0x3151 -MX28_PAD_SAIF0_BITCLK__PWM_5 0x3161 -MX28_PAD_SAIF0_SDATA0__PWM_6 0x3171 -MX28_PAD_I2C0_SCL__TIMROT_ROTARYA 0x3181 -MX28_PAD_I2C0_SDA__TIMROT_ROTARYB 0x3191 -MX28_PAD_SAIF1_SDATA0__PWM_7 0x31a1 -MX28_PAD_LCD_RESET__LCD_VSYNC 0x31e1 -MX28_PAD_ENET0_MDC__GPMI_CE4N 0x4001 -MX28_PAD_ENET0_MDIO__GPMI_CE5N 0x4011 -MX28_PAD_ENET0_RX_EN__GPMI_CE6N 0x4021 -MX28_PAD_ENET0_RXD0__GPMI_CE7N 0x4031 -MX28_PAD_ENET0_RXD1__GPMI_READY4 0x4041 -MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER 0x4051 -MX28_PAD_ENET0_TX_EN__GPMI_READY5 0x4061 -MX28_PAD_ENET0_TXD0__GPMI_READY6 0x4071 -MX28_PAD_ENET0_TXD1__GPMI_READY7 0x4081 -MX28_PAD_ENET0_RXD2__ENET1_RXD0 0x4091 -MX28_PAD_ENET0_RXD3__ENET1_RXD1 0x40a1 -MX28_PAD_ENET0_TXD2__ENET1_TXD0 0x40b1 -MX28_PAD_ENET0_TXD3__ENET1_TXD1 0x40c1 -MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER 0x40d1 -MX28_PAD_ENET0_COL__ENET1_TX_EN 0x40e1 -MX28_PAD_ENET0_CRS__ENET1_RX_EN 0x40f1 -MX28_PAD_GPMI_CE2N__ENET0_RX_ER 0x0122 -MX28_PAD_GPMI_CE3N__SAIF1_MCLK 0x0132 -MX28_PAD_GPMI_RDY0__USB0_ID 0x0142 -MX28_PAD_GPMI_RDY2__ENET0_TX_ER 0x0162 -MX28_PAD_GPMI_RDY3__HSADC_TRIGGER 0x0172 -MX28_PAD_GPMI_ALE__SSP3_D4 0x01a2 -MX28_PAD_GPMI_CLE__SSP3_D5 0x01b2 -MX28_PAD_LCD_D00__ETM_DA0 0x1002 -MX28_PAD_LCD_D01__ETM_DA1 0x1012 -MX28_PAD_LCD_D02__ETM_DA2 0x1022 -MX28_PAD_LCD_D03__ETM_DA3 0x1032 -MX28_PAD_LCD_D04__ETM_DA4 0x1042 -MX28_PAD_LCD_D05__ETM_DA5 0x1052 -MX28_PAD_LCD_D06__ETM_DA6 0x1062 -MX28_PAD_LCD_D07__ETM_DA7 0x1072 -MX28_PAD_LCD_D08__ETM_DA8 0x1082 -MX28_PAD_LCD_D09__ETM_DA9 0x1092 -MX28_PAD_LCD_D10__ETM_DA10 0x10a2 -MX28_PAD_LCD_D11__ETM_DA11 0x10b2 -MX28_PAD_LCD_D12__ETM_DA12 0x10c2 -MX28_PAD_LCD_D13__ETM_DA13 0x10d2 -MX28_PAD_LCD_D14__ETM_DA14 0x10e2 -MX28_PAD_LCD_D15__ETM_DA15 0x10f2 -MX28_PAD_LCD_D16__ETM_DA7 0x1102 -MX28_PAD_LCD_D17__ETM_DA6 0x1112 -MX28_PAD_LCD_D18__ETM_DA5 0x1122 -MX28_PAD_LCD_D19__ETM_DA4 0x1132 -MX28_PAD_LCD_D20__ETM_DA3 0x1142 -MX28_PAD_LCD_D21__ETM_DA2 0x1152 -MX28_PAD_LCD_D22__ETM_DA1 0x1162 -MX28_PAD_LCD_D23__ETM_DA0 0x1172 -MX28_PAD_LCD_RD_E__ETM_TCTL 0x1182 -MX28_PAD_LCD_WR_RWN__ETM_TCLK 0x1192 -MX28_PAD_LCD_HSYNC__ETM_TCTL 0x11d2 -MX28_PAD_LCD_DOTCLK__ETM_TCLK 0x11e2 -MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT 0x20c2 -MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN 0x20d2 -MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT 0x20e2 -MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN 0x20f2 -MX28_PAD_SSP2_SCK__SAIF0_SDATA1 0x2102 -MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 0x2112 -MX28_PAD_SSP2_MISO__SAIF1_SDATA1 0x2122 -MX28_PAD_SSP2_SS0__SAIF1_SDATA2 0x2132 -MX28_PAD_SSP2_SS1__USB1_OVERCURRENT 0x2142 -MX28_PAD_SSP2_SS2__USB0_OVERCURRENT 0x2152 -MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT 0x2182 -MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN 0x2192 -MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT 0x21a2 -MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN 0x21b2 -MX28_PAD_AUART0_RX__DUART_CTS 0x3002 -MX28_PAD_AUART0_TX__DUART_RTS 0x3012 -MX28_PAD_AUART0_CTS__DUART_RX 0x3022 -MX28_PAD_AUART0_RTS__DUART_TX 0x3032 -MX28_PAD_AUART1_RX__PWM_0 0x3042 -MX28_PAD_AUART1_TX__PWM_1 0x3052 -MX28_PAD_AUART1_CTS__TIMROT_ROTARYA 0x3062 -MX28_PAD_AUART1_RTS__TIMROT_ROTARYB 0x3072 -MX28_PAD_AUART2_RX__SSP3_D4 0x3082 -MX28_PAD_AUART2_TX__SSP3_D5 0x3092 -MX28_PAD_AUART2_CTS__SAIF1_BITCLK 0x30a2 -MX28_PAD_AUART2_RTS__SAIF1_LRCLK 0x30b2 -MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT 0x30c2 -MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN 0x30d2 -MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT 0x30e2 -MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN 0x30f2 -MX28_PAD_PWM0__DUART_RX 0x3102 -MX28_PAD_PWM1__DUART_TX 0x3112 -MX28_PAD_PWM2__USB1_OVERCURRENT 0x3122 -MX28_PAD_SAIF0_MCLK__AUART4_CTS 0x3142 -MX28_PAD_SAIF0_LRCLK__AUART4_RTS 0x3152 -MX28_PAD_SAIF0_BITCLK__AUART4_RX 0x3162 -MX28_PAD_SAIF0_SDATA0__AUART4_TX 0x3172 -MX28_PAD_I2C0_SCL__DUART_RX 0x3182 -MX28_PAD_I2C0_SDA__DUART_TX 0x3192 -MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 0x31a2 -MX28_PAD_SPDIF__ENET1_RX_ER 0x31b2 -MX28_PAD_ENET0_MDC__SAIF0_SDATA1 0x4002 -MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 0x4012 -MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 0x4022 -MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 0x4032 -MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT 0x4052 -MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT 0x4092 -MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN 0x40a2 -MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT 0x40b2 -MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN 0x40c2 -MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN 0x40d2 -MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT 0x40e2 -MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN 0x40f2 -MX28_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX28_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX28_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX28_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX28_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX28_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX28_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX28_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX28_PAD_GPMI_CE0N__GPIO_0_16 0x0103 -MX28_PAD_GPMI_CE1N__GPIO_0_17 0x0113 -MX28_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX28_PAD_GPMI_CE3N__GPIO_0_19 0x0133 -MX28_PAD_GPMI_RDY0__GPIO_0_20 0x0143 -MX28_PAD_GPMI_RDY1__GPIO_0_21 0x0153 -MX28_PAD_GPMI_RDY2__GPIO_0_22 0x0163 -MX28_PAD_GPMI_RDY3__GPIO_0_23 0x0173 -MX28_PAD_GPMI_RDN__GPIO_0_24 0x0183 -MX28_PAD_GPMI_WRN__GPIO_0_25 0x0193 -MX28_PAD_GPMI_ALE__GPIO_0_26 0x01a3 -MX28_PAD_GPMI_CLE__GPIO_0_27 0x01b3 -MX28_PAD_GPMI_RESETN__GPIO_0_28 0x01c3 -MX28_PAD_LCD_D00__GPIO_1_0 0x1003 -MX28_PAD_LCD_D01__GPIO_1_1 0x1013 -MX28_PAD_LCD_D02__GPIO_1_2 0x1023 -MX28_PAD_LCD_D03__GPIO_1_3 0x1033 -MX28_PAD_LCD_D04__GPIO_1_4 0x1043 -MX28_PAD_LCD_D05__GPIO_1_5 0x1053 -MX28_PAD_LCD_D06__GPIO_1_6 0x1063 -MX28_PAD_LCD_D07__GPIO_1_7 0x1073 -MX28_PAD_LCD_D08__GPIO_1_8 0x1083 -MX28_PAD_LCD_D09__GPIO_1_9 0x1093 -MX28_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX28_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX28_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX28_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX28_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX28_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX28_PAD_LCD_D16__GPIO_1_16 0x1103 -MX28_PAD_LCD_D17__GPIO_1_17 0x1113 -MX28_PAD_LCD_D18__GPIO_1_18 0x1123 -MX28_PAD_LCD_D19__GPIO_1_19 0x1133 -MX28_PAD_LCD_D20__GPIO_1_20 0x1143 -MX28_PAD_LCD_D21__GPIO_1_21 0x1153 -MX28_PAD_LCD_D22__GPIO_1_22 0x1163 -MX28_PAD_LCD_D23__GPIO_1_23 0x1173 -MX28_PAD_LCD_RD_E__GPIO_1_24 0x1183 -MX28_PAD_LCD_WR_RWN__GPIO_1_25 0x1193 -MX28_PAD_LCD_RS__GPIO_1_26 0x11a3 -MX28_PAD_LCD_CS__GPIO_1_27 0x11b3 -MX28_PAD_LCD_VSYNC__GPIO_1_28 0x11c3 -MX28_PAD_LCD_HSYNC__GPIO_1_29 0x11d3 -MX28_PAD_LCD_DOTCLK__GPIO_1_30 0x11e3 -MX28_PAD_LCD_ENABLE__GPIO_1_31 0x11f3 -MX28_PAD_SSP0_DATA0__GPIO_2_0 0x2003 -MX28_PAD_SSP0_DATA1__GPIO_2_1 0x2013 -MX28_PAD_SSP0_DATA2__GPIO_2_2 0x2023 -MX28_PAD_SSP0_DATA3__GPIO_2_3 0x2033 -MX28_PAD_SSP0_DATA4__GPIO_2_4 0x2043 -MX28_PAD_SSP0_DATA5__GPIO_2_5 0x2053 -MX28_PAD_SSP0_DATA6__GPIO_2_6 0x2063 -MX28_PAD_SSP0_DATA7__GPIO_2_7 0x2073 -MX28_PAD_SSP0_CMD__GPIO_2_8 0x2083 -MX28_PAD_SSP0_DETECT__GPIO_2_9 0x2093 -MX28_PAD_SSP0_SCK__GPIO_2_10 0x20a3 -MX28_PAD_SSP1_SCK__GPIO_2_12 0x20c3 -MX28_PAD_SSP1_CMD__GPIO_2_13 0x20d3 -MX28_PAD_SSP1_DATA0__GPIO_2_14 0x20e3 -MX28_PAD_SSP1_DATA3__GPIO_2_15 0x20f3 -MX28_PAD_SSP2_SCK__GPIO_2_16 0x2103 -MX28_PAD_SSP2_MOSI__GPIO_2_17 0x2113 -MX28_PAD_SSP2_MISO__GPIO_2_18 0x2123 -MX28_PAD_SSP2_SS0__GPIO_2_19 0x2133 -MX28_PAD_SSP2_SS1__GPIO_2_20 0x2143 -MX28_PAD_SSP2_SS2__GPIO_2_21 0x2153 -MX28_PAD_SSP3_SCK__GPIO_2_24 0x2183 -MX28_PAD_SSP3_MOSI__GPIO_2_25 0x2193 -MX28_PAD_SSP3_MISO__GPIO_2_26 0x21a3 -MX28_PAD_SSP3_SS0__GPIO_2_27 0x21b3 -MX28_PAD_AUART0_RX__GPIO_3_0 0x3003 -MX28_PAD_AUART0_TX__GPIO_3_1 0x3013 -MX28_PAD_AUART0_CTS__GPIO_3_2 0x3023 -MX28_PAD_AUART0_RTS__GPIO_3_3 0x3033 -MX28_PAD_AUART1_RX__GPIO_3_4 0x3043 -MX28_PAD_AUART1_TX__GPIO_3_5 0x3053 -MX28_PAD_AUART1_CTS__GPIO_3_6 0x3063 -MX28_PAD_AUART1_RTS__GPIO_3_7 0x3073 -MX28_PAD_AUART2_RX__GPIO_3_8 0x3083 -MX28_PAD_AUART2_TX__GPIO_3_9 0x3093 -MX28_PAD_AUART2_CTS__GPIO_3_10 0x30a3 -MX28_PAD_AUART2_RTS__GPIO_3_11 0x30b3 -MX28_PAD_AUART3_RX__GPIO_3_12 0x30c3 -MX28_PAD_AUART3_TX__GPIO_3_13 0x30d3 -MX28_PAD_AUART3_CTS__GPIO_3_14 0x30e3 -MX28_PAD_AUART3_RTS__GPIO_3_15 0x30f3 -MX28_PAD_PWM0__GPIO_3_16 0x3103 -MX28_PAD_PWM1__GPIO_3_17 0x3113 -MX28_PAD_PWM2__GPIO_3_18 0x3123 -MX28_PAD_SAIF0_MCLK__GPIO_3_20 0x3143 -MX28_PAD_SAIF0_LRCLK__GPIO_3_21 0x3153 -MX28_PAD_SAIF0_BITCLK__GPIO_3_22 0x3163 -MX28_PAD_SAIF0_SDATA0__GPIO_3_23 0x3173 -MX28_PAD_I2C0_SCL__GPIO_3_24 0x3183 -MX28_PAD_I2C0_SDA__GPIO_3_25 0x3193 -MX28_PAD_SAIF1_SDATA0__GPIO_3_26 0x31a3 -MX28_PAD_SPDIF__GPIO_3_27 0x31b3 -MX28_PAD_PWM3__GPIO_3_28 0x31c3 -MX28_PAD_PWM4__GPIO_3_29 0x31d3 -MX28_PAD_LCD_RESET__GPIO_3_30 0x31e3 -MX28_PAD_ENET0_MDC__GPIO_4_0 0x4003 -MX28_PAD_ENET0_MDIO__GPIO_4_1 0x4013 -MX28_PAD_ENET0_RX_EN__GPIO_4_2 0x4023 -MX28_PAD_ENET0_RXD0__GPIO_4_3 0x4033 -MX28_PAD_ENET0_RXD1__GPIO_4_4 0x4043 -MX28_PAD_ENET0_TX_CLK__GPIO_4_5 0x4053 -MX28_PAD_ENET0_TX_EN__GPIO_4_6 0x4063 -MX28_PAD_ENET0_TXD0__GPIO_4_7 0x4073 -MX28_PAD_ENET0_TXD1__GPIO_4_8 0x4083 -MX28_PAD_ENET0_RXD2__GPIO_4_9 0x4093 -MX28_PAD_ENET0_RXD3__GPIO_4_10 0x40a3 -MX28_PAD_ENET0_TXD2__GPIO_4_11 0x40b3 -MX28_PAD_ENET0_TXD3__GPIO_4_12 0x40c3 -MX28_PAD_ENET0_RX_CLK__GPIO_4_13 0x40d3 -MX28_PAD_ENET0_COL__GPIO_4_14 0x40e3 -MX28_PAD_ENET0_CRS__GPIO_4_15 0x40f3 -MX28_PAD_ENET_CLK__GPIO_4_16 0x4103 -MX28_PAD_JTAG_RTCK__GPIO_4_20 0x4143 - -Valid values for i.MX23 pinmux-id: - -pinmux id ------- -- -MX23_PAD_GPMI_D00__GPMI_D00 0x0000 -MX23_PAD_GPMI_D01__GPMI_D01 0x0010 -MX23_PAD_GPMI_D02__GPMI_D02 0x0020 -MX23_PAD_GPMI_D03__GPMI_D03 0x0030 -MX23_PAD_GPMI_D04__GPMI_D04 0x0040 -MX23_PAD_GPMI_D05__GPMI_D05 0x0050 -MX23_PAD_GPMI_D06__GPMI_D06 0x0060 -MX23_PAD_GPMI_D07__GPMI_D07 0x0070 -MX23_PAD_GPMI_D08__GPMI_D08 0x0080 -MX23_PAD_GPMI_D09__GPMI_D09 0x0090 -MX23_PAD_GPMI_D10__GPMI_D10 0x00a0 -MX23_PAD_GPMI_D11__GPMI_D11 0x00b0 -MX23_PAD_GPMI_D12__GPMI_D12 0x00c0 -MX23_PAD_GPMI_D13__GPMI_D13 0x00d0 -MX23_PAD_GPMI_D14__GPMI_D14 0x00e0 -MX23_PAD_GPMI_D15__GPMI_D15 0x00f0 -MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100 -MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110 -MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120 -MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130 -MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140 -MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150 -MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160 -MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170 -MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180 -MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190 -MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0 -MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0 -MX23_PAD_AUART1_RX__AUART1_RX 0x01c0 -MX23_PAD_AUART1_TX__AUART1_TX 0x01d0 -MX23_PAD_I2C_SCL__I2C_SCL 0x01e0 -MX23_PAD_I2C_SDA__I2C_SDA 0x01f0 -MX23_PAD_LCD_D00__LCD_D00 0x1000 -MX23_PAD_LCD_D01__LCD_D01 0x1010 -MX23_PAD_LCD_D02__LCD_D02 0x1020 -MX23_PAD_LCD_D03__LCD_D03 0x1030 -MX23_PAD_LCD_D04__LCD_D04 0x1040 -MX23_PAD_LCD_D05__LCD_D05 0x1050 -MX23_PAD_LCD_D06__LCD_D06 0x1060 -MX23_PAD_LCD_D07__LCD_D07 0x1070 -MX23_PAD_LCD_D08__LCD_D08 0x1080 -MX23_PAD_LCD_D09__LCD_D09 0x1090 -MX23_PAD_LCD_D10__LCD_D10 0x10a0 -MX23_PAD_LCD_D11__LCD_D11 0x10b0 -MX23_PAD_LCD_D12__LCD_D12 0x10c0 -MX23_PAD_LCD_D13__LCD_D13 0x10d0 -MX23_PAD_LCD_D14__LCD_D14 0x10e0 -MX23_PAD_LCD_D15__LCD_D15 0x10f0 -MX23_PAD_LCD_D16__LCD_D16 0x1100 -MX23_PAD_LCD_D17__LCD_D17 0x1110 -MX23_PAD_LCD_RESET__LCD_RESET 0x1120 -MX23_PAD_LCD_RS__LCD_RS 0x1130 -MX23_PAD_LCD_WR__LCD_WR 0x1140 -MX23_PAD_LCD_CS__LCD_CS 0x1150 -MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160 -MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170 -MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180 -MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190 -MX23_PAD_PWM0__PWM0 0x11a0 -MX23_PAD_PWM1__PWM1 0x11b0 -MX23_PAD_PWM2__PWM2 0x11c0 -MX23_PAD_PWM3__PWM3 0x11d0 -MX23_PAD_PWM4__PWM4 0x11e0 -MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000 -MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010 -MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020 -MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030 -MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040 -MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050 -MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060 -MX23_PAD_ROTARYA__ROTARYA 0x2070 -MX23_PAD_ROTARYB__ROTARYB 0x2080 -MX23_PAD_EMI_A00__EMI_A00 0x2090 -MX23_PAD_EMI_A01__EMI_A01 0x20a0 -MX23_PAD_EMI_A02__EMI_A02 0x20b0 -MX23_PAD_EMI_A03__EMI_A03 0x20c0 -MX23_PAD_EMI_A04__EMI_A04 0x20d0 -MX23_PAD_EMI_A05__EMI_A05 0x20e0 -MX23_PAD_EMI_A06__EMI_A06 0x20f0 -MX23_PAD_EMI_A07__EMI_A07 0x2100 -MX23_PAD_EMI_A08__EMI_A08 0x2110 -MX23_PAD_EMI_A09__EMI_A09 0x2120 -MX23_PAD_EMI_A10__EMI_A10 0x2130 -MX23_PAD_EMI_A11__EMI_A11 0x2140 -MX23_PAD_EMI_A12__EMI_A12 0x2150 -MX23_PAD_EMI_BA0__EMI_BA0 0x2160 -MX23_PAD_EMI_BA1__EMI_BA1 0x2170 -MX23_PAD_EMI_CASN__EMI_CASN 0x2180 -MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190 -MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0 -MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0 -MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0 -MX23_PAD_EMI_CKE__EMI_CKE 0x21d0 -MX23_PAD_EMI_RASN__EMI_RASN 0x21e0 -MX23_PAD_EMI_WEN__EMI_WEN 0x21f0 -MX23_PAD_EMI_D00__EMI_D00 0x3000 -MX23_PAD_EMI_D01__EMI_D01 0x3010 -MX23_PAD_EMI_D02__EMI_D02 0x3020 -MX23_PAD_EMI_D03__EMI_D03 0x3030 -MX23_PAD_EMI_D04__EMI_D04 0x3040 -MX23_PAD_EMI_D05__EMI_D05 0x3050 -MX23_PAD_EMI_D06__EMI_D06 0x3060 -MX23_PAD_EMI_D07__EMI_D07 0x3070 -MX23_PAD_EMI_D08__EMI_D08 0x3080 -MX23_PAD_EMI_D09__EMI_D09 0x3090 -MX23_PAD_EMI_D10__EMI_D10 0x30a0 -MX23_PAD_EMI_D11__EMI_D11 0x30b0 -MX23_PAD_EMI_D12__EMI_D12 0x30c0 -MX23_PAD_EMI_D13__EMI_D13 0x30d0 -MX23_PAD_EMI_D14__EMI_D14 0x30e0 -MX23_PAD_EMI_D15__EMI_D15 0x30f0 -MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100 -MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110 -MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120 -MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130 -MX23_PAD_EMI_CLK__EMI_CLK 0x3140 -MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150 -MX23_PAD_GPMI_D00__LCD_D8 0x0001 -MX23_PAD_GPMI_D01__LCD_D9 0x0011 -MX23_PAD_GPMI_D02__LCD_D10 0x0021 -MX23_PAD_GPMI_D03__LCD_D11 0x0031 -MX23_PAD_GPMI_D04__LCD_D12 0x0041 -MX23_PAD_GPMI_D05__LCD_D13 0x0051 -MX23_PAD_GPMI_D06__LCD_D14 0x0061 -MX23_PAD_GPMI_D07__LCD_D15 0x0071 -MX23_PAD_GPMI_D08__LCD_D18 0x0081 -MX23_PAD_GPMI_D09__LCD_D19 0x0091 -MX23_PAD_GPMI_D10__LCD_D20 0x00a1 -MX23_PAD_GPMI_D11__LCD_D21 0x00b1 -MX23_PAD_GPMI_D12__LCD_D22 0x00c1 -MX23_PAD_GPMI_D13__LCD_D23 0x00d1 -MX23_PAD_GPMI_D14__AUART2_RX 0x00e1 -MX23_PAD_GPMI_D15__AUART2_TX 0x00f1 -MX23_PAD_GPMI_CLE__LCD_D16 0x0101 -MX23_PAD_GPMI_ALE__LCD_D17 0x0111 -MX23_PAD_GPMI_CE2N__ATA_A2 0x0121 -MX23_PAD_AUART1_RTS__IR_CLK 0x01b1 -MX23_PAD_AUART1_RX__IR_RX 0x01c1 -MX23_PAD_AUART1_TX__IR_TX 0x01d1 -MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1 -MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1 -MX23_PAD_LCD_D00__ETM_DA8 0x1001 -MX23_PAD_LCD_D01__ETM_DA9 0x1011 -MX23_PAD_LCD_D02__ETM_DA10 0x1021 -MX23_PAD_LCD_D03__ETM_DA11 0x1031 -MX23_PAD_LCD_D04__ETM_DA12 0x1041 -MX23_PAD_LCD_D05__ETM_DA13 0x1051 -MX23_PAD_LCD_D06__ETM_DA14 0x1061 -MX23_PAD_LCD_D07__ETM_DA15 0x1071 -MX23_PAD_LCD_D08__ETM_DA0 0x1081 -MX23_PAD_LCD_D09__ETM_DA1 0x1091 -MX23_PAD_LCD_D10__ETM_DA2 0x10a1 -MX23_PAD_LCD_D11__ETM_DA3 0x10b1 -MX23_PAD_LCD_D12__ETM_DA4 0x10c1 -MX23_PAD_LCD_D13__ETM_DA5 0x10d1 -MX23_PAD_LCD_D14__ETM_DA6 0x10e1 -MX23_PAD_LCD_D15__ETM_DA7 0x10f1 -MX23_PAD_LCD_RESET__ETM_TCTL 0x1121 -MX23_PAD_LCD_RS__ETM_TCLK 0x1131 -MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161 -MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171 -MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181 -MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191 -MX23_PAD_PWM0__ROTARYA 0x11a1 -MX23_PAD_PWM1__ROTARYB 0x11b1 -MX23_PAD_PWM2__GPMI_RDY3 0x11c1 -MX23_PAD_PWM3__ETM_TCTL 0x11d1 -MX23_PAD_PWM4__ETM_TCLK 0x11e1 -MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011 -MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031 -MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041 -MX23_PAD_ROTARYA__AUART2_RTS 0x2071 -MX23_PAD_ROTARYB__AUART2_CTS 0x2081 -MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002 -MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012 -MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022 -MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032 -MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042 -MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052 -MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062 -MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072 -MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082 -MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092 -MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2 -MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2 -MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2 -MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132 -MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142 -MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182 -MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2 -MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2 -MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2 -MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2 -MX23_PAD_I2C_SCL__AUART1_TX 0x01e2 -MX23_PAD_I2C_SDA__AUART1_RX 0x01f2 -MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082 -MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092 -MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2 -MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2 -MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2 -MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2 -MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2 -MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2 -MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102 -MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122 -MX23_PAD_PWM0__DUART_RX 0x11a2 -MX23_PAD_PWM1__DUART_TX 0x11b2 -MX23_PAD_PWM3__AUART1_CTS 0x11d2 -MX23_PAD_PWM4__AUART1_RTS 0x11e2 -MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002 -MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012 -MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022 -MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032 -MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042 -MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052 -MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062 -MX23_PAD_ROTARYA__SPDIF 0x2072 -MX23_PAD_ROTARYB__GPMI_CE3N 0x2082 -MX23_PAD_GPMI_D00__GPIO_0_0 0x0003 -MX23_PAD_GPMI_D01__GPIO_0_1 0x0013 -MX23_PAD_GPMI_D02__GPIO_0_2 0x0023 -MX23_PAD_GPMI_D03__GPIO_0_3 0x0033 -MX23_PAD_GPMI_D04__GPIO_0_4 0x0043 -MX23_PAD_GPMI_D05__GPIO_0_5 0x0053 -MX23_PAD_GPMI_D06__GPIO_0_6 0x0063 -MX23_PAD_GPMI_D07__GPIO_0_7 0x0073 -MX23_PAD_GPMI_D08__GPIO_0_8 0x0083 -MX23_PAD_GPMI_D09__GPIO_0_9 0x0093 -MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3 -MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3 -MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3 -MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3 -MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3 -MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3 -MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103 -MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113 -MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123 -MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133 -MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143 -MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153 -MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163 -MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173 -MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183 -MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193 -MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3 -MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3 -MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3 -MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3 -MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3 -MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3 -MX23_PAD_LCD_D00__GPIO_1_0 0x1003 -MX23_PAD_LCD_D01__GPIO_1_1 0x1013 -MX23_PAD_LCD_D02__GPIO_1_2 0x1023 -MX23_PAD_LCD_D03__GPIO_1_3 0x1033 -MX23_PAD_LCD_D04__GPIO_1_4 0x1043 -MX23_PAD_LCD_D05__GPIO_1_5 0x1053 -MX23_PAD_LCD_D06__GPIO_1_6 0x1063 -MX23_PAD_LCD_D07__GPIO_1_7 0x1073 -MX23_PAD_LCD_D08__GPIO_1_8 0x1083 -MX23_PAD_LCD_D09__GPIO_1_9 0x1093 -MX23_PAD_LCD_D10__GPIO_1_10 0x10a3 -MX23_PAD_LCD_D11__GPIO_1_11 0x10b3 -MX23_PAD_LCD_D12__GPIO_1_12 0x10c3 -MX23_PAD_LCD_D13__GPIO_1_13 0x10d3 -MX23_PAD_LCD_D14__GPIO_1_14 0x10e3 -MX23_PAD_LCD_D15__GPIO_1_15 0x10f3 -MX23_PAD_LCD_D16__GPIO_1_16 0x1103 -MX23_PAD_LCD_D17__GPIO_1_17 0x1113 -MX23_PAD_LCD_RESET__GPIO_1_18 0x1123 -MX23_PAD_LCD_RS__GPIO_1_19 0x1133 -MX23_PAD_LCD_WR__GPIO_1_20 0x1143 -MX23_PAD_LCD_CS__GPIO_1_21 0x1153 -MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163 -MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173 -MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183 -MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193 -MX23_PAD_PWM0__GPIO_1_26 0x11a3 -MX23_PAD_PWM1__GPIO_1_27 0x11b3 -MX23_PAD_PWM2__GPIO_1_28 0x11c3 -MX23_PAD_PWM3__GPIO_1_29 0x11d3 -MX23_PAD_PWM4__GPIO_1_30 0x11e3 -MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003 -MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013 -MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023 -MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033 -MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043 -MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053 -MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063 -MX23_PAD_ROTARYA__GPIO_2_7 0x2073 -MX23_PAD_ROTARYB__GPIO_2_8 0x2083 -MX23_PAD_EMI_A00__GPIO_2_9 0x2093 -MX23_PAD_EMI_A01__GPIO_2_10 0x20a3 -MX23_PAD_EMI_A02__GPIO_2_11 0x20b3 -MX23_PAD_EMI_A03__GPIO_2_12 0x20c3 -MX23_PAD_EMI_A04__GPIO_2_13 0x20d3 -MX23_PAD_EMI_A05__GPIO_2_14 0x20e3 -MX23_PAD_EMI_A06__GPIO_2_15 0x20f3 -MX23_PAD_EMI_A07__GPIO_2_16 0x2103 -MX23_PAD_EMI_A08__GPIO_2_17 0x2113 -MX23_PAD_EMI_A09__GPIO_2_18 0x2123 -MX23_PAD_EMI_A10__GPIO_2_19 0x2133 -MX23_PAD_EMI_A11__GPIO_2_20 0x2143 -MX23_PAD_EMI_A12__GPIO_2_21 0x2153 -MX23_PAD_EMI_BA0__GPIO_2_22 0x2163 -MX23_PAD_EMI_BA1__GPIO_2_23 0x2173 -MX23_PAD_EMI_CASN__GPIO_2_24 0x2183 -MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193 -MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3 -MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3 -MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3 -MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3 -MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3 -MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3 diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt deleted file mode 100644 index c8e578263ce2..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt +++ /dev/null @@ -1,132 +0,0 @@ -NVIDIA Tegra20 pinmux controller - -Required properties: -- compatible: "nvidia,tegra20-pinmux" -- reg: Should contain the register physical address and length for each of - the tri-state, mux, pull-up/down, and pad control register sets. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Tegra's pin configuration nodes act as a container for an abitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, tristate, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function or tristate parameter. For this -reason, even seemingly boolean values are actually tristates in this binding: -unspecified, off, or on. Unspecified is represented as an absent property, -and off/on are represented as integer values 0 and 1. - -Required subnode-properties: -- nvidia,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- nvidia,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below. See the Tegra - TRM to determine which are valid for each pin or group. -- nvidia,pull: Integer, representing the pull-down/up to apply to the pin. - 0: none, 1: down, 2: up. -- nvidia,tristate: Integer. - 0: drive, 1: tristate. -- nvidia,high-speed-mode: Integer. Enable high speed mode the pins. - 0: no, 1: yes. -- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input. - 0: no, 1: yes. -- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is - most power. Controls the drive power or current. See "Low Power Mode" - or "LPMD1" and "LPMD0" in the Tegra TRM. -- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVDN" in the - Tegra TRM. -- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest. - The range of valid values depends on the pingroup. See "CAL_DRVUP" in the - Tegra TRM. -- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVDN_SLWR" in the Tegra TRM. -- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is - fastest. The range of valid values depends on the pingroup. See - "DRVUP_SLWF" in the Tegra TRM. - -Note that many of these properties are only valid for certain specific pins -or groups. See the Tegra TRM and various pinmux spreadsheets for complete -details regarding which groups support which functionality. The Linux pinctrl -driver may also be a useful reference, since it consolidates, disambiguates, -and corrects data from all those sources. - -Valid values for pin and group names are: - - mux groups: - - These all support nvidia,function, nvidia,tristate, and many support - nvidia,pull. - - ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4, - ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7, - gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, - ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13, - ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp, - lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs, - owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, - spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad, - uca, ucb, uda. - - tristate groups: - - These only support nvidia,pull. - - ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0, - ld19_18, ld21_20, ld23_22. - - drive groups: - - With some exceptions, these support nvidia,high-speed-mode, - nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength, - nvidia,pull-up-strength, nvidia,slew_rate-rising, nvidia,slew_rate-falling. - - drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2, - drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg, - drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, - drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a, - drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc, - drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr, - drive_uda. - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra20-pinmux"; - reg = < 0x70000014 0x10 /* Tri-state registers */ - 0x70000080 0x20 /* Mux registers */ - 0x700000a0 0x14 /* Pull-up/down registers */ - 0x70000868 0xa8 >; /* Pad control registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdio4_default: sdio4_default { - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@c8000600 { - pinctrl-names = "default"; - pinctrl-0 = <&sdio4_default>; - }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt deleted file mode 100644 index c275b70349c1..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt +++ /dev/null @@ -1,132 +0,0 @@ -NVIDIA Tegra30 pinmux controller - -The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding, -as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes -that binding as a baseline, and only documents the differences between the -two bindings. - -Required properties: -- compatible: "nvidia,tegra30-pinmux" -- reg: Should contain the register physical address and length for each of - the pad control and mux registers. - -Tegra30 adds the following optional properties for pin configuration subnodes: -- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes. -- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes. -- nvidia,lock: Integer. Lock the pin configuration against further changes - until reset. 0: no, 1: yes. -- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes. - -As with Tegra20, see the Tegra TRM for complete details regarding which groups -support which functionality. - -Valid values for pin and group names are: - - per-pin mux groups: - - These all support nvidia,function, nvidia,tristate, nvidia,pull, - nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain, - nvidia,io-reset. - - clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3, - dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0, - gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5, - sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1, - uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, - lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2, - sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7, - lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, - lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3, - lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0, - gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, - gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, - gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7, - gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4, - gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, - gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5, - uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2, - gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7, - vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, - vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3, - lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0, - dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5, - lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2, - ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, - ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, - dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, - kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, - kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, - kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, - kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, - kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1, - vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, - sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0, - pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, - lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4, - clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1, - spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6, - spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, - sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7, - sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4, - sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, - sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, - sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0, - cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, - cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4, - clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7, - pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, - pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5, - pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1, - clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr, - pwr_int_n. - - drive groups: - - These all support nvidia,pull-down-strength, nvidia,pull-up-strength, - nvidia,slew_rate-rising, nvidia,slew_rate-falling. Most but not all - support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode. - - ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1, - dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg, - gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2, - uart3, uda, vi1. - -Example: - - pinctrl@70000000 { - compatible = "nvidia,tegra30-pinmux"; - reg = < 0x70000868 0xd0 /* Pad control registers */ - 0x70003000 0x3e0 >; /* Mux registers */ - }; - -Example board file extract: - - pinctrl@70000000 { - sdmmc4_default: pinmux { - sdmmc4_clk_pcc4 { - nvidia,pins = "sdmmc4_clk_pcc4", - "sdmmc4_rst_n_pcc3"; - nvidia,function = "sdmmc4"; - nvidia,pull = <0>; - nvidia,tristate = <0>; - }; - sdmmc4_dat0_paa0 { - nvidia,pins = "sdmmc4_dat0_paa0", - "sdmmc4_dat1_paa1", - "sdmmc4_dat2_paa2", - "sdmmc4_dat3_paa3", - "sdmmc4_dat4_paa4", - "sdmmc4_dat5_paa5", - "sdmmc4_dat6_paa6", - "sdmmc4_dat7_paa7"; - nvidia,function = "sdmmc4"; - nvidia,pull = <2>; - nvidia,tristate = <0>; - }; - }; - }; - - sdhci@78000400 { - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc4_default>; - }; diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt deleted file mode 100644 index c95ea8278f87..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ /dev/null @@ -1,128 +0,0 @@ -== Introduction == - -Hardware modules that control pin multiplexing or configuration parameters -such as pull-up/down, tri-state, drive-strength etc are designated as pin -controllers. Each pin controller must be represented as a node in device tree, -just like any other hardware module. - -Hardware modules whose signals are affected by pin configuration are -designated client devices. Again, each client device must be represented as a -node in device tree, just like any other hardware module. - -For a client device to operate correctly, certain pin controllers must -set up certain specific pin configurations. Some client devices need a -single static pin configuration, e.g. set up during initialization. Others -need to reconfigure pins at run-time, for example to tri-state pins when the -device is inactive. Hence, each client device can define a set of named -states. The number and names of those states is defined by the client device's -own binding. - -The common pinctrl bindings defined in this file provide an infrastructure -for client device device tree nodes to map those state names to the pin -configuration used by those states. - -Note that pin controllers themselves may also be client devices of themselves. -For example, a pin controller may set up its own "active" state when the -driver loads. This would allow representing a board's static pin configuration -in a single place, rather than splitting it across multiple client device -nodes. The decision to do this or not somewhat rests with the author of -individual board device tree files, and any requirements imposed by the -bindings for the individual client devices in use by that board, i.e. whether -they require certain specific named states for dynamic pin configuration. - -== Pinctrl client devices == - -For each client device individually, every pin state is assigned an integer -ID. These numbers start at 0, and are contiguous. For each state ID, a unique -property exists to define the pin configuration. Each state may also be -assigned a name. When names are used, another property exists to map from -those names to the integer IDs. - -Each client device's own binding determines the set of states the must be -defined in its device tree node, and whether to define the set of state -IDs that must be provided, or whether to define the set of state names that -must be provided. - -Required properties: -pinctrl-0: List of phandles, each pointing at a pin configuration - node. These referenced pin configuration nodes must be child - nodes of the pin controller that they configure. Multiple - entries may exist in this list so that multiple pin - controllers may be configured, or so that a state may be built - from multiple nodes for a single pin controller, each - contributing part of the overall configuration. See the next - section of this document for details of the format of these - pin configuration nodes. - - In some cases, it may be useful to define a state, but for it - to be empty. This may be required when a common IP block is - used in an SoC either without a pin controller, or where the - pin controller does not affect the HW module in question. If - the binding for that IP block requires certain pin states to - exist, they must still be defined, but may be left empty. - -Optional properties: -pinctrl-1: List of phandles, each pointing at a pin configuration - node within a pin controller. -... -pinctrl-n: List of phandles, each pointing at a pin configuration - node within a pin controller. -pinctrl-names: The list of names to assign states. List entry 0 defines the - name for integer state ID 0, list entry 1 for state ID 1, and - so on. - -For example: - - /* For a client device requiring named states */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* For the same device if using state IDs */ - device { - pinctrl-0 = <&state_0_node_a>; - pinctrl-1 = <&state_1_node_a &state_1_node_b>; - }; - - /* - * For an IP block whose binding supports pin configuration, - * but in use on an SoC that doesn't have any pin control hardware - */ - device { - pinctrl-names = "active", "idle"; - pinctrl-0 = <>; - pinctrl-1 = <>; - }; - -== Pin controller devices == - -Pin controller devices should contain the pin configuration nodes that client -devices reference. - -For example: - - pincontroller { - ... /* Standard DT properties for the device itself elided */ - - state_0_node_a { - ... - }; - state_1_node_a { - ... - }; - state_1_node_b { - ... - }; - } - -The contents of each of those pin configuration child nodes is defined -entirely by the binding for the individual pin controller device. There -exists no common standard for this content. - -The pin configuration nodes need not be direct children of the pin controller -device; they may be grandchildren, for example. Whether this is legal, and -whether there is any interaction between the child and intermediate parent -nodes, is again defined entirely by the binding for the individual pin -controller device. diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt deleted file mode 100644 index 3664d37e6799..000000000000 --- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ /dev/null @@ -1,108 +0,0 @@ -ST Microelectronics, SPEAr pinmux controller - -Required properties: -- compatible : "st,spear300-pinmux" - : "st,spear310-pinmux" - : "st,spear320-pinmux" -- reg : Address range of the pinctrl registers -- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. - - Its values for SPEAr300: - - NAND_MODE : <0> - - NOR_MODE : <1> - - PHOTO_FRAME_MODE : <2> - - LEND_IP_PHONE_MODE : <3> - - HEND_IP_PHONE_MODE : <4> - - LEND_WIFI_PHONE_MODE : <5> - - HEND_WIFI_PHONE_MODE : <6> - - ATA_PABX_WI2S_MODE : <7> - - ATA_PABX_I2S_MODE : <8> - - CAML_LCDW_MODE : <9> - - CAMU_LCD_MODE : <10> - - CAMU_WLCD_MODE : <11> - - CAML_LCD_MODE : <12> - - Its values for SPEAr320: - - AUTO_NET_SMII_MODE : <0> - - AUTO_NET_MII_MODE : <1> - - AUTO_EXP_MODE : <2> - - SMALL_PRINTERS_MODE : <3> - - EXTENDED_MODE : <4> - -Please refer to pinctrl-bindings.txt in this directory for details of the common -pinctrl bindings used by client devices. - -SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each -of these subnodes represents muxing for a pin, a group, or a list of pins or -groups. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Required subnode-properties: -- st,pins : An array of strings. Each string contains the name of a pin or - group. -- st,function: A string containing the name of the function to mux to the pin or - group. See the SPEAr's TRM to determine which are valid for each pin or group. - - Valid values for group and function names can be found from looking at the - group and function arrays in driver files: - drivers/pinctrl/spear/pinctrl-spear3*0.c - -Valid values for group names are: -For All SPEAr3xx machines: - "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp", - "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp", - "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp", - "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp" - -For SPEAr300 machines: - "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp", - "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp", - "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp", - "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" - -For SPEAr310 machines: - "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp", - "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp" - -For SPEAr320 machines: - "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp", - "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp", - "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp", - "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp", - "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp", - "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp", - "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp", - "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", - "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp", - "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp", - "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp", - "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp", - "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp", - "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp", - "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp", - "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp", - "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp", - "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp", - "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp", - "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp", - "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp", - "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", - "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" - -Valid values for function names are: -For All SPEAr3xx machines: - "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", - "uart0", "timer_0_1", "timer_2_3" - -For SPEAr300 machines: - "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1" - -For SPEAr310 machines: - "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0", - "rs485_1", "tdm" - -For SPEAr320 machines: - "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem", - "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", - "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", - "mii0_1", "i2c1", "i2c2" diff --git a/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt new file mode 100644 index 000000000000..36f82dbdd14d --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt @@ -0,0 +1,5 @@ +NVIDIA Tegra 2 pinmux controller + +Required properties: +- compatible : "nvidia,tegra20-pinmux" + diff --git a/trunk/Documentation/driver-model/devres.txt b/trunk/Documentation/driver-model/devres.txt index 950856bd2e39..2a596a4fc23e 100644 --- a/trunk/Documentation/driver-model/devres.txt +++ b/trunk/Documentation/driver-model/devres.txt @@ -276,11 +276,3 @@ REGULATOR devm_regulator_get() devm_regulator_put() devm_regulator_bulk_get() - -CLOCK - devm_clk_get() - devm_clk_put() - -PINCTRL - devm_pinctrl_get() - devm_pinctrl_put() diff --git a/trunk/Documentation/pinctrl.txt b/trunk/Documentation/pinctrl.txt index e40f4b4e1977..d97bccf46147 100644 --- a/trunk/Documentation/pinctrl.txt +++ b/trunk/Documentation/pinctrl.txt @@ -152,9 +152,11 @@ static const struct foo_group foo_groups[] = { }; -static int foo_get_groups_count(struct pinctrl_dev *pctldev) +static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_groups); + if (selector >= ARRAY_SIZE(foo_groups)) + return -EINVAL; + return 0; } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, @@ -173,7 +175,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, + .list_groups = foo_list_groups, .get_group_name = foo_get_group_name, .get_group_pins = foo_get_group_pins, }; @@ -184,12 +186,13 @@ static struct pinctrl_desc foo_desc = { .pctlops = &foo_pctrl_ops, }; -The pin control subsystem will call the .get_groups_count() function to -determine total number of legal selectors, then it will call the other functions -to retrieve the name and pins of the group. Maintaining the data structure of -the groups is up to the driver, this is just a simple example - in practice you -may need more entries in your group structure, for example specific register -ranges associated with each group and so on. +The pin control subsystem will call the .list_groups() function repeatedly +beginning on 0 until it returns non-zero to determine legal selectors, then +it will call the other functions to retrieve the name and pins of the group. +Maintaining the data structure of the groups is up to the driver, this is +just a simple example - in practice you may need more entries in your group +structure, for example specific register ranges associated with each group +and so on. Pin configuration @@ -603,9 +606,11 @@ static const struct foo_group foo_groups[] = { }; -static int foo_get_groups_count(struct pinctrl_dev *pctldev) +static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_groups); + if (selector >= ARRAY_SIZE(foo_groups)) + return -EINVAL; + return 0; } static const char *foo_get_group_name(struct pinctrl_dev *pctldev, @@ -624,7 +629,7 @@ static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, + .list_groups = foo_list_groups, .get_group_name = foo_get_group_name, .get_group_pins = foo_get_group_pins, }; @@ -635,7 +640,7 @@ struct foo_pmx_func { const unsigned num_groups; }; -static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; +static const char * const spi0_groups[] = { "spi0_1_grp" }; static const char * const i2c0_groups[] = { "i2c0_grp" }; static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", "mmc0_3_grp" }; @@ -658,9 +663,11 @@ static const struct foo_pmx_func foo_functions[] = { }, }; -int foo_get_functions_count(struct pinctrl_dev *pctldev) +int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(foo_functions); + if (selector >= ARRAY_SIZE(foo_functions)) + return -EINVAL; + return 0; } const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) @@ -696,7 +703,7 @@ void foo_disable(struct pinctrl_dev *pctldev, unsigned selector, } struct pinmux_ops foo_pmxops = { - .get_functions_count = foo_get_functions_count, + .list_functions = foo_list_funcs, .get_function_name = foo_get_fname, .get_function_groups = foo_get_groups, .enable = foo_enable, @@ -779,7 +786,7 @@ and spi on the second function mapping: #include -static const struct pinctrl_map mapping[] __initconst = { +static const struct pinctrl_map __initdata mapping[] = { { .dev_name = "foo-spi.0", .name = PINCTRL_STATE_DEFAULT, @@ -945,13 +952,13 @@ case), we define a mapping like this: The result of grabbing this mapping from the device with something like this (see next paragraph): - p = devm_pinctrl_get(dev); + p = pinctrl_get(dev); s = pinctrl_lookup_state(p, "8bit"); ret = pinctrl_select_state(p, s); or more simply: - p = devm_pinctrl_get_select(dev, "8bit"); + p = pinctrl_get_select(dev, "8bit"); Will be that you activate all the three bottom records in the mapping at once. Since they share the same name, pin controller device, function and @@ -985,7 +992,7 @@ foo_probe() /* Allocate a state holder named "foo" etc */ struct foo_state *foo = ...; - foo->p = devm_pinctrl_get(&device); + foo->p = pinctrl_get(&device); if (IS_ERR(foo->p)) { /* FIXME: clean up "foo" here */ return PTR_ERR(foo->p); @@ -993,17 +1000,24 @@ foo_probe() foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); if (IS_ERR(foo->s)) { + pinctrl_put(foo->p); /* FIXME: clean up "foo" here */ return PTR_ERR(s); } ret = pinctrl_select_state(foo->s); if (ret < 0) { + pinctrl_put(foo->p); /* FIXME: clean up "foo" here */ return ret; } } +foo_remove() +{ + pinctrl_put(state->p); +} + This get/lookup/select/put sequence can just as well be handled by bus drivers if you don't want each and every driver to handle it and you know the arrangement on your bus. @@ -1015,11 +1029,6 @@ The semantics of the pinctrl APIs are: kernel memory to hold the pinmux state. All mapping table parsing or similar slow operations take place within this API. -- devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() - to be called automatically on the retrieved pointer when the associated - device is removed. It is recommended to use this function over plain - pinctrl_get(). - - pinctrl_lookup_state() is called in process context to obtain a handle to a specific state for a the client device. This operation may be slow too. @@ -1032,30 +1041,14 @@ The semantics of the pinctrl APIs are: - pinctrl_put() frees all information associated with a pinctrl handle. -- devm_pinctrl_put() is a variant of pinctrl_put() that may be used to - explicitly destroy a pinctrl object returned by devm_pinctrl_get(). - However, use of this function will be rare, due to the automatic cleanup - that will occur even without calling it. - - pinctrl_get() must be paired with a plain pinctrl_put(). - pinctrl_get() may not be paired with devm_pinctrl_put(). - devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). - devm_pinctrl_get() may not be paired with plain pinctrl_put(). - Usually the pin control core handled the get/put pair and call out to the device drivers bookkeeping operations, like checking available functions and the associated pins, whereas the enable/disable pass on to the pin controller driver which takes care of activating and/or deactivating the mux setting by quickly poking some registers. -The pins are allocated for your device when you issue the devm_pinctrl_get() -call, after this you should be able to see this in the debugfs listing of all -pins. - -NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the -requested pinctrl handles, for example if the pinctrl driver has not yet -registered. Thus make sure that the error path in your driver gracefully -cleans up and is ready to retry the probing later in the startup process. +The pins are allocated for your device when you issue the pinctrl_get() call, +after this you should be able to see this in the debugfs listing of all pins. System pin control hogging @@ -1101,13 +1094,13 @@ it, disables and releases it, and muxes it in on the pins defined by group B: #include -struct pinctrl *p; -struct pinctrl_state *s1, *s2; - -foo_probe() +foo_switch() { + struct pinctrl *p; + struct pinctrl_state *s1, *s2; + /* Setup */ - p = devm_pinctrl_get(&device); + p = pinctrl_get(&device); if (IS_ERR(p)) ... @@ -1118,10 +1111,7 @@ foo_probe() s2 = pinctrl_lookup_state(foo->p, "pos-B"); if (IS_ERR(s2)) ... -} -foo_switch() -{ /* Enable on position A */ ret = pinctrl_select_state(s1); if (ret < 0) @@ -1135,6 +1125,8 @@ foo_switch() ... ... + + pinctrl_put(p); } The above has to be done from process context. diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 27085a75162f..b0f1073c40b0 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -1882,16 +1882,6 @@ F: Documentation/filesystems/coda.txt F: fs/coda/ F: include/linux/coda*.h -COMMON CLK FRAMEWORK -M: Mike Turquette -M: Mike Turquette -L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV) -T: git git://git.linaro.org/people/mturquette/linux.git -S: Maintained -F: drivers/clk/clk.c -F: drivers/clk/clk-* -F: include/linux/clk-pr* - COMMON INTERNET FILE SYSTEM (CIFS) M: Steve French L: linux-cifs@vger.kernel.org @@ -2331,9 +2321,9 @@ S: Supported F: drivers/acpi/dock.c DOCUMENTATION -M: Rob Landley +M: Randy Dunlap L: linux-doc@vger.kernel.org -T: TBD +T: quilt http://xenotime.net/kernel-doc-patches/current/ S: Maintained F: Documentation/ @@ -5244,14 +5234,6 @@ M: Linus Walleij S: Maintained F: drivers/pinctrl/ -PIN CONTROLLER - ST SPEAR -M: Viresh Kumar -L: spear-devel@list.st.com -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -W: http://www.st.com/spear -S: Maintained -F: driver/pinctrl/spear/ - PKTCDVD DRIVER M: Peter Osterlund S: Maintained @@ -6344,7 +6326,24 @@ L: spear-devel@list.st.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) W: http://www.st.com/spear S: Maintained -F: drivers/clk/spear/ +F: arch/arm/mach-spear*/clock.c +F: arch/arm/plat-spear/clock.c +F: arch/arm/plat-spear/include/plat/clock.h + +SPEAR PAD MULTIPLEXING SUPPORT +M: Viresh Kumar +L: spear-devel@list.st.com +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +W: http://www.st.com/spear +S: Maintained +F: arch/arm/plat-spear/include/plat/padmux.h +F: arch/arm/plat-spear/padmux.c +F: arch/arm/mach-spear*/spear*xx.c +F: arch/arm/mach-spear*/include/mach/generic.h +F: arch/arm/mach-spear3xx/spear3*0.c +F: arch/arm/mach-spear3xx/spear3*0_evb.c +F: arch/arm/mach-spear6xx/spear600.c +F: arch/arm/mach-spear6xx/spear600_evb.c SPI SUBSYSTEM M: Grant Likely diff --git a/trunk/Makefile b/trunk/Makefile index afc868e6c75d..f6578f47e21e 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 4 SUBLEVEL = 0 -EXTRAVERSION = -rc4 +EXTRAVERSION = -rc3 NAME = Saber-toothed Squirrel # *DOCUMENTATION* diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index ce030c242644..cf006d40342c 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -980,7 +980,6 @@ config PLAT_SPEAR select ARM_AMBA select ARCH_REQUIRE_GPIOLIB select CLKDEV_LOOKUP - select COMMON_CLK select CLKSRC_MMIO select GENERIC_CLOCKEVENTS select HAVE_CLK diff --git a/trunk/arch/arm/boot/dts/spear300-evb.dts b/trunk/arch/arm/boot/dts/spear300-evb.dts index 402ca0d55011..6a79d69775b5 100644 --- a/trunk/arch/arm/boot/dts/spear300-evb.dts +++ b/trunk/arch/arm/boot/dts/spear300-evb.dts @@ -25,44 +25,6 @@ }; ahb { - pinmux@99000000 { - st,pinmux-mode = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - clcd { - st,pins = "clcd_pfmode_grp"; - st,function = "clcd"; - }; - sdhci { - st,pins = "sdhci_4bit_grp"; - st,function = "sdhci"; - }; - gpio1 { - st,pins = "gpio1_4_to_7_grp", - "gpio1_0_to_3_grp"; - st,function = "gpio1"; - }; - }; - }; - clcd@60000000 { status = "okay"; }; @@ -119,87 +81,87 @@ }; kbd@a0000000 { - linux,keymap = < 0x00010000 - 0x00020100 - 0x00030200 - 0x00040300 - 0x00050400 - 0x00060500 - 0x00070600 - 0x00080700 - 0x00090800 - 0x000a0001 - 0x000c0101 - 0x000d0201 - 0x000e0301 - 0x000f0401 - 0x00100501 - 0x00110601 - 0x00120701 - 0x00130801 - 0x00140002 - 0x00150102 - 0x00160202 - 0x00170302 - 0x00180402 - 0x00190502 - 0x001a0602 - 0x001b0702 - 0x001c0802 - 0x001d0003 - 0x001e0103 - 0x001f0203 - 0x00200303 - 0x00210403 - 0x00220503 - 0x00230603 - 0x00240703 - 0x00250803 - 0x00260004 - 0x00270104 - 0x00280204 - 0x00290304 - 0x002a0404 - 0x002b0504 - 0x002c0604 - 0x002d0704 - 0x002e0804 - 0x002f0005 - 0x00300105 - 0x00310205 - 0x00320305 - 0x00330405 - 0x00340505 - 0x00350605 - 0x00360705 - 0x00370805 - 0x00380006 - 0x00390106 - 0x003a0206 - 0x003b0306 - 0x003c0406 - 0x003d0506 - 0x003e0606 - 0x003f0706 - 0x00400806 - 0x00410007 - 0x00420107 - 0x00430207 - 0x00440307 - 0x00450407 - 0x00460507 - 0x00470607 - 0x00480707 - 0x00490807 - 0x004a0008 - 0x004b0108 - 0x004c0208 - 0x004d0308 - 0x004e0408 - 0x004f0508 - 0x00500608 - 0x00510708 - 0x00520808 >; + linux,keymap = < 0x00000001 + 0x00010002 + 0x00020003 + 0x00030004 + 0x00040005 + 0x00050006 + 0x00060007 + 0x00070008 + 0x00080009 + 0x0100000a + 0x0101000c + 0x0102000d + 0x0103000e + 0x0104000f + 0x01050010 + 0x01060011 + 0x01070012 + 0x01080013 + 0x02000014 + 0x02010015 + 0x02020016 + 0x02030017 + 0x02040018 + 0x02050019 + 0x0206001a + 0x0207001b + 0x0208001c + 0x0300001d + 0x0301001e + 0x0302001f + 0x03030020 + 0x03040021 + 0x03050022 + 0x03060023 + 0x03070024 + 0x03080025 + 0x04000026 + 0x04010027 + 0x04020028 + 0x04030029 + 0x0404002a + 0x0405002b + 0x0406002c + 0x0407002d + 0x0408002e + 0x0500002f + 0x05010030 + 0x05020031 + 0x05030032 + 0x05040033 + 0x05050034 + 0x05060035 + 0x05070036 + 0x05080037 + 0x06000038 + 0x06010039 + 0x0602003a + 0x0603003b + 0x0604003c + 0x0605003d + 0x0606003e + 0x0607003f + 0x06080040 + 0x07000041 + 0x07010042 + 0x07020043 + 0x07030044 + 0x07040045 + 0x07050046 + 0x07060047 + 0x07070048 + 0x07080049 + 0x0800004a + 0x0801004b + 0x0802004c + 0x0803004d + 0x0804004e + 0x0805004f + 0x08060050 + 0x08070051 + 0x08080052 >; autorepeat; st,mode = <0>; status = "okay"; diff --git a/trunk/arch/arm/boot/dts/spear300.dtsi b/trunk/arch/arm/boot/dts/spear300.dtsi index 01c5e358fdb2..f9fcbf4f477b 100644 --- a/trunk/arch/arm/boot/dts/spear300.dtsi +++ b/trunk/arch/arm/boot/dts/spear300.dtsi @@ -21,11 +21,6 @@ ranges = <0x60000000 0x60000000 0x50000000 0xd0000000 0xd0000000 0x30000000>; - pinmux@99000000 { - compatible = "st,spear300-pinmux"; - reg = <0x99000000 0x1000>; - }; - clcd@60000000 { compatible = "arm,clcd-pl110", "arm,primecell"; reg = <0x60000000 0x1000>; diff --git a/trunk/arch/arm/boot/dts/spear310-evb.dts b/trunk/arch/arm/boot/dts/spear310-evb.dts index 6d95317100ad..c86af33f700e 100644 --- a/trunk/arch/arm/boot/dts/spear310-evb.dts +++ b/trunk/arch/arm/boot/dts/spear310-evb.dts @@ -25,67 +25,6 @@ }; ahb { - pinmux@b4000000 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - gpio0 { - st,pins = "gpio0_pin0_grp", - "gpio0_pin1_grp", - "gpio0_pin2_grp", - "gpio0_pin3_grp", - "gpio0_pin4_grp", - "gpio0_pin5_grp"; - st,function = "gpio0"; - }; - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - emi { - st,pins = "emi_cs_0_to_5_grp"; - st,function = "emi"; - }; - fsmc { - st,pins = "fsmc_grp"; - st,function = "fsmc"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - uart3 { - st,pins = "uart3_grp"; - st,function = "uart3"; - }; - uart4 { - st,pins = "uart4_grp"; - st,function = "uart4"; - }; - uart5 { - st,pins = "uart5_grp"; - st,function = "uart5"; - }; - }; - }; - dma@fc400000 { status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/spear310.dtsi b/trunk/arch/arm/boot/dts/spear310.dtsi index e47081c494d9..dc7fa14da846 100644 --- a/trunk/arch/arm/boot/dts/spear310.dtsi +++ b/trunk/arch/arm/boot/dts/spear310.dtsi @@ -22,11 +22,6 @@ 0xb0000000 0xb0000000 0x10000000 0xd0000000 0xd0000000 0x30000000>; - pinmux@b4000000 { - compatible = "st,spear310-pinmux"; - reg = <0xb4000000 0x1000>; - }; - fsmc: flash@44000000 { compatible = "st,spear600-fsmc-nand"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/spear320-evb.dts b/trunk/arch/arm/boot/dts/spear320-evb.dts index 0c6463b71a37..d43de712e863 100644 --- a/trunk/arch/arm/boot/dts/spear320-evb.dts +++ b/trunk/arch/arm/boot/dts/spear320-evb.dts @@ -25,67 +25,6 @@ }; ahb { - pinmux@b3000000 { - st,pinmux-mode = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - i2c0 { - st,pins = "i2c0_grp"; - st,function = "i2c0"; - }; - mii0 { - st,pins = "mii0_grp"; - st,function = "mii0"; - }; - ssp0 { - st,pins = "ssp0_grp"; - st,function = "ssp0"; - }; - uart0 { - st,pins = "uart0_grp"; - st,function = "uart0"; - }; - sdhci { - st,pins = "sdhci_cd_51_grp"; - st,function = "sdhci"; - }; - i2s { - st,pins = "i2s_grp"; - st,function = "i2s"; - }; - uart1 { - st,pins = "uart1_grp"; - st,function = "uart1"; - }; - uart2 { - st,pins = "uart2_grp"; - st,function = "uart2"; - }; - can0 { - st,pins = "can0_grp"; - st,function = "can0"; - }; - can1 { - st,pins = "can1_grp"; - st,function = "can1"; - }; - mii2 { - st,pins = "mii2_grp"; - st,function = "mii2"; - }; - pwm0_1 { - st,pins = "pwm0_1_pin_14_15_grp"; - st,function = "pwm0_1"; - }; - pwm2 { - st,pins = "pwm2_pin_13_grp"; - st,function = "pwm2"; - }; - }; - }; - clcd@90000000 { status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/spear320.dtsi b/trunk/arch/arm/boot/dts/spear320.dtsi index 5372ca399b1f..9a0267a5a0b7 100644 --- a/trunk/arch/arm/boot/dts/spear320.dtsi +++ b/trunk/arch/arm/boot/dts/spear320.dtsi @@ -18,14 +18,9 @@ #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - ranges = <0x40000000 0x40000000 0x80000000 + ranges = <0x40000000 0x40000000 0x70000000 0xd0000000 0xd0000000 0x30000000>; - pinmux@b3000000 { - compatible = "st,spear320-pinmux"; - reg = <0xb3000000 0x1000>; - }; - clcd@90000000 { compatible = "arm,clcd-pl110", "arm,primecell"; reg = <0x90000000 0x1000>; diff --git a/trunk/arch/arm/boot/dts/spear3xx.dtsi b/trunk/arch/arm/boot/dts/spear3xx.dtsi index 0ae7c8e86311..91072553963f 100644 --- a/trunk/arch/arm/boot/dts/spear3xx.dtsi +++ b/trunk/arch/arm/boot/dts/spear3xx.dtsi @@ -139,6 +139,12 @@ interrupts = <12>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <2>; + }; }; }; }; diff --git a/trunk/arch/arm/boot/dts/spear600.dtsi b/trunk/arch/arm/boot/dts/spear600.dtsi index d777e3a6f178..089f0a42c50e 100644 --- a/trunk/arch/arm/boot/dts/spear600.dtsi +++ b/trunk/arch/arm/boot/dts/spear600.dtsi @@ -177,6 +177,12 @@ interrupts = <28>; status = "disabled"; }; + + timer@f0000000 { + compatible = "st,spear-timer"; + reg = <0xf0000000 0x400>; + interrupts = <16>; + }; }; }; }; diff --git a/trunk/arch/arm/configs/imx_v4_v5_defconfig b/trunk/arch/arm/configs/imx_v4_v5_defconfig index 6b31cb60daab..b5ac644e12af 100644 --- a/trunk/arch/arm/configs/imx_v4_v5_defconfig +++ b/trunk/arch/arm/configs/imx_v4_v5_defconfig @@ -112,7 +112,6 @@ CONFIG_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_MC13XXX=y CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MC13783=y CONFIG_REGULATOR_MC13892=y CONFIG_FB=y diff --git a/trunk/arch/arm/configs/u8500_defconfig b/trunk/arch/arm/configs/u8500_defconfig index 7e84f453e8a6..889d73ac1ae1 100644 --- a/trunk/arch/arm/configs/u8500_defconfig +++ b/trunk/arch/arm/configs/u8500_defconfig @@ -8,6 +8,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_U8500=y +CONFIG_UX500_SOC_DB5500=y +CONFIG_UX500_SOC_DB8500=y CONFIG_MACH_HREFV60=y CONFIG_MACH_SNOWBALL=y CONFIG_MACH_U5500=y @@ -37,6 +39,7 @@ CONFIG_CAIF=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_MISC_DEVICES=y CONFIG_AB8500_PWM=y CONFIG_SENSORS_BH1780=y CONFIG_NETDEVICES=y @@ -62,18 +65,16 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_NOMADIK=y +CONFIG_I2C=y +CONFIG_I2C_NOMADIK=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_TC3589X=y -CONFIG_POWER_SUPPLY=y -CONFIG_AB8500_BM=y -CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y CONFIG_MFD_STMPE=y CONFIG_MFD_TC3589X=y CONFIG_AB5500_CORE=y CONFIG_AB8500_CORE=y -CONFIG_REGULATOR=y CONFIG_REGULATOR_AB8500=y # CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y diff --git a/trunk/arch/arm/mach-at91/at91rm9200_devices.c b/trunk/arch/arm/mach-at91/at91rm9200_devices.c index 05774e5b1cba..99ce5c955e39 100644 --- a/trunk/arch/arm/mach-at91/at91rm9200_devices.c +++ b/trunk/arch/arm/mach-at91/at91rm9200_devices.c @@ -1173,6 +1173,7 @@ void __init at91_add_device_serial(void) printk(KERN_INFO "AT91: No default serial console defined.\n"); } #else +void __init __deprecated at91_init_serial(struct at91_uart_config *config) {} void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} void __init at91_set_serial_console(unsigned portnr) {} void __init at91_add_device_serial(void) {} diff --git a/trunk/arch/arm/mach-at91/at91rm9200_time.c b/trunk/arch/arm/mach-at91/at91rm9200_time.c index 104ca40d8d18..dd7f782b0b91 100644 --- a/trunk/arch/arm/mach-at91/at91rm9200_time.c +++ b/trunk/arch/arm/mach-at91/at91rm9200_time.c @@ -23,7 +23,6 @@ #include #include #include -#include #include @@ -177,7 +176,6 @@ static struct clock_event_device clkevt = { }; void __iomem *at91_st_base; -EXPORT_SYMBOL_GPL(at91_st_base); void __init at91rm9200_ioremap_st(u32 addr) { diff --git a/trunk/arch/arm/mach-at91/board-rm9200ek.c b/trunk/arch/arm/mach-at91/board-rm9200ek.c index b2e4fe21f346..11cbaa8946fe 100644 --- a/trunk/arch/arm/mach-at91/board-rm9200ek.c +++ b/trunk/arch/arm/mach-at91/board-rm9200ek.c @@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = { }; #define EK_FLASH_BASE AT91_CHIPSELECT_0 -#define EK_FLASH_SIZE SZ_8M +#define EK_FLASH_SIZE SZ_2M static struct physmap_flash_data ek_flash_data = { .width = 2, diff --git a/trunk/arch/arm/mach-at91/board-sam9261ek.c b/trunk/arch/arm/mach-at91/board-sam9261ek.c index 065fed342424..c3f994462864 100644 --- a/trunk/arch/arm/mach-at91/board-sam9261ek.c +++ b/trunk/arch/arm/mach-at91/board-sam9261ek.c @@ -85,6 +85,8 @@ static struct resource dm9000_resource[] = { .flags = IORESOURCE_MEM }, [2] = { + .start = AT91_PIN_PC11, + .end = AT91_PIN_PC11, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE, } @@ -128,8 +130,6 @@ static struct sam9_smc_config __initdata dm9000_smc_config = { static void __init ek_add_device_dm9000(void) { - struct resource *r = &dm9000_resource[2]; - /* Configure chip-select 2 (DM9000) */ sam9_smc_configure(0, 2, &dm9000_smc_config); @@ -139,7 +139,6 @@ static void __init ek_add_device_dm9000(void) /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PC11, 0); - r->start = r->end = gpio_to_irq(AT91_PIN_PC11); platform_device_register(&dm9000_device); } #else diff --git a/trunk/arch/arm/mach-at91/clock.c b/trunk/arch/arm/mach-at91/clock.c index 6b692824c988..a0f4d7424cdc 100644 --- a/trunk/arch/arm/mach-at91/clock.c +++ b/trunk/arch/arm/mach-at91/clock.c @@ -35,7 +35,6 @@ #include "generic.h" void __iomem *at91_pmc_base; -EXPORT_SYMBOL_GPL(at91_pmc_base); /* * There's a lot more which can be done with clocks, including cpufreq diff --git a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h index ea2c57a86ca6..36604782a78f 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base; #define at91_pmc_write(field, value) \ __raw_writel(value, at91_pmc_base + field) #else -.extern at91_pmc_base +.extern at91_aic_base #endif #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ diff --git a/trunk/arch/arm/mach-at91/setup.c b/trunk/arch/arm/mach-at91/setup.c index f44a2e7272e3..97cc04dc8073 100644 --- a/trunk/arch/arm/mach-at91/setup.c +++ b/trunk/arch/arm/mach-at91/setup.c @@ -54,7 +54,6 @@ void __init at91_init_interrupts(unsigned int *priority) } void __iomem *at91_ramc_base[2]; -EXPORT_SYMBOL_GPL(at91_ramc_base); void __init at91_ioremap_ramc(int id, u32 addr, u32 size) { @@ -293,7 +292,6 @@ void __init at91_ioremap_rstc(u32 base_addr) } void __iomem *at91_matrix_base; -EXPORT_SYMBOL_GPL(at91_matrix_base); void __init at91_ioremap_matrix(u32 base_addr) { diff --git a/trunk/arch/arm/mach-bcmring/core.c b/trunk/arch/arm/mach-bcmring/core.c index adbfb1994582..22e4e0a28ad1 100644 --- a/trunk/arch/arm/mach-bcmring/core.c +++ b/trunk/arch/arm/mach-bcmring/core.c @@ -52,8 +52,8 @@ #include #include -static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL); -static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL); +static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL); +static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL); static struct clk pll1_clk = { .name = "PLL1", diff --git a/trunk/arch/arm/mach-imx/imx27-dt.c b/trunk/arch/arm/mach-imx/imx27-dt.c index ed38d03c61f2..861ceb8232d6 100644 --- a/trunk/arch/arm/mach-imx/imx27-dt.c +++ b/trunk/arch/arm/mach-imx/imx27-dt.c @@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = { static int __init imx27_avic_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { - irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL); + irq_domain_add_simple(np, 0); return 0; } @@ -44,9 +44,7 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np, { static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS; - gpio_irq_base -= 32; - irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, - NULL); + irq_domain_add_simple(np, gpio_irq_base); return 0; } diff --git a/trunk/arch/arm/mach-imx/mm-imx5.c b/trunk/arch/arm/mach-imx/mm-imx5.c index e10f3914fcfe..05250aed61fb 100644 --- a/trunk/arch/arm/mach-imx/mm-imx5.c +++ b/trunk/arch/arm/mach-imx/mm-imx5.c @@ -35,7 +35,7 @@ static void imx5_idle(void) } clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - if (!tzic_enable_wake()) + if (tzic_enable_wake() != 0) cpu_do_idle(); clk_disable(gpc_dvfs_clk); } diff --git a/trunk/arch/arm/mach-omap1/mux.c b/trunk/arch/arm/mach-omap1/mux.c index e9cc52d4cb28..087dba0df47e 100644 --- a/trunk/arch/arm/mach-omap1/mux.c +++ b/trunk/arch/arm/mach-omap1/mux.c @@ -27,7 +27,6 @@ #include #include -#include #include diff --git a/trunk/arch/arm/mach-omap1/timer.c b/trunk/arch/arm/mach-omap1/timer.c index fb202af01d0d..6e90665a7c47 100644 --- a/trunk/arch/arm/mach-omap1/timer.c +++ b/trunk/arch/arm/mach-omap1/timer.c @@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev, int n = (pdev->id - 1) << 1; u32 l; - l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); + l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n); l |= source << n; - omap_writel(l, MOD_CONF_CTRL_1); + __raw_writel(l, MOD_CONF_CTRL_1); return 0; } diff --git a/trunk/arch/arm/mach-omap2/board-4430sdp.c b/trunk/arch/arm/mach-omap2/board-4430sdp.c index 130ab00c09a2..a39fc4bbd2b8 100644 --- a/trunk/arch/arm/mach-omap2/board-4430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-4430sdp.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -561,7 +560,7 @@ static struct regulator_init_data sdp4430_vusim = { }, }; -static struct twl6040_codec_data twl6040_codec = { +static struct twl4030_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -569,7 +568,7 @@ static struct twl6040_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl6040_vibra_data twl6040_vibra = { +static struct twl4030_vibra_data twl6040_vibra = { .vibldrv_res = 8, .vibrdrv_res = 3, .viblmotor_res = 10, @@ -578,14 +577,16 @@ static struct twl6040_vibra_data twl6040_vibra = { .vddvibr_uV = 0, /* fixed volt supply - VBAT */ }; -static struct twl6040_platform_data twl6040_data = { +static struct twl4030_audio_data twl6040_audio = { .codec = &twl6040_codec, .vibra = &twl6040_vibra, .audpwron_gpio = 127, + .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; static struct twl4030_platform_data sdp4430_twldata = { + .audio = &twl6040_audio, /* Regulators */ .vusim = &sdp4430_vusim, .vaux1 = &sdp4430_vaux1, @@ -616,8 +617,7 @@ static int __init omap4_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &sdp4430_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &sdp4430_twldata); omap_register_i2c_bus(2, 400, NULL, 0); omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo, ARRAY_SIZE(sdp4430_i2c_3_boardinfo)); diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index 098d183a0086..74e1687b5170 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = { static void __init omap4_i2c_init(void) { - omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0); + omap4_pmic_init("twl6030", &sdp4430_twldata); } static void __init omap4_init(void) diff --git a/trunk/arch/arm/mach-omap2/board-omap4panda.c b/trunk/arch/arm/mach-omap2/board-omap4panda.c index 1b782ba53433..d8c0e89f0126 100644 --- a/trunk/arch/arm/mach-omap2/board-omap4panda.c +++ b/trunk/arch/arm/mach-omap2/board-omap4panda.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -285,7 +284,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) return 0; } -static struct twl6040_codec_data twl6040_codec = { +static struct twl4030_codec_data twl6040_codec = { /* single-step ramp for headset and handsfree */ .hs_left_step = 0x0f, .hs_right_step = 0x0f, @@ -293,14 +292,17 @@ static struct twl6040_codec_data twl6040_codec = { .hf_right_step = 0x1d, }; -static struct twl6040_platform_data twl6040_data = { +static struct twl4030_audio_data twl6040_audio = { .codec = &twl6040_codec, .audpwron_gpio = 127, + .naudint_irq = OMAP44XX_IRQ_SYS_2N, .irq_base = TWL6040_CODEC_IRQ_BASE, }; /* Panda board uses the common PMIC configuration */ -static struct twl4030_platform_data omap4_panda_twldata; +static struct twl4030_platform_data omap4_panda_twldata = { + .audio = &twl6040_audio, +}; /* * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM @@ -324,8 +326,7 @@ static int __init omap4_panda_i2c_init(void) TWL_COMMON_REGULATOR_VCXIO | TWL_COMMON_REGULATOR_VUSB | TWL_COMMON_REGULATOR_CLK32KG); - omap4_pmic_init("twl6030", &omap4_panda_twldata, - &twl6040_data, OMAP44XX_IRQ_SYS_2N); + omap4_pmic_init("twl6030", &omap4_panda_twldata); omap_register_i2c_bus(2, 400, NULL, 0); /* * Bus 3 is attached to the DVI port where devices like the pico DLP diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 7144ae651d3d..2c27fdb61e66 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -1422,9 +1422,6 @@ static int _ocp_softreset(struct omap_hwmod *oh) goto dis_opt_clks; _write_sysconfig(v, oh); - if (oh->class->sysc->srst_udelay) - udelay(oh->class->sysc->srst_udelay); - if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) @@ -1906,20 +1903,10 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) */ int omap_hwmod_softreset(struct omap_hwmod *oh) { - u32 v; - int ret; - - if (!oh || !(oh->_sysc_cache)) + if (!oh) return -EINVAL; - v = oh->_sysc_cache; - ret = _set_softreset(oh, &v); - if (ret) - goto error; - _write_sysconfig(v, oh); - -error: - return ret; + return _ocp_softreset(oh); } /** diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a6bde34e443a..a5409ce3f323 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -1000,6 +1000,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 04a3885f4475..c4f56cb60d7d 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -1049,6 +1049,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { .slave = &omap2430_dss_venc_hwmod, .clk = "dss_ick", .addr = omap2_dss_venc_addrs, + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index db86ce90c69f..34b9766d1d23 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1676,6 +1676,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { .flags = OMAP_FIREWALL_L4, } }, + .flags = OCPIF_SWSUP_IDLE, .user = OCP_USER_MPU | OCP_USER_SDMA, }; diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 6abc75753e42..cc9bd106a854 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -2594,15 +2594,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { .rev_offs = 0x0000, .sysc_offs = 0x0010, - /* - * ISS needs 100 OCP clk cycles delay after a softreset before - * accessing sysconfig again. - * The lowest frequency at the moment for L3 bus is 100 MHz, so - * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). - * - * TODO: Indicate errata when available. - */ - .srst_udelay = 2, .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | diff --git a/trunk/arch/arm/mach-omap2/serial.c b/trunk/arch/arm/mach-omap2/serial.c index 9fc2f44188cb..0cdd359a128e 100644 --- a/trunk/arch/arm/mach-omap2/serial.c +++ b/trunk/arch/arm/mach-omap2/serial.c @@ -108,14 +108,8 @@ static void omap_uart_set_noidle(struct platform_device *pdev) static void omap_uart_set_smartidle(struct platform_device *pdev) { struct omap_device *od = to_omap_device(pdev); - u8 idlemode; - if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP) - idlemode = HWMOD_IDLEMODE_SMART_WKUP; - else - idlemode = HWMOD_IDLEMODE_SMART; - - omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode); + omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART); } #else @@ -126,8 +120,124 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {} #endif /* CONFIG_PM */ #ifdef CONFIG_OMAP_MUX +static struct omap_device_pad default_uart1_pads[] __initdata = { + { + .name = "uart1_cts.uart1_cts", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart1_rts.uart1_rts", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart1_tx.uart1_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart1_rx.uart1_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, +}; + +static struct omap_device_pad default_uart2_pads[] __initdata = { + { + .name = "uart2_cts.uart2_cts", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart2_rts.uart2_rts", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart2_tx.uart2_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart2_rx.uart2_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, +}; + +static struct omap_device_pad default_uart3_pads[] __initdata = { + { + .name = "uart3_cts_rctx.uart3_cts_rctx", + .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0, + }, + { + .name = "uart3_rts_sd.uart3_rts_sd", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart3_tx_irtx.uart3_tx_irtx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart3_rx_irrx.uart3_rx_irrx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + }, +}; + +static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = { + { + .name = "gpmc_wait2.uart4_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "gpmc_wait3.uart4_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE2, + }, +}; + +static struct omap_device_pad default_omap4_uart4_pads[] __initdata = { + { + .name = "uart4_tx.uart4_tx", + .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0, + }, + { + .name = "uart4_rx.uart4_rx", + .flags = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP, + .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + .idle = OMAP_PIN_INPUT | OMAP_MUX_MODE0, + }, +}; + static void omap_serial_fill_default_pads(struct omap_board_data *bdata) { + switch (bdata->id) { + case 0: + bdata->pads = default_uart1_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads); + break; + case 1: + bdata->pads = default_uart2_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads); + break; + case 2: + bdata->pads = default_uart3_pads; + bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads); + break; + case 3: + if (cpu_is_omap44xx()) { + bdata->pads = default_omap4_uart4_pads; + bdata->pads_cnt = + ARRAY_SIZE(default_omap4_uart4_pads); + } else if (cpu_is_omap3630()) { + bdata->pads = default_omap36xx_uart4_pads; + bdata->pads_cnt = + ARRAY_SIZE(default_omap36xx_uart4_pads); + } + break; + default: + break; + } } #else static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {} diff --git a/trunk/arch/arm/mach-omap2/twl-common.c b/trunk/arch/arm/mach-omap2/twl-common.c index 7a7b89304c48..4b57757bf9d1 100644 --- a/trunk/arch/arm/mach-omap2/twl-common.c +++ b/trunk/arch/arm/mach-omap2/twl-common.c @@ -37,16 +37,6 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = { .flags = I2C_CLIENT_WAKE, }; -static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { - { - .addr = 0x48, - .flags = I2C_CLIENT_WAKE, - }, - { - I2C_BOARD_INFO("twl6040", 0x4b), - }, -}; - void __init omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data) @@ -59,31 +49,14 @@ void __init omap_pmic_init(int bus, u32 clkrate, omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1); } -void __init omap4_pmic_init(const char *pmic_type, - struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *twl6040_data, int twl6040_irq) -{ - /* PMIC part*/ - strncpy(omap4_i2c1_board_info[0].type, pmic_type, - sizeof(omap4_i2c1_board_info[0].type)); - omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N; - omap4_i2c1_board_info[0].platform_data = pmic_data; - - /* TWL6040 audio IC part */ - omap4_i2c1_board_info[1].irq = twl6040_irq; - omap4_i2c1_board_info[1].platform_data = twl6040_data; - - omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2); - -} - void __init omap_pmic_late_init(void) { /* Init the OMAP TWL parameters (if PMIC has been registerd) */ - if (pmic_i2c_board_info.irq) - omap3_twl_init(); - if (omap4_i2c1_board_info[0].irq) - omap4_twl_init(); + if (!pmic_i2c_board_info.irq) + return; + + omap3_twl_init(); + omap4_twl_init(); } #if defined(CONFIG_ARCH_OMAP3) diff --git a/trunk/arch/arm/mach-omap2/twl-common.h b/trunk/arch/arm/mach-omap2/twl-common.h index 09627483a57f..275dde8cb27a 100644 --- a/trunk/arch/arm/mach-omap2/twl-common.h +++ b/trunk/arch/arm/mach-omap2/twl-common.h @@ -29,7 +29,6 @@ struct twl4030_platform_data; -struct twl6040_platform_data; void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq, struct twl4030_platform_data *pmic_data); @@ -47,9 +46,12 @@ static inline void omap3_pmic_init(const char *pmic_type, omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data); } -void omap4_pmic_init(const char *pmic_type, - struct twl4030_platform_data *pmic_data, - struct twl6040_platform_data *audio_data, int twl6040_irq); +static inline void omap4_pmic_init(const char *pmic_type, + struct twl4030_platform_data *pmic_data) +{ + /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */ + omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data); +} void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, u32 pdata_flags, u32 regulators_flags); diff --git a/trunk/arch/arm/mach-spear3xx/Kconfig b/trunk/arch/arm/mach-spear3xx/Kconfig index 8bd37291fa4f..d9fe11cb6f16 100644 --- a/trunk/arch/arm/mach-spear3xx/Kconfig +++ b/trunk/arch/arm/mach-spear3xx/Kconfig @@ -7,19 +7,16 @@ if ARCH_SPEAR3XX menu "SPEAr3xx Implementations" config MACH_SPEAR300 bool "SPEAr300 Machine support with Device Tree" - select PINCTRL_SPEAR300 help Supports ST SPEAr300 machine configured via the device-tree config MACH_SPEAR310 bool "SPEAr310 Machine support with Device Tree" - select PINCTRL_SPEAR310 help Supports ST SPEAr310 machine configured via the device-tree config MACH_SPEAR320 bool "SPEAr320 Machine support with Device Tree" - select PINCTRL_SPEAR320 help Supports ST SPEAr320 machine configured via the device-tree endmenu diff --git a/trunk/arch/arm/mach-spear3xx/Makefile b/trunk/arch/arm/mach-spear3xx/Makefile index 8d12faa178fd..17b5d83cf2d5 100644 --- a/trunk/arch/arm/mach-spear3xx/Makefile +++ b/trunk/arch/arm/mach-spear3xx/Makefile @@ -3,7 +3,7 @@ # # common files -obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o +obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx.o clock.o # spear300 specific files obj-$(CONFIG_MACH_SPEAR300) += spear300.o diff --git a/trunk/arch/arm/mach-spear3xx/clock.c b/trunk/arch/arm/mach-spear3xx/clock.c new file mode 100644 index 000000000000..cd6c11099083 --- /dev/null +++ b/trunk/arch/arm/mach-spear3xx/clock.c @@ -0,0 +1,892 @@ +/* + * arch/arm/mach-spear3xx/clock.c + * + * SPEAr3xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ (MISC_BASE + 0x018) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG (MISC_BASE + 0x028) +/* PERIP_CLK_CFG register masks */ +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 11 +#define GPT2_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 + +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) +/* PERIP1_CLK_ENB register masks */ +#define UART_CLK_ENB 3 +#define SSP_CLK_ENB 5 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FIRDA_CLK_ENB 10 +#define GPT1_CLK_ENB 11 +#define GPT2_CLK_ENB 12 +#define ADC_CLK_ENB 15 +#define RTC_CLK_ENB 17 +#define GPIO_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH_CLK_ENB 25 +#define C3_CLK_ENB 31 + +#define RAS_CLK_ENB (MISC_BASE + 0x034) + +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32000, +}; + +/* 24 MHz oscillator clock */ +static struct clk osc_24m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 24000000, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from 24 MHz osc clk */ +/* pll masks structure */ +static struct pll_clk_masks pll1_masks = { + .mode_mask = PLL_MODE_MASK, + .mode_shift = PLL_MODE_SHIFT, + .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, + .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, + .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, + .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, + .div_p_mask = PLL_DIV_P_MASK, + .div_p_shift = PLL_DIV_P_SHIFT, + .div_n_mask = PLL_DIV_N_MASK, + .div_n_shift = PLL_DIV_N_SHIFT, +}; + +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, + .masks = &pll1_masks, +}; + +/* pll rate configuration table, in ascending order of rates */ +struct pll_rate_tbl pll_rtbl[] = { + {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ + {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .flags = ENABLED_ON_INIT, + .pclk = &osc_24m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .calc_rate = &pll_calc_rate, + .recalc = &pll_clk_recalc, + .set_rate = &pll_clk_set_rate, + .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, + .private_data = &pll1_config, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .rate = 48000000, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_24m_clk, + .recalc = &follow_parent, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +/* ahb masks structure */ +static struct bus_clk_masks ahb_masks = { + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .masks = &ahb_masks, +}; + +/* ahb rate configuration table, in ascending order of rates */ +struct bus_rate_tbl bus_rtbl[] = { + {.div = 3}, /* == parent divided by 4 */ + {.div = 2}, /* == parent divided by 3 */ + {.div = 1}, /* == parent divided by 2 */ + {.div = 0}, /* == parent divided by 1 */ +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &bus_calc_rate, + .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, + .private_data = &ahb_config, +}; + +/* auxiliary synthesizers masks */ +static struct aux_clk_masks aux_masks = { + .eq_sel_mask = AUX_EQ_SEL_MASK, + .eq_sel_shift = AUX_EQ_SEL_SHIFT, + .eq1_mask = AUX_EQ1_SEL, + .eq2_mask = AUX_EQ2_SEL, + .xscale_sel_mask = AUX_XSCALE_MASK, + .xscale_sel_shift = AUX_XSCALE_SHIFT, + .yscale_sel_mask = AUX_YSCALE_MASK, + .yscale_sel_shift = AUX_YSCALE_SHIFT, +}; + +/* uart synth configurations */ +static struct aux_clk_config uart_synth_config = { + .synth_reg = UART_CLK_SYNT, + .masks = &aux_masks, +}; + +/* aux rate configuration table, in ascending order of rates */ +struct aux_rate_tbl aux_rtbl[] = { + /* For PLL1 = 332 MHz */ + {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ + {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ + {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ +}; + +/* uart synth clock */ +static struct clk uart_synth_clk = { + .en_reg = UART_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, + .private_data = &uart_synth_config, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &uart_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart clock */ +static struct clk uart_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* firda configurations */ +static struct aux_clk_config firda_synth_config = { + .synth_reg = FIRDA_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk firda_synth_clk = { + .en_reg = FIRDA_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 1}, + .private_data = &firda_synth_config, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &firda_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt synthesizer masks */ +static struct gpt_clk_masks gpt_masks = { + .mscale_sel_mask = GPT_MSCALE_MASK, + .mscale_sel_shift = GPT_MSCALE_SHIFT, + .nscale_sel_mask = GPT_NSCALE_MASK, + .nscale_sel_shift = GPT_NSCALE_SHIFT, +}; + +/* gpt rate configuration table, in ascending order of rates */ +struct gpt_rate_tbl gpt_rtbl[] = { + /* For pll1 = 332 MHz */ + {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ + {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ + {.mscale = 1, .nscale = 0}, /* 83 MHz */ +}; + +/* gpt0 synth clk config*/ +static struct gpt_clk_config gpt0_synth_config = { + .synth_reg = PRSC1_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt0_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt0_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt0_pclk_info[] = { + { + .pclk = &gpt0_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt0_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0 timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt0_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt1 synth clk configurations */ +static struct gpt_clk_config gpt1_synth_config = { + .synth_reg = PRSC2_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt1 synth clock */ +static struct clk gpt1_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt1_synth_config, +}; + +static struct pclk_info gpt1_pclk_info[] = { + { + .pclk = &gpt1_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt1_pclk_sel = { + .pclk_info = gpt1_pclk_info, + .pclk_count = ARRAY_SIZE(gpt1_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT1_CLK_ENB, + .pclk_sel = &gpt1_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt2 synth clk configurations */ +static struct gpt_clk_config gpt2_synth_config = { + .synth_reg = PRSC3_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt1 synth clock */ +static struct clk gpt2_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt2_synth_config, +}; + +static struct pclk_info gpt2_pclk_info[] = { + { + .pclk = &gpt2_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt2_pclk_sel = { + .pclk_info = gpt2_pclk_info, + .pclk_count = ARRAY_SIZE(gpt2_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPT2_CLK_ENB, + .pclk_sel = &gpt2_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* clock derived from pll3 clk */ +/* usbh clock */ +static struct clk usbh_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from usbh clk */ +/* usbh0 clock */ +static struct clk usbh0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &usbh_clk, + .recalc = &follow_parent, +}; + +/* usbh1 clock */ +static struct clk usbh1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &usbh_clk, + .recalc = &follow_parent, +}; + +/* clock derived from ahb clk */ +/* apb masks structure */ +static struct bus_clk_masks apb_masks = { + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .masks = &apb_masks, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .calc_rate = &bus_calc_rate, + .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, + .private_data = &apb_config, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +/* c3 clock */ +static struct clk c3_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = C3_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* emi clock */ +static struct clk emi_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif + +/* ssp clock */ +static struct clk ssp0_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio clock */ +static struct clk gpio_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk dummy_apb_pclk; + +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \ + defined(CONFIG_MACH_SPEAR320) +/* fsmc clock */ +static struct clk fsmc_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif + +/* common clocks to spear310 and spear320 */ +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* uart1 clock */ +static struct clk uart1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart2 clock */ +static struct clk uart2_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ + +/* common clocks to spear300 and spear320 */ +#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320) +/* clcd clock */ +static struct clk clcd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll3_48m_clk, + .recalc = &follow_parent, +}; + +/* sdhci clock */ +static struct clk sdhci_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; +#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */ + +/* spear300 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR300 +/* gpio1 clock */ +static struct clk gpio1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* keyboard clock */ +static struct clk kbd_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +#endif + +/* spear310 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR310 +/* uart3 clock */ +static struct clk uart3_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart4 clock */ +static struct clk uart4_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* uart5 clock */ +static struct clk uart5_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif + +/* spear320 machine specific clock structures */ +#ifdef CONFIG_MACH_SPEAR320 +/* can0 clock */ +static struct clk can0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* can1 clock */ +static struct clk can1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* i2c1 clock */ +static struct clk i2c1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .recalc = &follow_parent, +}; + +/* ssp1 clock */ +static struct clk ssp1_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* ssp2 clock */ +static struct clk ssp2_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* pwm clock */ +static struct clk pwm_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; +#endif + +/* array of all spear 3xx clock lookups */ +static struct clk_lookup spear_clk_lookups[] = { + CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + /* root clks */ + CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), + CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk), + /* clock derived from 32 KHz osc clk */ + CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk), + /* clock derived from 24 MHz osc clk */ + CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), + CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), + CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk), + /* clock derived from pll1 clk */ + CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), + CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), + CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), + CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), + CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), + CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk), + CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), + CLKDEV_INIT("d0000000.serial", NULL, &uart_clk), + CLKDEV_INIT("firda", NULL, &firda_clk), + CLKDEV_INIT("gpt0", NULL, &gpt0_clk), + CLKDEV_INIT("gpt1", NULL, &gpt1_clk), + CLKDEV_INIT("gpt2", NULL, &gpt2_clk), + /* clock derived from pll3 clk */ + CLKDEV_INIT("designware_udc", NULL, &usbd_clk), + CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk), + /* clock derived from usbh clk */ + CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), + CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + /* clock derived from ahb clk */ + CLKDEV_INIT(NULL, "apb_clk", &apb_clk), + CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk), + CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), + CLKDEV_INIT("jpeg", NULL, &jpeg_clk), + CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk), + CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), + CLKDEV_INIT("c3", NULL, &c3_clk), + /* clock derived from apb clk */ + CLKDEV_INIT("adc", NULL, &adc_clk), + CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk), + CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk), +}; + +/* array of all spear 300 clock lookups */ +#ifdef CONFIG_MACH_SPEAR300 +static struct clk_lookup spear300_clk_lookups[] = { + CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk), + CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk), + CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk), + CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk), + CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), +}; + +void __init spear300_clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++) + clk_register(&spear300_clk_lookups[i]); + + clk_init(); +} +#endif + +/* array of all spear 310 clock lookups */ +#ifdef CONFIG_MACH_SPEAR310 +static struct clk_lookup spear310_clk_lookups[] = { + CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk), + CLKDEV_INIT(NULL, "emi", &emi_clk), + CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk), + CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk), + CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk), + CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk), + CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk), +}; + +void __init spear310_clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++) + clk_register(&spear310_clk_lookups[i]); + + clk_init(); +} +#endif + +/* array of all spear 320 clock lookups */ +#ifdef CONFIG_MACH_SPEAR320 +static struct clk_lookup spear320_clk_lookups[] = { + CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk), + CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk), + CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk), + CLKDEV_INIT(NULL, "emi", &emi_clk), + CLKDEV_INIT("pwm", NULL, &pwm_clk), + CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk), + CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk), + CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk), + CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk), + CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk), + CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk), + CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk), +}; + +void __init spear320_clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++) + clk_register(&spear320_clk_lookups[i]); + + clk_init(); +} +#endif diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h index c10eac6c10cb..efb69357429a 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/generic.h @@ -20,15 +20,7 @@ #include #include #include - -/* spear3xx declarations */ -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2 +#include /* Add spear3xx family device structure declarations here */ extern struct sys_timer spear3xx_timer; @@ -36,11 +28,155 @@ extern struct pl022_ssp_controller pl022_plat_data; extern struct pl08x_platform_data pl080_plat_data; /* Add spear3xx family function declarations here */ -void __init spear_setup_timer(void); -void __init spear3xx_clk_init(void); +void __init spear_setup_of_timer(void); void __init spear3xx_map_io(void); void __init spear3xx_dt_init_irq(void); void spear_restart(char, const char *); +/* pad mux declarations */ +#define PMX_FIRDA_MASK (1 << 14) +#define PMX_I2C_MASK (1 << 13) +#define PMX_SSP_CS_MASK (1 << 12) +#define PMX_SSP_MASK (1 << 11) +#define PMX_MII_MASK (1 << 10) +#define PMX_GPIO_PIN0_MASK (1 << 9) +#define PMX_GPIO_PIN1_MASK (1 << 8) +#define PMX_GPIO_PIN2_MASK (1 << 7) +#define PMX_GPIO_PIN3_MASK (1 << 6) +#define PMX_GPIO_PIN4_MASK (1 << 5) +#define PMX_GPIO_PIN5_MASK (1 << 4) +#define PMX_UART0_MODEM_MASK (1 << 3) +#define PMX_UART0_MASK (1 << 2) +#define PMX_TIMER_3_4_MASK (1 << 1) +#define PMX_TIMER_1_2_MASK (1 << 0) + +/* pad mux devices */ +extern struct pmx_dev spear3xx_pmx_firda; +extern struct pmx_dev spear3xx_pmx_i2c; +extern struct pmx_dev spear3xx_pmx_ssp_cs; +extern struct pmx_dev spear3xx_pmx_ssp; +extern struct pmx_dev spear3xx_pmx_mii; +extern struct pmx_dev spear3xx_pmx_gpio_pin0; +extern struct pmx_dev spear3xx_pmx_gpio_pin1; +extern struct pmx_dev spear3xx_pmx_gpio_pin2; +extern struct pmx_dev spear3xx_pmx_gpio_pin3; +extern struct pmx_dev spear3xx_pmx_gpio_pin4; +extern struct pmx_dev spear3xx_pmx_gpio_pin5; +extern struct pmx_dev spear3xx_pmx_uart0_modem; +extern struct pmx_dev spear3xx_pmx_uart0; +extern struct pmx_dev spear3xx_pmx_timer_3_4; +extern struct pmx_dev spear3xx_pmx_timer_1_2; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* padmux plgpio devices */ +extern struct pmx_dev spear3xx_pmx_plgpio_0_1; +extern struct pmx_dev spear3xx_pmx_plgpio_2_3; +extern struct pmx_dev spear3xx_pmx_plgpio_4_5; +extern struct pmx_dev spear3xx_pmx_plgpio_6_9; +extern struct pmx_dev spear3xx_pmx_plgpio_10_27; +extern struct pmx_dev spear3xx_pmx_plgpio_28; +extern struct pmx_dev spear3xx_pmx_plgpio_29; +extern struct pmx_dev spear3xx_pmx_plgpio_30; +extern struct pmx_dev spear3xx_pmx_plgpio_31; +extern struct pmx_dev spear3xx_pmx_plgpio_32; +extern struct pmx_dev spear3xx_pmx_plgpio_33; +extern struct pmx_dev spear3xx_pmx_plgpio_34_36; +extern struct pmx_dev spear3xx_pmx_plgpio_37_42; +extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48; +extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50; +#endif + +/* spear300 declarations */ +#ifdef CONFIG_MACH_SPEAR300 +/* pad mux modes */ +extern struct pmx_mode spear300_nand_mode; +extern struct pmx_mode spear300_nor_mode; +extern struct pmx_mode spear300_photo_frame_mode; +extern struct pmx_mode spear300_lend_ip_phone_mode; +extern struct pmx_mode spear300_hend_ip_phone_mode; +extern struct pmx_mode spear300_lend_wifi_phone_mode; +extern struct pmx_mode spear300_hend_wifi_phone_mode; +extern struct pmx_mode spear300_ata_pabx_wi2s_mode; +extern struct pmx_mode spear300_ata_pabx_i2s_mode; +extern struct pmx_mode spear300_caml_lcdw_mode; +extern struct pmx_mode spear300_camu_lcd_mode; +extern struct pmx_mode spear300_camu_wlcd_mode; +extern struct pmx_mode spear300_caml_lcd_mode; + +/* pad mux devices */ +extern struct pmx_dev spear300_pmx_fsmc_2_chips; +extern struct pmx_dev spear300_pmx_fsmc_4_chips; +extern struct pmx_dev spear300_pmx_keyboard; +extern struct pmx_dev spear300_pmx_clcd; +extern struct pmx_dev spear300_pmx_telecom_gpio; +extern struct pmx_dev spear300_pmx_telecom_tdm; +extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk; +extern struct pmx_dev spear300_pmx_telecom_camera; +extern struct pmx_dev spear300_pmx_telecom_dac; +extern struct pmx_dev spear300_pmx_telecom_i2s; +extern struct pmx_dev spear300_pmx_telecom_boot_pins; +extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit; +extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit; +extern struct pmx_dev spear300_pmx_gpio1; + +/* Add spear300 machine declarations here */ +void __init spear300_clk_init(void); + +#endif /* CONFIG_MACH_SPEAR300 */ + +/* spear310 declarations */ +#ifdef CONFIG_MACH_SPEAR310 +/* pad mux devices */ +extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5; +extern struct pmx_dev spear310_pmx_emi_cs_2_3; +extern struct pmx_dev spear310_pmx_uart1; +extern struct pmx_dev spear310_pmx_uart2; +extern struct pmx_dev spear310_pmx_uart3_4_5; +extern struct pmx_dev spear310_pmx_fsmc; +extern struct pmx_dev spear310_pmx_rs485_0_1; +extern struct pmx_dev spear310_pmx_tdm0; + +/* Add spear310 machine declarations here */ +void __init spear310_clk_init(void); + +#endif /* CONFIG_MACH_SPEAR310 */ + +/* spear320 declarations */ +#ifdef CONFIG_MACH_SPEAR320 +/* pad mux modes */ +extern struct pmx_mode spear320_auto_net_smii_mode; +extern struct pmx_mode spear320_auto_net_mii_mode; +extern struct pmx_mode spear320_auto_exp_mode; +extern struct pmx_mode spear320_small_printers_mode; + +/* pad mux devices */ +extern struct pmx_dev spear320_pmx_clcd; +extern struct pmx_dev spear320_pmx_emi; +extern struct pmx_dev spear320_pmx_fsmc; +extern struct pmx_dev spear320_pmx_spp; +extern struct pmx_dev spear320_pmx_sdhci; +extern struct pmx_dev spear320_pmx_i2s; +extern struct pmx_dev spear320_pmx_uart1; +extern struct pmx_dev spear320_pmx_uart1_modem; +extern struct pmx_dev spear320_pmx_uart2; +extern struct pmx_dev spear320_pmx_touchscreen; +extern struct pmx_dev spear320_pmx_can; +extern struct pmx_dev spear320_pmx_sdhci_led; +extern struct pmx_dev spear320_pmx_pwm0; +extern struct pmx_dev spear320_pmx_pwm1; +extern struct pmx_dev spear320_pmx_pwm2; +extern struct pmx_dev spear320_pmx_pwm3; +extern struct pmx_dev spear320_pmx_ssp1; +extern struct pmx_dev spear320_pmx_ssp2; +extern struct pmx_dev spear320_pmx_mii1; +extern struct pmx_dev spear320_pmx_smii0; +extern struct pmx_dev spear320_pmx_smii1; +extern struct pmx_dev spear320_pmx_i2c1; + +/* Add spear320 machine declarations here */ +void __init spear320_clk_init(void); + +#endif /* CONFIG_MACH_SPEAR320 */ + #endif /* __MACH_GENERIC_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h index defa374f5bee..40a8c178f10d 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -1,20 +1 @@ -/* - * arch/arm/mach-spear3xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr3xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include -#include - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h b/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h index 6e265442808e..51bd62a0254c 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -14,141 +14,14 @@ #ifndef __MACH_IRQS_H #define __MACH_IRQS_H -/* SPEAr3xx IRQ definitions */ -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0 +/* FIXME: probe all these from DT */ #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 -#define SPEAR3XX_IRQ_CPU_GPT1_1 2 -#define SPEAR3XX_IRQ_CPU_GPT1_2 3 -#define SPEAR3XX_IRQ_BASIC_GPT1_1 4 -#define SPEAR3XX_IRQ_BASIC_GPT1_2 5 -#define SPEAR3XX_IRQ_BASIC_GPT2_1 6 -#define SPEAR3XX_IRQ_BASIC_GPT2_2 7 -#define SPEAR3XX_IRQ_BASIC_DMA 8 -#define SPEAR3XX_IRQ_BASIC_SMI 9 -#define SPEAR3XX_IRQ_BASIC_RTC 10 -#define SPEAR3XX_IRQ_BASIC_GPIO 11 -#define SPEAR3XX_IRQ_BASIC_WDT 12 -#define SPEAR3XX_IRQ_DDR_CONTROLLER 13 -#define SPEAR3XX_IRQ_SYS_ERROR 14 -#define SPEAR3XX_IRQ_WAKEUP_RCV 15 -#define SPEAR3XX_IRQ_JPEG 16 -#define SPEAR3XX_IRQ_IRDA 17 -#define SPEAR3XX_IRQ_ADC 18 -#define SPEAR3XX_IRQ_UART 19 -#define SPEAR3XX_IRQ_SSP 20 -#define SPEAR3XX_IRQ_I2C 21 -#define SPEAR3XX_IRQ_MAC_1 22 -#define SPEAR3XX_IRQ_MAC_2 23 -#define SPEAR3XX_IRQ_USB_DEV 24 -#define SPEAR3XX_IRQ_USB_H_OHCI_0 25 -#define SPEAR3XX_IRQ_USB_H_EHCI_0 26 -#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0 -#define SPEAR3XX_IRQ_USB_H_OHCI_1 27 #define SPEAR3XX_IRQ_GEN_RAS_1 28 #define SPEAR3XX_IRQ_GEN_RAS_2 29 #define SPEAR3XX_IRQ_GEN_RAS_3 30 -#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31 #define SPEAR3XX_IRQ_VIC_END 32 - #define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END -/* SPEAr300 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) -#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) -#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) -#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) -#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) -#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) -#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) -#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) -#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM - -/* SPEAr310 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) -#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) -#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) -#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) -#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) -#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) -#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) -#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) -#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) -#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) -#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) - -/* SPEAr320 Virtual irq definitions */ -/* IRQs sharing IRQ_GEN_RAS_1 */ -#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) -#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) -#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) - -/* IRQs sharing IRQ_GEN_RAS_2 */ -#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 - -/* IRQs sharing IRQ_GEN_RAS_3 */ -#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) -#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) -#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) - -/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) -#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) -#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) -#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) -#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) -#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) -#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) -#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) -#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) -#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) -#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) - -/* - * GPIO pins virtual irqs - * Use the lowest number for the GPIO virtual IRQs base on which subarchs - * we have compiled in - */ -#if defined(CONFIG_MACH_SPEAR310) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18) -#elif defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17) -#else -#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9) -#endif - -#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_PLGPIO_COUNT 102 - -#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) -#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8) -#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \ - SPEAR3XX_PLGPIO_COUNT) -#else -#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8) -#endif - -#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END -#define NR_IRQS SPEAR3XX_VIRQ_END +#define NR_IRQS 160 #endif /* __MACH_IRQS_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 50cfe0d1a7c4..e0ab72e61507 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,9 +14,7 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include -#include - #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h index e7bc8bab83fe..04da906b0d4c 100644 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/trunk/arch/arm/mach-spear3xx/include/mach/spear.h @@ -15,61 +15,26 @@ #define __MACH_SPEAR3XX_H #include -#include -#include -#include - -#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) - -#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) #define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) -#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) -#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) -#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) - -/* ICM4 - High Speed Connection */ -#define SPEAR3XX_ICM4_BASE UL(0xE0000000) -#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) -#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) -#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ #define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) -#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) -#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) #define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) #define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE @@ -79,17 +44,4 @@ #define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE #define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE -/* SPEAr320 Macros */ -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) -#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000) -#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE) -#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018) - #define SPEAR320_UARTX_PCLK_MASK 0x1 - #define SPEAR320_UART2_PCLK_SHIFT 8 - #define SPEAR320_UART3_PCLK_SHIFT 9 - #define SPEAR320_UART4_PCLK_SHIFT 10 - #define SPEAR320_UART5_PCLK_SHIFT 11 - #define SPEAR320_UART6_PCLK_SHIFT 12 - #define SPEAR320_RS485_PCLK_SHIFT 13 - #endif /* __MACH_SPEAR3XX_H */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h deleted file mode 100644 index 3b6ea0729040..000000000000 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear300.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear300.h - * - * SPEAr300 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR300 - -#ifndef __MACH_SPEAR300_H -#define __MACH_SPEAR300_H - -/* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE UL(0x50000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR300_INT_ENB_MASK_REG 0x54 -#define SPEAR300_INT_STS_MASK_REG 0x58 -#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) -#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) -#define SPEAR300_I2S_IRQ_MASK (1 << 2) -#define SPEAR300_TDM_IRQ_MASK (1 << 3) -#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) -#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) -#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) -#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) -#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) - -#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF - -#define SPEAR300_CLCD_BASE UL(0x60000000) -#define SPEAR300_SDHCI_BASE UL(0x70000000) -#define SPEAR300_NAND_0_BASE UL(0x80000000) -#define SPEAR300_NAND_1_BASE UL(0x84000000) -#define SPEAR300_NAND_2_BASE UL(0x88000000) -#define SPEAR300_NAND_3_BASE UL(0x8c000000) -#define SPEAR300_NOR_0_BASE UL(0x90000000) -#define SPEAR300_NOR_1_BASE UL(0x91000000) -#define SPEAR300_NOR_2_BASE UL(0x92000000) -#define SPEAR300_NOR_3_BASE UL(0x93000000) -#define SPEAR300_FSMC_BASE UL(0x94000000) -#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) -#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) -#define SPEAR300_GPIO_BASE UL(0xA9000000) - -#endif /* __MACH_SPEAR300_H */ - -#endif /* CONFIG_MACH_SPEAR300 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h deleted file mode 100644 index 1567d0da725f..000000000000 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear310.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear310.h - * - * SPEAr310 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR310 - -#ifndef __MACH_SPEAR310_H -#define __MACH_SPEAR310_H - -#define SPEAR310_NAND_BASE UL(0x40000000) -#define SPEAR310_FSMC_BASE UL(0x44000000) -#define SPEAR310_UART1_BASE UL(0xB2000000) -#define SPEAR310_UART2_BASE UL(0xB2080000) -#define SPEAR310_UART3_BASE UL(0xB2100000) -#define SPEAR310_UART4_BASE UL(0xB2180000) -#define SPEAR310_UART5_BASE UL(0xB2200000) -#define SPEAR310_HDLC_BASE UL(0xB2800000) -#define SPEAR310_RS485_0_BASE UL(0xB3000000) -#define SPEAR310_RS485_1_BASE UL(0xB3800000) -#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR310_INT_STS_MASK_REG 0x04 -#define SPEAR310_SMII0_IRQ_MASK (1 << 0) -#define SPEAR310_SMII1_IRQ_MASK (1 << 1) -#define SPEAR310_SMII2_IRQ_MASK (1 << 2) -#define SPEAR310_SMII3_IRQ_MASK (1 << 3) -#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define SPEAR310_UART1_IRQ_MASK (1 << 8) -#define SPEAR310_UART2_IRQ_MASK (1 << 9) -#define SPEAR310_UART3_IRQ_MASK (1 << 10) -#define SPEAR310_UART4_IRQ_MASK (1 << 11) -#define SPEAR310_UART5_IRQ_MASK (1 << 12) -#define SPEAR310_EMI_IRQ_MASK (1 << 13) -#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) -#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) -#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) - -#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF -#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 -#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 -#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 - -#endif /* __MACH_SPEAR310_H */ - -#endif /* CONFIG_MACH_SPEAR310 */ diff --git a/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h b/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h deleted file mode 100644 index 8cfa83fa1296..000000000000 --- a/trunk/arch/arm/mach-spear3xx/include/mach/spear320.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * arch/arm/mach-spear3xx/include/mach/spear320.h - * - * SPEAr320 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR320 - -#ifndef __MACH_SPEAR320_H -#define __MACH_SPEAR320_H - -#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) -#define SPEAR320_FSMC_BASE UL(0x4C000000) -#define SPEAR320_NAND_BASE UL(0x50000000) -#define SPEAR320_I2S_BASE UL(0x60000000) -#define SPEAR320_SDHCI_BASE UL(0x70000000) -#define SPEAR320_CLCD_BASE UL(0x90000000) -#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) -#define SPEAR320_CAN0_BASE UL(0xA1000000) -#define SPEAR320_CAN1_BASE UL(0xA2000000) -#define SPEAR320_UART1_BASE UL(0xA3000000) -#define SPEAR320_UART2_BASE UL(0xA4000000) -#define SPEAR320_SSP0_BASE UL(0xA5000000) -#define SPEAR320_SSP1_BASE UL(0xA6000000) -#define SPEAR320_I2C_BASE UL(0xA7000000) -#define SPEAR320_PWM_BASE UL(0xA8000000) -#define SPEAR320_SMII0_BASE UL(0xAA000000) -#define SPEAR320_SMII1_BASE UL(0xAB000000) -#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) - -/* Interrupt registers offsets and masks */ -#define SPEAR320_INT_STS_MASK_REG 0x04 -#define SPEAR320_INT_CLR_MASK_REG 0x04 -#define SPEAR320_INT_ENB_MASK_REG 0x08 -#define SPEAR320_GPIO_IRQ_MASK (1 << 0) -#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) -#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) -#define SPEAR320_EMI_IRQ_MASK (1 << 7) -#define SPEAR320_CLCD_IRQ_MASK (1 << 8) -#define SPEAR320_SPP_IRQ_MASK (1 << 9) -#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) -#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) -#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) -#define SPEAR320_UART1_IRQ_MASK (1 << 13) -#define SPEAR320_UART2_IRQ_MASK (1 << 14) -#define SPEAR320_SSP1_IRQ_MASK (1 << 15) -#define SPEAR320_SSP2_IRQ_MASK (1 << 16) -#define SPEAR320_SMII0_IRQ_MASK (1 << 17) -#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) -#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) -#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) -#define SPEAR320_I2C1_IRQ_MASK (1 << 21) - -#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 -#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 -#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 - -#endif /* __MACH_SPEAR320_H */ - -#endif /* CONFIG_MACH_SPEAR320 */ diff --git a/trunk/arch/arm/mach-spear3xx/spear300.c b/trunk/arch/arm/mach-spear3xx/spear300.c index 2db0bd14e481..febcdd8d4e92 100644 --- a/trunk/arch/arm/mach-spear3xx/spear300.c +++ b/trunk/arch/arm/mach-spear3xx/spear300.c @@ -19,7 +19,397 @@ #include #include #include -#include +#include + +/* Base address of various IPs */ +#define SPEAR300_TELECOM_BASE UL(0x50000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR300_INT_ENB_MASK_REG 0x54 +#define SPEAR300_INT_STS_MASK_REG 0x58 +#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0) +#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1) +#define SPEAR300_I2S_IRQ_MASK (1 << 2) +#define SPEAR300_TDM_IRQ_MASK (1 << 3) +#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4) +#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5) +#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6) +#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7) +#define SPEAR300_GPIO1_IRQ_MASK (1 << 8) + +#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF + +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) + + +/* SPEAr300 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0) +#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1) +#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2) +#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3) +#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4) +#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5) +#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6) +#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7) +#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3 + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x00 +#define MODE_CONFIG_REG 0x04 + +/* modes */ +#define NAND_MODE (1 << 0) +#define NOR_MODE (1 << 1) +#define PHOTO_FRAME_MODE (1 << 2) +#define LEND_IP_PHONE_MODE (1 << 3) +#define HEND_IP_PHONE_MODE (1 << 4) +#define LEND_WIFI_PHONE_MODE (1 << 5) +#define HEND_WIFI_PHONE_MODE (1 << 6) +#define ATA_PABX_WI2S_MODE (1 << 7) +#define ATA_PABX_I2S_MODE (1 << 8) +#define CAML_LCDW_MODE (1 << 9) +#define CAMU_LCD_MODE (1 << 10) +#define CAMU_WLCD_MODE (1 << 11) +#define CAML_LCD_MODE (1 << 12) +#define ALL_MODES 0x1FFF + +struct pmx_mode spear300_nand_mode = { + .id = NAND_MODE, + .name = "nand mode", + .mask = 0x00, +}; + +struct pmx_mode spear300_nor_mode = { + .id = NOR_MODE, + .name = "nor mode", + .mask = 0x01, +}; + +struct pmx_mode spear300_photo_frame_mode = { + .id = PHOTO_FRAME_MODE, + .name = "photo frame mode", + .mask = 0x02, +}; + +struct pmx_mode spear300_lend_ip_phone_mode = { + .id = LEND_IP_PHONE_MODE, + .name = "lend ip phone mode", + .mask = 0x03, +}; + +struct pmx_mode spear300_hend_ip_phone_mode = { + .id = HEND_IP_PHONE_MODE, + .name = "hend ip phone mode", + .mask = 0x04, +}; + +struct pmx_mode spear300_lend_wifi_phone_mode = { + .id = LEND_WIFI_PHONE_MODE, + .name = "lend wifi phone mode", + .mask = 0x05, +}; + +struct pmx_mode spear300_hend_wifi_phone_mode = { + .id = HEND_WIFI_PHONE_MODE, + .name = "hend wifi phone mode", + .mask = 0x06, +}; + +struct pmx_mode spear300_ata_pabx_wi2s_mode = { + .id = ATA_PABX_WI2S_MODE, + .name = "ata pabx wi2s mode", + .mask = 0x07, +}; + +struct pmx_mode spear300_ata_pabx_i2s_mode = { + .id = ATA_PABX_I2S_MODE, + .name = "ata pabx i2s mode", + .mask = 0x08, +}; + +struct pmx_mode spear300_caml_lcdw_mode = { + .id = CAML_LCDW_MODE, + .name = "caml lcdw mode", + .mask = 0x0C, +}; + +struct pmx_mode spear300_camu_lcd_mode = { + .id = CAMU_LCD_MODE, + .name = "camu lcd mode", + .mask = 0x0D, +}; + +struct pmx_mode spear300_camu_wlcd_mode = { + .id = CAMU_WLCD_MODE, + .name = "camu wlcd mode", + .mask = 0x0E, +}; + +struct pmx_mode spear300_caml_lcd_mode = { + .id = CAML_LCD_MODE, + .name = "caml lcd mode", + .mask = 0x0F, +}; + +/* devices */ +static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear300_pmx_fsmc_2_chips = { + .name = "fsmc_2_chips", + .modes = pmx_fsmc_2_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = { + { + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear300_pmx_fsmc_4_chips = { + .name = "fsmc_4_chips", + .modes = pmx_fsmc_4_chips_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_keyboard_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE | + CAML_LCD_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear300_pmx_keyboard = { + .name = "keyboard", + .modes = pmx_keyboard_modes, + .mode_count = ARRAY_SIZE(pmx_keyboard_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK , + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | + CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_gpio_modes[] = { + { + .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK, + }, { + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK, + }, { + .ids = ATA_PABX_WI2S_MODE, + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK + | PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_gpio = { + .name = "telecom_gpio", + .modes = pmx_telecom_gpio_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_tdm_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_tdm = { + .name = "telecom_tdm", + .modes = pmx_telecom_tdm_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE + | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | + CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = { + .name = "telecom_spi_cs_i2c_clk", + .modes = pmx_telecom_spi_cs_i2c_clk_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_camera_modes[] = { + { + .ids = CAML_LCDW_MODE | CAML_LCD_MODE, + .mask = PMX_MII_MASK, + }, { + .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_camera = { + .name = "telecom_camera", + .modes = pmx_telecom_camera_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_dac_modes[] = { + { + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_dac = { + .name = "telecom_dac", + .modes = pmx_telecom_dac_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_i2s_modes[] = { + { + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE + | CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_i2s = { + .name = "telecom_i2s", + .modes = pmx_telecom_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = { + { + .ids = NAND_MODE | NOR_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_boot_pins = { + .name = "telecom_boot_pins", + .modes = pmx_telecom_boot_pins_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE | + ATA_PABX_I2S_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_sdhci_4bit = { + .name = "telecom_sdhci_4bit", + .modes = pmx_telecom_sdhci_4bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = { + { + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | + CAMU_WLCD_MODE | CAML_LCD_MODE, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, + }, +}; + +struct pmx_dev spear300_pmx_telecom_sdhci_8bit = { + .name = "telecom_sdhci_8bit", + .modes = pmx_telecom_sdhci_8bit_modes, + .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_gpio1_modes[] = { + { + .ids = PHOTO_FRAME_MODE, + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK | + PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear300_pmx_gpio1 = { + .name = "arm gpio1", + .modes = pmx_gpio1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -74,6 +464,22 @@ static struct spear_shirq shirq_ras1 = { }, }; +/* padmux devices to enable */ +static struct pmx_dev *spear300_evb_pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp_cs, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear300 specific devices */ + &spear300_pmx_fsmc_2_chips, + &spear300_pmx_clcd, + &spear300_pmx_telecom_sdhci_4bit, + &spear300_pmx_gpio1, +}; + /* DMAC platform data's slave info */ struct pl08x_channel_data spear300_dma_info[] = { { @@ -272,7 +678,7 @@ static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = { static void __init spear300_dt_init(void) { - int ret; + int ret = -EINVAL; pl080_plat_data.slave_channels = spear300_dma_info; pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info); @@ -287,6 +693,26 @@ static void __init spear300_dt_init(void) if (ret) pr_err("Error registering Shared IRQ\n"); } + + if (of_machine_is_compatible("st,spear300-evb")) { + /* pmx initialization */ + pmx_driver.mode = &spear300_photo_frame_mode; + pmx_driver.devs = spear300_evb_pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(spear300_evb_pmx_devs); + + pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K); + if (pmx_driver.base) { + ret = pmx_register(&pmx_driver); + if (ret) + pr_err("padmux: registration failed. err no: %d\n", + ret); + /* Free Mapping, device selection already done */ + iounmap(pmx_driver.base); + } + + if (ret) + pr_err("Initialization Failed"); + } } static const char * const spear300_dt_board_compat[] = { diff --git a/trunk/arch/arm/mach-spear3xx/spear310.c b/trunk/arch/arm/mach-spear3xx/spear310.c index aec07c951205..b26e41566b50 100644 --- a/trunk/arch/arm/mach-spear3xx/spear310.c +++ b/trunk/arch/arm/mach-spear3xx/spear310.c @@ -20,7 +20,189 @@ #include #include #include -#include +#include + +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) + +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 + +/* SPEAr310 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0) +#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1) +#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2) +#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3) +#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4) +#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5) +#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6) +#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12) + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13) +#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15) +#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16) +#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17) + + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x08 + +/* devices */ +static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { + .name = "emi_cs_0_1_4_5", + .modes = pmx_emi_cs_0_1_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear310_pmx_emi_cs_2_3 = { + .name = "emi_cs_2_3", + .modes = pmx_emi_cs_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear310_pmx_uart3_4_5 = { + .name = "uart3_4_5", + .modes = pmx_uart3_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear310_pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear310_pmx_rs485_0_1 = { + .name = "rs485_0_1", + .modes = pmx_rs485_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_tdm0_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear310_pmx_tdm0 = { + .name = "tdm0", + .modes = pmx_tdm0_modes, + .mode_count = ARRAY_SIZE(pmx_tdm0_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { @@ -138,6 +320,30 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; +/* padmux devices to enable */ +static struct pmx_dev *spear310_evb_pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_gpio_pin0, + &spear3xx_pmx_gpio_pin1, + &spear3xx_pmx_gpio_pin2, + &spear3xx_pmx_gpio_pin3, + &spear3xx_pmx_gpio_pin4, + &spear3xx_pmx_gpio_pin5, + &spear3xx_pmx_uart0, + + /* spear310 specific devices */ + &spear310_pmx_emi_cs_0_1_4_5, + &spear310_pmx_emi_cs_2_3, + &spear310_pmx_uart1, + &spear310_pmx_uart2, + &spear310_pmx_uart3_4_5, + &spear310_pmx_fsmc, + &spear310_pmx_rs485_0_1, + &spear310_pmx_tdm0, +}; + /* DMAC platform data's slave info */ struct pl08x_channel_data spear310_dma_info[] = { { @@ -372,7 +578,7 @@ static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { static void __init spear310_dt_init(void) { void __iomem *base; - int ret; + int ret = 0; pl080_plat_data.slave_channels = spear310_dma_info; pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); @@ -407,6 +613,19 @@ static void __init spear310_dt_init(void) if (ret) pr_err("Error registering Shared IRQ 4\n"); } + + if (of_machine_is_compatible("st,spear310-evb")) { + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = NULL; + pmx_driver.devs = spear310_evb_pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(spear310_evb_pmx_devs); + + ret = pmx_register(&pmx_driver); + if (ret) + pr_err("padmux: registration failed. err no: %d\n", + ret); + } } static const char * const spear310_dt_board_compat[] = { diff --git a/trunk/arch/arm/mach-spear3xx/spear320.c b/trunk/arch/arm/mach-spear3xx/spear320.c index fb28c189688e..2f5979b0c169 100644 --- a/trunk/arch/arm/mach-spear3xx/spear320.c +++ b/trunk/arch/arm/mach-spear3xx/spear320.c @@ -21,9 +21,435 @@ #include #include #include -#include #include +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) + +/* Interrupt registers offsets and masks */ +#define SPEAR320_INT_STS_MASK_REG 0x04 +#define SPEAR320_INT_CLR_MASK_REG 0x04 +#define SPEAR320_INT_ENB_MASK_REG 0x08 +#define SPEAR320_GPIO_IRQ_MASK (1 << 0) +#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1) +#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2) +#define SPEAR320_EMI_IRQ_MASK (1 << 7) +#define SPEAR320_CLCD_IRQ_MASK (1 << 8) +#define SPEAR320_SPP_IRQ_MASK (1 << 9) +#define SPEAR320_SDHCI_IRQ_MASK (1 << 10) +#define SPEAR320_CAN_U_IRQ_MASK (1 << 11) +#define SPEAR320_CAN_L_IRQ_MASK (1 << 12) +#define SPEAR320_UART1_IRQ_MASK (1 << 13) +#define SPEAR320_UART2_IRQ_MASK (1 << 14) +#define SPEAR320_SSP1_IRQ_MASK (1 << 15) +#define SPEAR320_SSP2_IRQ_MASK (1 << 16) +#define SPEAR320_SMII0_IRQ_MASK (1 << 17) +#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18) +#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19) +#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20) +#define SPEAR320_I2C1_IRQ_MASK (1 << 21) + +#define SPEAR320_SHIRQ_RAS1_MASK 0x000380 +#define SPEAR320_SHIRQ_RAS3_MASK 0x000007 +#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800 + +/* SPEAr320 Virtual irq definitions */ +/* IRQs sharing IRQ_GEN_RAS_1 */ +#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0) +#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1) +#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2) + +/* IRQs sharing IRQ_GEN_RAS_2 */ +#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2 + +/* IRQs sharing IRQ_GEN_RAS_3 */ +#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3) +#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4) +#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5) + +/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ +#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6) +#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7) +#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8) +#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9) +#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10) +#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11) +#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12) +#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13) +#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14) +#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15) +#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16) + +/* pad multiplexing support */ +/* muxing registers */ +#define PAD_MUX_CONFIG_REG 0x0C +#define MODE_CONFIG_REG 0x10 + +/* modes */ +#define AUTO_NET_SMII_MODE (1 << 0) +#define AUTO_NET_MII_MODE (1 << 1) +#define AUTO_EXP_MODE (1 << 2) +#define SMALL_PRINTERS_MODE (1 << 3) +#define ALL_MODES 0xF + +struct pmx_mode spear320_auto_net_smii_mode = { + .id = AUTO_NET_SMII_MODE, + .name = "Automation Networking SMII Mode", + .mask = 0x00, +}; + +struct pmx_mode spear320_auto_net_mii_mode = { + .id = AUTO_NET_MII_MODE, + .name = "Automation Networking MII Mode", + .mask = 0x01, +}; + +struct pmx_mode spear320_auto_exp_mode = { + .id = AUTO_EXP_MODE, + .name = "Automation Expanded Mode", + .mask = 0x02, +}; + +struct pmx_mode spear320_small_printers_mode = { + .id = SMALL_PRINTERS_MODE, + .name = "Small Printers Mode", + .mask = 0x03, +}; + +/* devices */ +static struct pmx_dev_mode pmx_clcd_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_clcd = { + .name = "clcd", + .modes = pmx_clcd_modes, + .mode_count = ARRAY_SIZE(pmx_clcd_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_emi_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear320_pmx_emi = { + .name = "emi", + .modes = pmx_emi_modes, + .mode_count = ARRAY_SIZE(pmx_emi_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_fsmc_modes[] = { + { + .ids = ALL_MODES, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_fsmc = { + .name = "fsmc", + .modes = pmx_fsmc_modes, + .mode_count = ARRAY_SIZE(pmx_fsmc_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_spp_modes[] = { + { + .ids = SMALL_PRINTERS_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_spp = { + .name = "spp", + .modes = pmx_spp_modes, + .mode_count = ARRAY_SIZE(pmx_spp_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_sdhci_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | + SMALL_PRINTERS_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear320_pmx_sdhci = { + .name = "sdhci", + .modes = pmx_sdhci_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_i2s_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear320_pmx_i2s = { + .name = "i2s", + .modes = pmx_i2s_modes, + .mode_count = ARRAY_SIZE(pmx_i2s_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart1 = { + .name = "uart1", + .modes = pmx_uart1_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart1_modem_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | + PMX_SSP_CS_MASK, + }, { + .ids = SMALL_PRINTERS_MODE, + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart1_modem = { + .name = "uart1_modem", + .modes = pmx_uart1_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_uart2_modes[] = { + { + .ids = ALL_MODES, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear320_pmx_uart2 = { + .name = "uart2", + .modes = pmx_uart2_modes, + .mode_count = ARRAY_SIZE(pmx_uart2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_touchscreen_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_touchscreen = { + .name = "touchscreen", + .modes = pmx_touchscreen_modes, + .mode_count = ARRAY_SIZE(pmx_touchscreen_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_can_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE, + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear320_pmx_can = { + .name = "can", + .modes = pmx_can_modes, + .mode_count = ARRAY_SIZE(pmx_can_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_sdhci_led_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear320_pmx_sdhci_led = { + .name = "sdhci_led", + .modes = pmx_sdhci_led_modes, + .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm0 = { + .name = "pwm0", + .modes = pmx_pwm0_modes, + .mode_count = ARRAY_SIZE(pmx_pwm0_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_UART0_MODEM_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm1 = { + .name = "pwm1", + .modes = pmx_pwm1_modes, + .mode_count = ARRAY_SIZE(pmx_pwm1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE, + .mask = PMX_SSP_CS_MASK, + }, { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm2 = { + .name = "pwm2", + .modes = pmx_pwm2_modes, + .mode_count = ARRAY_SIZE(pmx_pwm2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_pwm3_modes[] = { + { + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_pwm3 = { + .name = "pwm3", + .modes = pmx_pwm3_modes, + .mode_count = ARRAY_SIZE(pmx_pwm3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_ssp1_modes[] = { + { + .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_ssp1 = { + .name = "ssp1", + .modes = pmx_ssp1_modes, + .mode_count = ARRAY_SIZE(pmx_ssp1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_ssp2_modes[] = { + { + .ids = AUTO_NET_SMII_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_ssp2 = { + .name = "ssp2", + .modes = pmx_ssp2_modes, + .mode_count = ARRAY_SIZE(pmx_ssp2_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_mii1_modes[] = { + { + .ids = AUTO_NET_MII_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_mii1 = { + .name = "mii1", + .modes = pmx_mii1_modes, + .mode_count = ARRAY_SIZE(pmx_mii1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_smii0_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_smii0 = { + .name = "smii0", + .modes = pmx_smii0_modes, + .mode_count = ARRAY_SIZE(pmx_smii0_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_smii1_modes[] = { + { + .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear320_pmx_smii1 = { + .name = "smii1", + .modes = pmx_smii1_modes, + .mode_count = ARRAY_SIZE(pmx_smii1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_i2c1_modes[] = { + { + .ids = AUTO_EXP_MODE, + .mask = 0x0, + }, +}; + +struct pmx_dev spear320_pmx_i2c1 = { + .name = "i2c1", + .modes = pmx_i2c1_modes, + .mode_count = ARRAY_SIZE(pmx_i2c1_modes), + .enb_on_reset = 1, +}; + +/* pmx driver structure */ +static struct pmx_driver pmx_driver = { + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007}, + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, +}; + /* spear3xx shared irq */ static struct shirq_dev_config shirq_ras1_config[] = { { @@ -148,6 +574,27 @@ static struct spear_shirq shirq_intrcomm_ras = { }, }; +/* padmux devices to enable */ +static struct pmx_dev *spear320_evb_pmx_devs[] = { + /* spear3xx specific devices */ + &spear3xx_pmx_i2c, + &spear3xx_pmx_ssp, + &spear3xx_pmx_mii, + &spear3xx_pmx_uart0, + + /* spear320 specific devices */ + &spear320_pmx_fsmc, + &spear320_pmx_sdhci, + &spear320_pmx_i2s, + &spear320_pmx_uart1, + &spear320_pmx_uart2, + &spear320_pmx_can, + &spear320_pmx_pwm0, + &spear320_pmx_pwm1, + &spear320_pmx_pwm2, + &spear320_pmx_mii1, +}; + /* DMAC platform data's slave info */ struct pl08x_channel_data spear320_dma_info[] = { { @@ -385,7 +832,7 @@ static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = { static void __init spear320_dt_init(void) { void __iomem *base; - int ret; + int ret = 0; pl080_plat_data.slave_channels = spear320_dma_info; pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info); @@ -414,6 +861,19 @@ static void __init spear320_dt_init(void) if (ret) pr_err("Error registering Shared IRQ 4\n"); } + + if (of_machine_is_compatible("st,spear320-evb")) { + /* pmx initialization */ + pmx_driver.base = base; + pmx_driver.mode = &spear320_auto_net_mii_mode; + pmx_driver.devs = spear320_evb_pmx_devs; + pmx_driver.devs_count = ARRAY_SIZE(spear320_evb_pmx_devs); + + ret = pmx_register(&pmx_driver); + if (ret) + pr_err("padmux: registration failed. err no: %d\n", + ret); + } } static const char * const spear320_dt_board_compat[] = { diff --git a/trunk/arch/arm/mach-spear3xx/spear3xx.c b/trunk/arch/arm/mach-spear3xx/spear3xx.c index 71927c717807..25c6c67d5b07 100644 --- a/trunk/arch/arm/mach-spear3xx/spear3xx.c +++ b/trunk/arch/arm/mach-spear3xx/spear3xx.c @@ -21,7 +21,432 @@ #include #include #include -#include +#include + +/* pad multiplexing support */ +/* devices */ +static struct pmx_dev_mode pmx_firda_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_firda = { + .name = "firda", + .modes = pmx_firda_modes, + .mode_count = ARRAY_SIZE(pmx_firda_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_i2c_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_i2c = { + .name = "i2c", + .modes = pmx_i2c_modes, + .mode_count = ARRAY_SIZE(pmx_i2c_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_ssp_cs_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_ssp_cs = { + .name = "ssp_chip_selects", + .modes = pmx_ssp_cs_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_ssp_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_ssp = { + .name = "ssp", + .modes = pmx_ssp_modes, + .mode_count = ARRAY_SIZE(pmx_ssp_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_mii_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_mii = { + .name = "mii", + .modes = pmx_mii_modes, + .mode_count = ARRAY_SIZE(pmx_mii_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin0 = { + .name = "gpio_pin0", + .modes = pmx_gpio_pin0_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin1 = { + .name = "gpio_pin1", + .modes = pmx_gpio_pin1_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin2 = { + .name = "gpio_pin2", + .modes = pmx_gpio_pin2_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin3 = { + .name = "gpio_pin3", + .modes = pmx_gpio_pin3_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin4 = { + .name = "gpio_pin4", + .modes = pmx_gpio_pin4_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_gpio_pin5 = { + .name = "gpio_pin5", + .modes = pmx_gpio_pin5_modes, + .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_uart0_modem_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_uart0_modem = { + .name = "uart0_modem", + .modes = pmx_uart0_modem_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_uart0_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_uart0 = { + .name = "uart0", + .modes = pmx_uart0_modes, + .mode_count = ARRAY_SIZE(pmx_uart0_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_timer_3_4_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_timer_3_4 = { + .name = "timer_3_4", + .modes = pmx_timer_3_4_modes, + .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), + .enb_on_reset = 0, +}; + +static struct pmx_dev_mode pmx_timer_1_2_modes[] = { + { + .ids = 0xffffffff, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_timer_1_2 = { + .name = "timer_1_2", + .modes = pmx_timer_1_2_modes, + .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), + .enb_on_reset = 0, +}; + +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) +/* plgpios devices */ +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { + { + .ids = 0x00, + .mask = PMX_FIRDA_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_0_1 = { + .name = "plgpio 0 and 1", + .modes = pmx_plgpio_0_1_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_2_3 = { + .name = "plgpio 2 and 3", + .modes = pmx_plgpio_2_3_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { + { + .ids = 0x00, + .mask = PMX_I2C_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_4_5 = { + .name = "plgpio 4 and 5", + .modes = pmx_plgpio_4_5_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_6_9 = { + .name = "plgpio 6 to 9", + .modes = pmx_plgpio_6_9_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { + { + .ids = 0x00, + .mask = PMX_MII_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_10_27 = { + .name = "plgpio 10 to 27", + .modes = pmx_plgpio_10_27_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_28_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN0_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_28 = { + .name = "plgpio 28", + .modes = pmx_plgpio_28_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_29_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN1_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_29 = { + .name = "plgpio 29", + .modes = pmx_plgpio_29_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_30_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_30 = { + .name = "plgpio 30", + .modes = pmx_plgpio_30_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_31_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN3_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_31 = { + .name = "plgpio 31", + .modes = pmx_plgpio_31_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_32_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_32 = { + .name = "plgpio 32", + .modes = pmx_plgpio_32_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_33_modes[] = { + { + .ids = 0x00, + .mask = PMX_GPIO_PIN5_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_33 = { + .name = "plgpio 33", + .modes = pmx_plgpio_33_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { + { + .ids = 0x00, + .mask = PMX_SSP_CS_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_34_36 = { + .name = "plgpio 34 to 36", + .modes = pmx_plgpio_34_36_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { + { + .ids = 0x00, + .mask = PMX_UART0_MODEM_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_37_42 = { + .name = "plgpio 37 to 42", + .modes = pmx_plgpio_37_42_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_1_2_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { + .name = "plgpio 43, 44, 47 and 48", + .modes = pmx_plgpio_43_44_47_48_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), + .enb_on_reset = 1, +}; + +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { + { + .ids = 0x00, + .mask = PMX_TIMER_3_4_MASK, + }, +}; + +struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { + .name = "plgpio 45, 46, 49 and 50", + .modes = pmx_plgpio_45_46_49_50_modes, + .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), + .enb_on_reset = 1, +}; +#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ /* ssp device registration */ struct pl022_ssp_controller pl022_plat_data = { @@ -90,8 +515,6 @@ static void __init spear3xx_timer_init(void) char pclk_name[] = "pll3_48m_clk"; struct clk *gpt_clk, *pclk; - spear3xx_clk_init(); - /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); if (IS_ERR(gpt_clk)) { @@ -111,7 +534,7 @@ static void __init spear3xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear3xx_timer = { diff --git a/trunk/arch/arm/mach-spear6xx/Makefile b/trunk/arch/arm/mach-spear6xx/Makefile index 898831d93f37..76e5750552fc 100644 --- a/trunk/arch/arm/mach-spear6xx/Makefile +++ b/trunk/arch/arm/mach-spear6xx/Makefile @@ -3,4 +3,4 @@ # # common files -obj-y += spear6xx.o +obj-y += clock.o spear6xx.o diff --git a/trunk/arch/arm/mach-spear6xx/clock.c b/trunk/arch/arm/mach-spear6xx/clock.c new file mode 100644 index 000000000000..bef77d43db87 --- /dev/null +++ b/trunk/arch/arm/mach-spear6xx/clock.c @@ -0,0 +1,789 @@ +/* + * arch/arm/mach-spear6xx/clock.c + * + * SPEAr6xx machines clock framework source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include + +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) +/* PLL_CTR register masks */ +#define PLL_ENABLE 2 +#define PLL_MODE_SHIFT 4 +#define PLL_MODE_MASK 0x3 +#define PLL_MODE_NORMAL 0 +#define PLL_MODE_FRACTION 1 +#define PLL_MODE_DITH_DSB 2 +#define PLL_MODE_DITH_SSB 3 + +#define PLL2_FRQ (MISC_BASE + 0x018) +/* PLL FRQ register masks */ +#define PLL_DIV_N_SHIFT 0 +#define PLL_DIV_N_MASK 0xFF +#define PLL_DIV_P_SHIFT 8 +#define PLL_DIV_P_MASK 0x7 +#define PLL_NORM_FDBK_M_SHIFT 24 +#define PLL_NORM_FDBK_M_MASK 0xFF +#define PLL_DITH_FDBK_M_SHIFT 16 +#define PLL_DITH_FDBK_M_MASK 0xFFFF + +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) +/* CORE CLK CFG register masks */ +#define PLL_HCLK_RATIO_SHIFT 10 +#define PLL_HCLK_RATIO_MASK 0x3 +#define HCLK_PCLK_RATIO_SHIFT 8 +#define HCLK_PCLK_RATIO_MASK 0x3 + +#define PERIP_CLK_CFG (MISC_BASE + 0x028) +/* PERIP_CLK_CFG register masks */ +#define CLCD_CLK_SHIFT 2 +#define CLCD_CLK_MASK 0x3 +#define UART_CLK_SHIFT 4 +#define UART_CLK_MASK 0x1 +#define FIRDA_CLK_SHIFT 5 +#define FIRDA_CLK_MASK 0x3 +#define GPT0_CLK_SHIFT 8 +#define GPT1_CLK_SHIFT 10 +#define GPT2_CLK_SHIFT 11 +#define GPT3_CLK_SHIFT 12 +#define GPT_CLK_MASK 0x1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 + +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) +/* PERIP1_CLK_ENB register masks */ +#define UART0_CLK_ENB 3 +#define UART1_CLK_ENB 4 +#define SSP0_CLK_ENB 5 +#define SSP1_CLK_ENB 6 +#define I2C_CLK_ENB 7 +#define JPEG_CLK_ENB 8 +#define FSMC_CLK_ENB 9 +#define FIRDA_CLK_ENB 10 +#define GPT2_CLK_ENB 11 +#define GPT3_CLK_ENB 12 +#define GPIO2_CLK_ENB 13 +#define SSP2_CLK_ENB 14 +#define ADC_CLK_ENB 15 +#define GPT1_CLK_ENB 11 +#define RTC_CLK_ENB 17 +#define GPIO1_CLK_ENB 18 +#define DMA_CLK_ENB 19 +#define SMI_CLK_ENB 21 +#define CLCD_CLK_ENB 22 +#define GMAC_CLK_ENB 23 +#define USBD_CLK_ENB 24 +#define USBH0_CLK_ENB 25 +#define USBH1_CLK_ENB 26 + +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) +/* gpt synthesizer register masks */ +#define GPT_MSCALE_SHIFT 0 +#define GPT_MSCALE_MASK 0xFFF +#define GPT_NSCALE_SHIFT 12 +#define GPT_NSCALE_MASK 0xF + +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) +/* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 +#define AUX_EQ_SEL_SHIFT 30 +#define AUX_EQ_SEL_MASK 1 +#define AUX_EQ1_SEL 0 +#define AUX_EQ2_SEL 1 +#define AUX_XSCALE_SHIFT 16 +#define AUX_XSCALE_MASK 0xFFF +#define AUX_YSCALE_SHIFT 0 +#define AUX_YSCALE_MASK 0xFFF + +/* root clks */ +/* 32 KHz oscillator clock */ +static struct clk osc_32k_clk = { + .flags = ALWAYS_ENABLED, + .rate = 32000, +}; + +/* 30 MHz oscillator clock */ +static struct clk osc_30m_clk = { + .flags = ALWAYS_ENABLED, + .rate = 30000000, +}; + +/* clock derived from 32 KHz osc clk */ +/* rtc clock */ +static struct clk rtc_clk = { + .pclk = &osc_32k_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = RTC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from 30 MHz osc clk */ +/* pll masks structure */ +static struct pll_clk_masks pll1_masks = { + .mode_mask = PLL_MODE_MASK, + .mode_shift = PLL_MODE_SHIFT, + .norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK, + .norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT, + .dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK, + .dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT, + .div_p_mask = PLL_DIV_P_MASK, + .div_p_shift = PLL_DIV_P_SHIFT, + .div_n_mask = PLL_DIV_N_MASK, + .div_n_shift = PLL_DIV_N_SHIFT, +}; + +/* pll1 configuration structure */ +static struct pll_clk_config pll1_config = { + .mode_reg = PLL1_CTR, + .cfg_reg = PLL1_FRQ, + .masks = &pll1_masks, +}; + +/* pll rate configuration table, in ascending order of rates */ +struct pll_rate_tbl pll_rtbl[] = { + {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */ + {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */ +}; + +/* PLL1 clock */ +static struct clk pll1_clk = { + .flags = ENABLED_ON_INIT, + .pclk = &osc_30m_clk, + .en_reg = PLL1_CTR, + .en_reg_bit = PLL_ENABLE, + .calc_rate = &pll_calc_rate, + .recalc = &pll_clk_recalc, + .set_rate = &pll_clk_set_rate, + .rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1}, + .private_data = &pll1_config, +}; + +/* PLL3 48 MHz clock */ +static struct clk pll3_48m_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .rate = 48000000, +}; + +/* watch dog timer clock */ +static struct clk wdt_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &osc_30m_clk, + .recalc = &follow_parent, +}; + +/* clock derived from pll1 clk */ +/* cpu clock */ +static struct clk cpu_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .recalc = &follow_parent, +}; + +/* ahb masks structure */ +static struct bus_clk_masks ahb_masks = { + .mask = PLL_HCLK_RATIO_MASK, + .shift = PLL_HCLK_RATIO_SHIFT, +}; + +/* ahb configuration structure */ +static struct bus_clk_config ahb_config = { + .reg = CORE_CLK_CFG, + .masks = &ahb_masks, +}; + +/* ahb rate configuration table, in ascending order of rates */ +struct bus_rate_tbl bus_rtbl[] = { + {.div = 3}, /* == parent divided by 4 */ + {.div = 2}, /* == parent divided by 3 */ + {.div = 1}, /* == parent divided by 2 */ + {.div = 0}, /* == parent divided by 1 */ +}; + +/* ahb clock */ +static struct clk ahb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &bus_calc_rate, + .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, + .private_data = &ahb_config, +}; + +/* auxiliary synthesizers masks */ +static struct aux_clk_masks aux_masks = { + .eq_sel_mask = AUX_EQ_SEL_MASK, + .eq_sel_shift = AUX_EQ_SEL_SHIFT, + .eq1_mask = AUX_EQ1_SEL, + .eq2_mask = AUX_EQ2_SEL, + .xscale_sel_mask = AUX_XSCALE_MASK, + .xscale_sel_shift = AUX_XSCALE_SHIFT, + .yscale_sel_mask = AUX_YSCALE_MASK, + .yscale_sel_shift = AUX_YSCALE_SHIFT, +}; + +/* uart configurations */ +static struct aux_clk_config uart_synth_config = { + .synth_reg = UART_CLK_SYNT, + .masks = &aux_masks, +}; + +/* aux rate configuration table, in ascending order of rates */ +struct aux_rate_tbl aux_rtbl[] = { + /* For PLL1 = 332 MHz */ + {.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */ + {.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */ + {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ +}; + +/* uart synth clock */ +static struct clk uart_synth_clk = { + .en_reg = UART_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &uart_synth_config, +}; + +/* uart parents */ +static struct pclk_info uart_pclk_info[] = { + { + .pclk = &uart_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* uart parent select structure */ +static struct pclk_sel uart_pclk_sel = { + .pclk_info = uart_pclk_info, + .pclk_count = ARRAY_SIZE(uart_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = UART_CLK_MASK, +}; + +/* uart0 clock */ +static struct clk uart0_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART0_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* uart1 clock */ +static struct clk uart1_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = UART1_CLK_ENB, + .pclk_sel = &uart_pclk_sel, + .pclk_sel_shift = UART_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* firda configurations */ +static struct aux_clk_config firda_synth_config = { + .synth_reg = FIRDA_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk firda_synth_clk = { + .en_reg = FIRDA_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &firda_synth_config, +}; + +/* firda parents */ +static struct pclk_info firda_pclk_info[] = { + { + .pclk = &firda_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* firda parent select structure */ +static struct pclk_sel firda_pclk_sel = { + .pclk_info = firda_pclk_info, + .pclk_count = ARRAY_SIZE(firda_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = FIRDA_CLK_MASK, +}; + +/* firda clock */ +static struct clk firda_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FIRDA_CLK_ENB, + .pclk_sel = &firda_pclk_sel, + .pclk_sel_shift = FIRDA_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* clcd configurations */ +static struct aux_clk_config clcd_synth_config = { + .synth_reg = CLCD_CLK_SYNT, + .masks = &aux_masks, +}; + +/* firda synth clock */ +static struct clk clcd_synth_clk = { + .en_reg = CLCD_CLK_SYNT, + .en_reg_bit = AUX_SYNT_ENB, + .pclk = &pll1_clk, + .calc_rate = &aux_calc_rate, + .recalc = &aux_clk_recalc, + .set_rate = &aux_clk_set_rate, + .rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2}, + .private_data = &clcd_synth_config, +}; + +/* clcd parents */ +static struct pclk_info clcd_pclk_info[] = { + { + .pclk = &clcd_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* clcd parent select structure */ +static struct pclk_sel clcd_pclk_sel = { + .pclk_info = clcd_pclk_info, + .pclk_count = ARRAY_SIZE(clcd_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = CLCD_CLK_MASK, +}; + +/* clcd clock */ +static struct clk clcd_clk = { + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = CLCD_CLK_ENB, + .pclk_sel = &clcd_pclk_sel, + .pclk_sel_shift = CLCD_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt synthesizer masks */ +static struct gpt_clk_masks gpt_masks = { + .mscale_sel_mask = GPT_MSCALE_MASK, + .mscale_sel_shift = GPT_MSCALE_SHIFT, + .nscale_sel_mask = GPT_NSCALE_MASK, + .nscale_sel_shift = GPT_NSCALE_SHIFT, +}; + +/* gpt rate configuration table, in ascending order of rates */ +struct gpt_rate_tbl gpt_rtbl[] = { + /* For pll1 = 332 MHz */ + {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ + {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ + {.mscale = 1, .nscale = 0}, /* 83 MHz */ +}; + +/* gpt0 synth clk config*/ +static struct gpt_clk_config gpt0_synth_config = { + .synth_reg = PRSC1_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt0_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt0_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt0_pclk_info[] = { + { + .pclk = &gpt0_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt0_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt0 ARM1 subsystem timer clock */ +static struct clk gpt0_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt0_pclk_sel, + .pclk_sel_shift = GPT0_CLK_SHIFT, + .recalc = &follow_parent, +}; + + +/* Note: gpt0 and gpt1 share same parent clocks */ +/* gpt parent select structure */ +static struct pclk_sel gpt1_pclk_sel = { + .pclk_info = gpt0_pclk_info, + .pclk_count = ARRAY_SIZE(gpt0_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt1 timer clock */ +static struct clk gpt1_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt1_pclk_sel, + .pclk_sel_shift = GPT1_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt2 synth clk config*/ +static struct gpt_clk_config gpt2_synth_config = { + .synth_reg = PRSC2_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt2_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt2_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt2_pclk_info[] = { + { + .pclk = &gpt2_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt2_pclk_sel = { + .pclk_info = gpt2_pclk_info, + .pclk_count = ARRAY_SIZE(gpt2_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt2 timer clock */ +static struct clk gpt2_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt2_pclk_sel, + .pclk_sel_shift = GPT2_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* gpt3 synth clk config*/ +static struct gpt_clk_config gpt3_synth_config = { + .synth_reg = PRSC3_CLK_CFG, + .masks = &gpt_masks, +}; + +/* gpt synth clock */ +static struct clk gpt3_synth_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &pll1_clk, + .calc_rate = &gpt_calc_rate, + .recalc = &gpt_clk_recalc, + .set_rate = &gpt_clk_set_rate, + .rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2}, + .private_data = &gpt3_synth_config, +}; + +/* gpt parents */ +static struct pclk_info gpt3_pclk_info[] = { + { + .pclk = &gpt3_synth_clk, + .pclk_val = AUX_CLK_PLL1_VAL, + }, { + .pclk = &pll3_48m_clk, + .pclk_val = AUX_CLK_PLL3_VAL, + }, +}; + +/* gpt parent select structure */ +static struct pclk_sel gpt3_pclk_sel = { + .pclk_info = gpt3_pclk_info, + .pclk_count = ARRAY_SIZE(gpt3_pclk_info), + .pclk_sel_reg = PERIP_CLK_CFG, + .pclk_sel_mask = GPT_CLK_MASK, +}; + +/* gpt3 timer clock */ +static struct clk gpt3_clk = { + .flags = ALWAYS_ENABLED, + .pclk_sel = &gpt3_pclk_sel, + .pclk_sel_shift = GPT3_CLK_SHIFT, + .recalc = &follow_parent, +}; + +/* clock derived from pll3 clk */ +/* usbh0 clock */ +static struct clk usbh0_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH0_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbh1 clock */ +static struct clk usbh1_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBH1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* usbd clock */ +static struct clk usbd_clk = { + .pclk = &pll3_48m_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = USBD_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from ahb clk */ +/* apb masks structure */ +static struct bus_clk_masks apb_masks = { + .mask = HCLK_PCLK_RATIO_MASK, + .shift = HCLK_PCLK_RATIO_SHIFT, +}; + +/* apb configuration structure */ +static struct bus_clk_config apb_config = { + .reg = CORE_CLK_CFG, + .masks = &apb_masks, +}; + +/* apb clock */ +static struct clk apb_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &ahb_clk, + .calc_rate = &bus_calc_rate, + .recalc = &bus_clk_recalc, + .set_rate = &bus_clk_set_rate, + .rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2}, + .private_data = &apb_config, +}; + +/* i2c clock */ +static struct clk i2c_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = I2C_CLK_ENB, + .recalc = &follow_parent, +}; + +/* dma clock */ +static struct clk dma_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = DMA_CLK_ENB, + .recalc = &follow_parent, +}; + +/* jpeg clock */ +static struct clk jpeg_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = JPEG_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gmac clock */ +static struct clk gmac_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GMAC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* smi clock */ +static struct clk smi_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SMI_CLK_ENB, + .recalc = &follow_parent, +}; + +/* fsmc clock */ +static struct clk fsmc_clk = { + .pclk = &ahb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = FSMC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* clock derived from apb clk */ +/* adc clock */ +static struct clk adc_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = ADC_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp0 clock */ +static struct clk ssp0_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP0_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp1 clock */ +static struct clk ssp1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* ssp2 clock */ +static struct clk ssp2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = SSP2_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio0 ARM subsystem clock */ +static struct clk gpio0_clk = { + .flags = ALWAYS_ENABLED, + .pclk = &apb_clk, + .recalc = &follow_parent, +}; + +/* gpio1 clock */ +static struct clk gpio1_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO1_CLK_ENB, + .recalc = &follow_parent, +}; + +/* gpio2 clock */ +static struct clk gpio2_clk = { + .pclk = &apb_clk, + .en_reg = PERIP1_CLK_ENB, + .en_reg_bit = GPIO2_CLK_ENB, + .recalc = &follow_parent, +}; + +static struct clk dummy_apb_pclk; + +/* array of all spear 6xx clock lookups */ +static struct clk_lookup spear_clk_lookups[] = { + CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk), + /* root clks */ + CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk), + CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk), + /* clock derived from 32 KHz os clk */ + CLKDEV_INIT("rtc-spear", NULL, &rtc_clk), + /* clock derived from 30 MHz os clk */ + CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk), + CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk), + CLKDEV_INIT("wdt", NULL, &wdt_clk), + /* clock derived from pll1 clk */ + CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk), + CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk), + CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk), + CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk), + CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk), + CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk), + CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk), + CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk), + CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk), + CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk), + CLKDEV_INIT("firda", NULL, &firda_clk), + CLKDEV_INIT("clcd", NULL, &clcd_clk), + CLKDEV_INIT("gpt0", NULL, &gpt0_clk), + CLKDEV_INIT("gpt1", NULL, &gpt1_clk), + CLKDEV_INIT("gpt2", NULL, &gpt2_clk), + CLKDEV_INIT("gpt3", NULL, &gpt3_clk), + /* clock derived from pll3 clk */ + CLKDEV_INIT("designware_udc", NULL, &usbd_clk), + CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk), + CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk), + /* clock derived from ahb clk */ + CLKDEV_INIT(NULL, "apb_clk", &apb_clk), + CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk), + CLKDEV_INIT("fc400000.dma", NULL, &dma_clk), + CLKDEV_INIT("jpeg", NULL, &jpeg_clk), + CLKDEV_INIT("gmac", NULL, &gmac_clk), + CLKDEV_INIT("fc000000.flash", NULL, &smi_clk), + CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk), + /* clock derived from apb clk */ + CLKDEV_INIT("adc", NULL, &adc_clk), + CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk), + CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk), + CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk), + CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk), + CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk), + CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk), +}; + +void __init spear6xx_clk_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++) + clk_register(&spear_clk_lookups[i]); + + clk_init(); +} diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/generic.h b/trunk/arch/arm/mach-spear6xx/include/mach/generic.h index 116b99301cf5..65514b159370 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/generic.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/generic.h @@ -15,34 +15,9 @@ #define __MACH_GENERIC_H #include -#include -#include -#include -#include - -/* - * Each GPT has 2 timer channels - * Following GPT channels will be used as clock source and clockevent - */ -#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE -#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 -#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 - -/* Add spear6xx family device structure declarations here */ -extern struct amba_device gpio_device[]; -extern struct amba_device uart_device[]; -extern struct sys_timer spear6xx_timer; - -/* Add spear6xx family function declarations here */ -void __init spear_setup_timer(void); -void __init spear6xx_map_io(void); -void __init spear6xx_init_irq(void); -void __init spear6xx_init(void); -void __init spear600_init(void); -void __init spear6xx_clk_init(void); +void __init spear_setup_of_timer(void); void spear_restart(char, const char *); - -/* Add spear600 machine device structure declarations here */ +void __init spear6xx_clk_init(void); #endif /* __MACH_GENERIC_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h b/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h index 0b3f96ae2848..40a8c178f10d 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/hardware.h @@ -1,23 +1 @@ -/* - * arch/arm/mach-spear6xx/include/mach/hardware.h - * - * Hardware definitions for SPEAr6xx machine family - * - * Copyright (C) 2009 ST Microelectronics - * Rajeev Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include -#include - -/* Vitual to physical translation of statically mapped space */ -#define IO_ADDRESS(x) (x | 0xF0000000) - -#endif /* __MACH_HARDWARE_H */ +/* empty */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h b/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h index 8f214b03d75d..37a5c411a866 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/irqs.h @@ -16,82 +16,10 @@ /* IRQ definitions */ /* VIC 1 */ -#define IRQ_INTRCOMM_SW_IRQ 0 -#define IRQ_INTRCOMM_CPU_1 1 -#define IRQ_INTRCOMM_CPU_2 2 -#define IRQ_INTRCOMM_RAS2A11_1 3 -#define IRQ_INTRCOMM_RAS2A11_2 4 -#define IRQ_INTRCOMM_RAS2A12_1 5 -#define IRQ_INTRCOMM_RAS2A12_2 6 -#define IRQ_GEN_RAS_0 7 -#define IRQ_GEN_RAS_1 8 -#define IRQ_GEN_RAS_2 9 -#define IRQ_GEN_RAS_3 10 -#define IRQ_GEN_RAS_4 11 -#define IRQ_GEN_RAS_5 12 -#define IRQ_GEN_RAS_6 13 -#define IRQ_GEN_RAS_7 14 -#define IRQ_GEN_RAS_8 15 -#define IRQ_CPU_GPT1_1 16 -#define IRQ_CPU_GPT1_2 17 -#define IRQ_LOCAL_GPIO 18 -#define IRQ_PLL_UNLOCK 19 -#define IRQ_JPEG 20 -#define IRQ_FSMC 21 -#define IRQ_IRDA 22 -#define IRQ_RESERVED 23 -#define IRQ_UART_0 24 -#define IRQ_UART_1 25 -#define IRQ_SSP_1 26 -#define IRQ_SSP_2 27 -#define IRQ_I2C 28 -#define IRQ_GEN_RAS_9 29 -#define IRQ_GEN_RAS_10 30 -#define IRQ_GEN_RAS_11 31 - -/* VIC 2 */ -#define IRQ_APPL_GPT1_1 32 -#define IRQ_APPL_GPT1_2 33 -#define IRQ_APPL_GPT2_1 34 -#define IRQ_APPL_GPT2_2 35 -#define IRQ_APPL_GPIO 36 -#define IRQ_APPL_SSP 37 -#define IRQ_APPL_ADC 38 -#define IRQ_APPL_RESERVED 39 -#define IRQ_AHB_EXP_MASTER 40 -#define IRQ_DDR_CONTROLLER 41 -#define IRQ_BASIC_DMA 42 -#define IRQ_BASIC_RESERVED1 43 -#define IRQ_BASIC_SMI 44 -#define IRQ_BASIC_CLCD 45 -#define IRQ_EXP_AHB_1 46 -#define IRQ_EXP_AHB_2 47 -#define IRQ_BASIC_GPT1_1 48 -#define IRQ_BASIC_GPT1_2 49 -#define IRQ_BASIC_RTC 50 -#define IRQ_BASIC_GPIO 51 -#define IRQ_BASIC_WDT 52 -#define IRQ_BASIC_RESERVED 53 -#define IRQ_AHB_EXP_SLAVE 54 -#define IRQ_GMAC_1 55 -#define IRQ_GMAC_2 56 -#define IRQ_USB_DEV 57 -#define IRQ_USB_H_OHCI_0 58 -#define IRQ_USB_H_EHCI_0 59 -#define IRQ_USB_H_OHCI_1 60 -#define IRQ_USB_H_EHCI_1 61 -#define IRQ_EXP_AHB_3 62 -#define IRQ_EXP_AHB_4 63 - #define IRQ_VIC_END 64 /* GPIO pins virtual irqs */ -#define SPEAR_GPIO_INT_BASE IRQ_VIC_END -#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE -#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) -#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) -#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) -#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) -#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) +#define VIRTUAL_IRQS 24 +#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) #endif /* __MACH_IRQS_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h index 633074fddf9a..2b9aaa6cdd11 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h @@ -14,9 +14,7 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include -#include - #define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) #endif /* __MACH_MISC_REGS_H */ diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/spear.h b/trunk/arch/arm/mach-spear6xx/include/mach/spear.h index 7fd621532def..cb8ed2f4dc85 100644 --- a/trunk/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/trunk/arch/arm/mach-spear6xx/include/mach/spear.h @@ -15,69 +15,25 @@ #define __MACH_SPEAR6XX_H #include -#include -#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000) /* ICM1 - Low speed connection */ #define SPEAR6XX_ICM1_BASE UL(0xD0000000) - +#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000) #define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) -#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) - -#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000) -#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000) -#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000) -#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000) -#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000) -#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000) -#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000) -#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000) -#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000) - -/* ICM2 - Application Subsystem */ -#define SPEAR6XX_ICM2_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000) -#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000) -#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000) -#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000) -#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000) +#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE) /* ML-1, 2 - Multi Layer CPU Subsystem */ #define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) -#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000) -#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000) -#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) -#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000) -#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) +#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000) /* ICM3 - Basic Subsystem */ -#define SPEAR6XX_ICM3_BASE UL(0xF8000000) -#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000) #define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) -#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) +#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) #define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) -#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) -#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000) -#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000) -#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000) -#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000) #define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) -#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) +#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE) #define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) -#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) - -/* ICM4 - High Speed Connection */ -#define SPEAR6XX_ICM4_BASE UL(0xE0000000) -#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000) -#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) -#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000) -#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) -#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000) -#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) -#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000) -#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) -#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000) +#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE diff --git a/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h b/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h deleted file mode 100644 index c068cc50b0fb..000000000000 --- a/trunk/arch/arm/mach-spear6xx/include/mach/spear600.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/arm/mach-spear66xx/include/mach/spear600.h - * - * SPEAr600 Machine specific definition - * - * Copyright (C) 2009 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifdef CONFIG_MACH_SPEAR600 - -#ifndef __MACH_SPEAR600_H -#define __MACH_SPEAR600_H - -#endif /* __MACH_SPEAR600_H */ - -#endif /* CONFIG_MACH_SPEAR600 */ diff --git a/trunk/arch/arm/mach-spear6xx/spear6xx.c b/trunk/arch/arm/mach-spear6xx/spear6xx.c index e9031ec6d6e0..7ae4d5be6cb5 100644 --- a/trunk/arch/arm/mach-spear6xx/spear6xx.c +++ b/trunk/arch/arm/mach-spear6xx/spear6xx.c @@ -14,6 +14,8 @@ */ #include +#include +#include #include #include #include @@ -21,9 +23,11 @@ #include #include #include +#include +#include #include #include -#include +#include /* dmac device registration */ static struct pl08x_channel_data spear600_dma_info[] = { @@ -384,32 +388,29 @@ struct pl08x_platform_data pl080_plat_data = { .num_slave_channels = ARRAY_SIZE(spear600_dma_info), }; -/* Following will create static virtual/physical mappings */ -static struct map_desc spear6xx_io_desc[] __initdata = { +/* + * Following will create 16MB static virtual/physical mappings + * PHYSICAL VIRTUAL + * 0xF0000000 0xF0000000 + * 0xF1000000 0xF1000000 + * 0xD0000000 0xFD000000 + * 0xFC000000 0xFC000000 + */ +struct map_desc spear6xx_io_desc[] __initdata = { { - .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR6XX_ML_CPU_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE), + .length = 2 * SZ_16M, .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), - .length = SZ_4K, + }, { + .virtual = VA_SPEAR6XX_ICM1_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE), + .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE), - .length = SZ_4K, - .type = MT_DEVICE - }, { - .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, - .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), - .length = SZ_4K, + .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE, + .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE), + .length = SZ_16M, .type = MT_DEVICE }, }; @@ -418,6 +419,9 @@ static struct map_desc spear6xx_io_desc[] __initdata = { void __init spear6xx_map_io(void) { iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc)); + + /* This will initialize clock framework */ + spear6xx_clk_init(); } static void __init spear6xx_timer_init(void) @@ -425,8 +429,6 @@ static void __init spear6xx_timer_init(void) char pclk_name[] = "pll3_48m_clk"; struct clk *gpt_clk, *pclk; - spear6xx_clk_init(); - /* get the system timer clock */ gpt_clk = clk_get_sys("gpt0", NULL); if (IS_ERR(gpt_clk)) { @@ -446,7 +448,7 @@ static void __init spear6xx_timer_init(void) clk_put(gpt_clk); clk_put(pclk); - spear_setup_timer(); + spear_setup_of_timer(); } struct sys_timer spear6xx_timer = { diff --git a/trunk/arch/arm/mach-ux500/Kconfig b/trunk/arch/arm/mach-ux500/Kconfig index ef7099eea0f2..880d02ec89d4 100644 --- a/trunk/arch/arm/mach-ux500/Kconfig +++ b/trunk/arch/arm/mach-ux500/Kconfig @@ -17,7 +17,6 @@ config UX500_SOC_DB5500 config UX500_SOC_DB8500 bool select MFD_DB8500_PRCMU - select REGULATOR select REGULATOR_DB8500_PRCMU select CPU_FREQ_TABLE if CPU_FREQ diff --git a/trunk/arch/arm/mach-ux500/platsmp.c b/trunk/arch/arm/mach-ux500/platsmp.c index eff5842f6232..d2058ef8345f 100644 --- a/trunk/arch/arm/mach-ux500/platsmp.c +++ b/trunk/arch/arm/mach-ux500/platsmp.c @@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) */ write_pen_release(cpu_logical_map(cpu)); - smp_send_reschedule(cpu); + gic_raise_softirq(cpumask_of(cpu), 1); timeout = jiffies + (1 * HZ); while (time_before(jiffies, timeout)) { diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index 3f26db4ee8e6..8070145ccb98 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -305,7 +305,6 @@ struct omap_hwmod_sysc_fields { * @rev_offs: IP block revision register offset (from module base addr) * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr) * @syss_offs: OCP_SYSSTATUS register offset (from module base addr) - * @srst_udelay: Delay needed after doing a softreset in usecs * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART} * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported * @clockact: the default value of the module CLOCKACTIVITY bits @@ -331,10 +330,9 @@ struct omap_hwmod_class_sysconfig { u16 sysc_offs; u16 syss_offs; u16 sysc_flags; - struct omap_hwmod_sysc_fields *sysc_fields; - u8 srst_udelay; u8 idlemodes; u8 clockact; + struct omap_hwmod_sysc_fields *sysc_fields; }; /** diff --git a/trunk/arch/arm/plat-omap/sram.c b/trunk/arch/arm/plat-omap/sram.c index f9a8c5341ee9..eec98afa0f83 100644 --- a/trunk/arch/arm/plat-omap/sram.c +++ b/trunk/arch/arm/plat-omap/sram.c @@ -348,6 +348,7 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, sdrc_actim_ctrl_b_1, sdrc_mr_1); } +#ifdef CONFIG_PM void omap3_sram_restore_context(void) { omap_sram_ceil = omap_sram_base + omap_sram_size; @@ -357,18 +358,17 @@ void omap3_sram_restore_context(void) omap3_sram_configure_core_dpll_sz); omap_push_sram_idle(); } +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_OMAP3 */ static inline int omap34xx_sram_init(void) { +#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) omap3_sram_restore_context(); +#endif return 0; } -#else -static inline int omap34xx_sram_init(void) -{ - return 0; -} -#endif /* CONFIG_ARCH_OMAP3 */ static inline int am33xx_sram_init(void) { diff --git a/trunk/arch/arm/plat-spear/Kconfig b/trunk/arch/arm/plat-spear/Kconfig index 387655b5ce05..6c066fcb2979 100644 --- a/trunk/arch/arm/plat-spear/Kconfig +++ b/trunk/arch/arm/plat-spear/Kconfig @@ -13,7 +13,6 @@ config ARCH_SPEAR3XX select ARM_VIC select CPU_ARM926T select USE_OF - select PINCTRL help Supports for ARM's SPEAR3XX family diff --git a/trunk/arch/arm/plat-spear/Makefile b/trunk/arch/arm/plat-spear/Makefile index 38f1235f4632..4af6258d0fee 100644 --- a/trunk/arch/arm/plat-spear/Makefile +++ b/trunk/arch/arm/plat-spear/Makefile @@ -3,6 +3,6 @@ # # Common support -obj-y := restart.o time.o pl080.o +obj-y := clock.o restart.o time.o pl080.o -obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o +obj-$(CONFIG_ARCH_SPEAR3XX) += shirq.o padmux.o diff --git a/trunk/arch/arm/plat-spear/clock.c b/trunk/arch/arm/plat-spear/clock.c new file mode 100644 index 000000000000..67dd00381ea6 --- /dev/null +++ b/trunk/arch/arm/plat-spear/clock.c @@ -0,0 +1,1005 @@ +/* + * arch/arm/plat-spear/clock.c + * + * Clock framework for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clocks_lock); +static LIST_HEAD(root_clks); +#ifdef CONFIG_DEBUG_FS +static LIST_HEAD(clocks); +#endif + +static void propagate_rate(struct clk *, int on_init); +#ifdef CONFIG_DEBUG_FS +static int clk_debugfs_reparent(struct clk *); +#endif + +static int generic_clk_enable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return -EFAULT; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val &= ~(1 << clk->en_reg_bit); + else + val |= 1 << clk->en_reg_bit; + + writel(val, clk->en_reg); + + return 0; +} + +static void generic_clk_disable(struct clk *clk) +{ + unsigned int val; + + if (!clk->en_reg) + return; + + val = readl(clk->en_reg); + if (unlikely(clk->flags & RESET_TO_ENABLE)) + val |= 1 << clk->en_reg_bit; + else + val &= ~(1 << clk->en_reg_bit); + + writel(val, clk->en_reg); +} + +/* generic clk ops */ +static struct clkops generic_clkops = { + .enable = generic_clk_enable, + .disable = generic_clk_disable, +}; + +/* returns current programmed clocks clock info structure */ +static struct pclk_info *pclk_info_get(struct clk *clk) +{ + unsigned int val, i; + struct pclk_info *info = NULL; + + val = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift) + & clk->pclk_sel->pclk_sel_mask; + + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk_val == val) + info = &clk->pclk_sel->pclk_info[i]; + } + + return info; +} + +/* + * Set Update pclk, and pclk_info of clk and add clock sibling node to current + * parents children list + */ +static void clk_reparent(struct clk *clk, struct pclk_info *pclk_info) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + list_del(&clk->sibling); + list_add(&clk->sibling, &pclk_info->pclk->children); + + clk->pclk = pclk_info->pclk; + spin_unlock_irqrestore(&clocks_lock, flags); + +#ifdef CONFIG_DEBUG_FS + clk_debugfs_reparent(clk); +#endif +} + +static void do_clk_disable(struct clk *clk) +{ + if (!clk) + return; + + if (!clk->usage_count) { + WARN_ON(1); + return; + } + + clk->usage_count--; + + if (clk->usage_count == 0) { + /* + * Surely, there are no active childrens or direct users + * of this clock + */ + if (clk->pclk) + do_clk_disable(clk->pclk); + + if (clk->ops && clk->ops->disable) + clk->ops->disable(clk); + } +} + +static int do_clk_enable(struct clk *clk) +{ + int ret = 0; + + if (!clk) + return -EFAULT; + + if (clk->usage_count == 0) { + if (clk->pclk) { + ret = do_clk_enable(clk->pclk); + if (ret) + goto err; + } + if (clk->ops && clk->ops->enable) { + ret = clk->ops->enable(clk); + if (ret) { + if (clk->pclk) + do_clk_disable(clk->pclk); + goto err; + } + } + /* + * Since the clock is going to be used for the first + * time please reclac + */ + if (clk->recalc) { + ret = clk->recalc(clk); + if (ret) + goto err; + } + } + clk->usage_count++; +err: + return ret; +} + +/* + * clk_enable - inform the system when the clock source should be running. + * @clk: clock source + * + * If the clock can not be enabled/disabled, this should return success. + * + * Returns success (0) or negative errno. + */ +int clk_enable(struct clk *clk) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&clocks_lock, flags); + ret = do_clk_enable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); + return ret; +} +EXPORT_SYMBOL(clk_enable); + +/* + * clk_disable - inform the system when the clock source is no longer required. + * @clk: clock source + * + * Inform the system that a clock source is no longer required by + * a driver and may be shut down. + * + * Implementation detail: if the clock source is shared between + * multiple drivers, clk_enable() calls must be balanced by the + * same number of clk_disable() calls for the clock source to be + * disabled. + */ +void clk_disable(struct clk *clk) +{ + unsigned long flags; + + spin_lock_irqsave(&clocks_lock, flags); + do_clk_disable(clk); + spin_unlock_irqrestore(&clocks_lock, flags); +} +EXPORT_SYMBOL(clk_disable); + +/** + * clk_get_rate - obtain the current clock rate (in Hz) for a clock source. + * This is only valid once the clock source has been enabled. + * @clk: clock source + */ +unsigned long clk_get_rate(struct clk *clk) +{ + unsigned long flags, rate; + + spin_lock_irqsave(&clocks_lock, flags); + rate = clk->rate; + spin_unlock_irqrestore(&clocks_lock, flags); + + return rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/** + * clk_set_parent - set the parent clock source for this clock + * @clk: clock source + * @parent: parent clock source + * + * Returns success (0) or negative errno. + */ +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + int i, found = 0, val = 0; + unsigned long flags; + + if (!clk || !parent) + return -EFAULT; + if (clk->pclk == parent) + return 0; + if (!clk->pclk_sel) + return -EPERM; + + /* check if requested parent is in clk parent list */ + for (i = 0; i < clk->pclk_sel->pclk_count; i++) { + if (clk->pclk_sel->pclk_info[i].pclk == parent) { + found = 1; + break; + } + } + + if (!found) + return -EINVAL; + + spin_lock_irqsave(&clocks_lock, flags); + /* reflect parent change in hardware */ + val = readl(clk->pclk_sel->pclk_sel_reg); + val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift); + val |= clk->pclk_sel->pclk_info[i].pclk_val << clk->pclk_sel_shift; + writel(val, clk->pclk_sel->pclk_sel_reg); + spin_unlock_irqrestore(&clocks_lock, flags); + + /* reflect parent change in software */ + clk_reparent(clk, &clk->pclk_sel->pclk_info[i]); + + propagate_rate(clk, 0); + return 0; +} +EXPORT_SYMBOL(clk_set_parent); + +/** + * clk_set_rate - set the clock rate for a clock source + * @clk: clock source + * @rate: desired clock rate in Hz + * + * Returns success (0) or negative errno. + */ +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long flags; + int ret = -EINVAL; + + if (!clk || !rate) + return -EFAULT; + + if (clk->set_rate) { + spin_lock_irqsave(&clocks_lock, flags); + ret = clk->set_rate(clk, rate); + if (!ret) + /* if successful -> propagate */ + propagate_rate(clk, 0); + spin_unlock_irqrestore(&clocks_lock, flags); + } else if (clk->pclk) { + u32 mult = clk->div_factor ? clk->div_factor : 1; + ret = clk_set_rate(clk->pclk, mult * rate); + } + + return ret; +} +EXPORT_SYMBOL(clk_set_rate); + +/* registers clock in platform clock framework */ +void clk_register(struct clk_lookup *cl) +{ + struct clk *clk; + unsigned long flags; + + if (!cl || !cl->clk) + return; + clk = cl->clk; + + spin_lock_irqsave(&clocks_lock, flags); + + INIT_LIST_HEAD(&clk->children); + if (clk->flags & ALWAYS_ENABLED) + clk->ops = NULL; + else if (!clk->ops) + clk->ops = &generic_clkops; + + /* root clock don't have any parents */ + if (!clk->pclk && !clk->pclk_sel) { + list_add(&clk->sibling, &root_clks); + } else if (clk->pclk && !clk->pclk_sel) { + /* add clocks with only one parent to parent's children list */ + list_add(&clk->sibling, &clk->pclk->children); + } else { + /* clocks with more than one parent */ + struct pclk_info *pclk_info; + + pclk_info = pclk_info_get(clk); + if (!pclk_info) { + pr_err("CLKDEV: invalid pclk info of clk with" + " %s dev_id and %s con_id\n", + cl->dev_id, cl->con_id); + } else { + clk->pclk = pclk_info->pclk; + list_add(&clk->sibling, &pclk_info->pclk->children); + } + } + + spin_unlock_irqrestore(&clocks_lock, flags); + + /* debugfs specific */ +#ifdef CONFIG_DEBUG_FS + list_add(&clk->node, &clocks); + clk->cl = cl; +#endif + + /* add clock to arm clockdev framework */ + clkdev_add(cl); +} + +/** + * propagate_rate - recalculate and propagate all clocks to children + * @pclk: parent clock required to be propogated + * @on_init: flag for enabling clocks which are ENABLED_ON_INIT. + * + * Recalculates all children clocks + */ +void propagate_rate(struct clk *pclk, int on_init) +{ + struct clk *clk, *_temp; + int ret = 0; + + list_for_each_entry_safe(clk, _temp, &pclk->children, sibling) { + if (clk->recalc) { + ret = clk->recalc(clk); + /* + * recalc will return error if clk out is not programmed + * In this case configure default rate. + */ + if (ret && clk->set_rate) + clk->set_rate(clk, 0); + } + propagate_rate(clk, on_init); + + if (!on_init) + continue; + + /* Enable clks enabled on init, in software view */ + if (clk->flags & ENABLED_ON_INIT) + do_clk_enable(clk); + } +} + +/** + * round_rate_index - return closest programmable rate index in rate_config tbl + * @clk: ptr to clock structure + * @drate: desired rate + * @rate: final rate will be returned in this variable only. + * + * Finds index in rate_config for highest clk rate which is less than + * requested rate. If there is no clk rate lesser than requested rate then + * -EINVAL is returned. This routine assumes that rate_config is written + * in incrementing order of clk rates. + * If drate passed is zero then default rate is programmed. + */ +static int +round_rate_index(struct clk *clk, unsigned long drate, unsigned long *rate) +{ + unsigned long tmp = 0, prev_rate = 0; + int index; + + if (!clk->calc_rate) + return -EFAULT; + + if (!drate) + return -EINVAL; + + /* + * This loops ends on two conditions: + * - as soon as clk is found with rate greater than requested rate. + * - if all clks in rate_config are smaller than requested rate. + */ + for (index = 0; index < clk->rate_config.count; index++) { + prev_rate = tmp; + tmp = clk->calc_rate(clk, index); + if (drate < tmp) { + index--; + break; + } + } + /* return if can't find suitable clock */ + if (index < 0) { + index = -EINVAL; + *rate = 0; + } else if (index == clk->rate_config.count) { + /* program with highest clk rate possible */ + index = clk->rate_config.count - 1; + *rate = tmp; + } else + *rate = prev_rate; + + return index; +} + +/** + * clk_round_rate - adjust a rate to the exact rate a clock can provide + * @clk: clock source + * @rate: desired clock rate in Hz + * + * Returns rounded clock rate in Hz, or negative errno. + */ +long clk_round_rate(struct clk *clk, unsigned long drate) +{ + long rate = 0; + int index; + + /* + * propagate call to parent who supports calc_rate. Similar approach is + * used in clk_set_rate. + */ + if (!clk->calc_rate) { + u32 mult; + if (!clk->pclk) + return clk->rate; + + mult = clk->div_factor ? clk->div_factor : 1; + return clk_round_rate(clk->pclk, mult * drate) / mult; + } + + index = round_rate_index(clk, drate, &rate); + if (index >= 0) + return rate; + else + return index; +} +EXPORT_SYMBOL(clk_round_rate); + +/*All below functions are called with lock held */ + +/* + * Calculates pll clk rate for specific value of mode, m, n and p + * + * In normal mode + * rate = (2 * M[15:8] * Fin)/(N * 2^P) + * + * In Dithered mode + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) + */ +unsigned long pll_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct pll_rate_tbl *tbls = clk->rate_config.tbls; + unsigned int mode; + + mode = tbls[index].mode ? 256 : 1; + return (((2 * rate / 10000) * tbls[index].m) / + (mode * tbls[index].n * (1 << tbls[index].p))) * 10000; +} + +/* + * calculates current programmed rate of pll1 + * + * In normal mode + * rate = (2 * M[15:8] * Fin)/(N * 2^P) + * + * In Dithered mode + * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P) + */ +int pll_clk_recalc(struct clk *clk) +{ + struct pll_clk_config *config = clk->private_data; + unsigned int num = 2, den = 0, val, mode = 0; + + mode = (readl(config->mode_reg) >> config->masks->mode_shift) & + config->masks->mode_mask; + + val = readl(config->cfg_reg); + /* calculate denominator */ + den = (val >> config->masks->div_p_shift) & config->masks->div_p_mask; + den = 1 << den; + den *= (val >> config->masks->div_n_shift) & config->masks->div_n_mask; + + /* calculate numerator & denominator */ + if (!mode) { + /* Normal mode */ + num *= (val >> config->masks->norm_fdbk_m_shift) & + config->masks->norm_fdbk_m_mask; + } else { + /* Dithered mode */ + num *= (val >> config->masks->dith_fdbk_m_shift) & + config->masks->dith_fdbk_m_mask; + den *= 256; + } + + if (!den) + return -EINVAL; + + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; + return 0; +} + +/* + * Configures new clock rate of pll + */ +int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct pll_rate_tbl *tbls = clk->rate_config.tbls; + struct pll_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->mode_reg) & + ~(config->masks->mode_mask << config->masks->mode_shift); + val |= (tbls[i].mode & config->masks->mode_mask) << + config->masks->mode_shift; + writel(val, config->mode_reg); + + val = readl(config->cfg_reg) & + ~(config->masks->div_p_mask << config->masks->div_p_shift); + val |= (tbls[i].p & config->masks->div_p_mask) << + config->masks->div_p_shift; + val &= ~(config->masks->div_n_mask << config->masks->div_n_shift); + val |= (tbls[i].n & config->masks->div_n_mask) << + config->masks->div_n_shift; + val &= ~(config->masks->dith_fdbk_m_mask << + config->masks->dith_fdbk_m_shift); + if (tbls[i].mode) + val |= (tbls[i].m & config->masks->dith_fdbk_m_mask) << + config->masks->dith_fdbk_m_shift; + else + val |= (tbls[i].m & config->masks->norm_fdbk_m_mask) << + config->masks->norm_fdbk_m_shift; + + writel(val, config->cfg_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Calculates ahb, apb clk rate for specific value of div + */ +unsigned long bus_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct bus_rate_tbl *tbls = clk->rate_config.tbls; + + return rate / (tbls[index].div + 1); +} + +/* calculates current programmed rate of ahb or apb bus */ +int bus_clk_recalc(struct clk *clk) +{ + struct bus_clk_config *config = clk->private_data; + unsigned int div; + + div = ((readl(config->reg) >> config->masks->shift) & + config->masks->mask) + 1; + + if (!div) + return -EINVAL; + + clk->rate = (unsigned long)clk->pclk->rate / div; + return 0; +} + +/* Configures new clock rate of AHB OR APB bus */ +int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct bus_rate_tbl *tbls = clk->rate_config.tbls; + struct bus_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->reg) & + ~(config->masks->mask << config->masks->shift); + val |= (tbls[i].div & config->masks->mask) << config->masks->shift; + writel(val, config->reg); + + clk->rate = rate; + + return 0; +} + +/* + * gives rate for different values of eq, x and y + * + * Fout from synthesizer can be given from two equations: + * Fout1 = (Fin * X/Y)/2 EQ1 + * Fout2 = Fin * X/Y EQ2 + */ +unsigned long aux_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct aux_rate_tbl *tbls = clk->rate_config.tbls; + u8 eq = tbls[index].eq ? 1 : 2; + + return (((rate/10000) * tbls[index].xscale) / + (tbls[index].yscale * eq)) * 10000; +} + +/* + * calculates current programmed rate of auxiliary synthesizers + * used by: UART, FIRDA + * + * Fout from synthesizer can be given from two equations: + * Fout1 = (Fin * X/Y)/2 + * Fout2 = Fin * X/Y + * + * Selection of eqn 1 or 2 is programmed in register + */ +int aux_clk_recalc(struct clk *clk) +{ + struct aux_clk_config *config = clk->private_data; + unsigned int num = 1, den = 1, val, eqn; + + val = readl(config->synth_reg); + + eqn = (val >> config->masks->eq_sel_shift) & + config->masks->eq_sel_mask; + if (eqn == config->masks->eq1_mask) + den *= 2; + + /* calculate numerator */ + num = (val >> config->masks->xscale_sel_shift) & + config->masks->xscale_sel_mask; + + /* calculate denominator */ + den *= (val >> config->masks->yscale_sel_shift) & + config->masks->yscale_sel_mask; + + if (!den) + return -EINVAL; + + clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000; + return 0; +} + +/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ +int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct aux_rate_tbl *tbls = clk->rate_config.tbls; + struct aux_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & + ~(config->masks->eq_sel_mask << config->masks->eq_sel_shift); + val |= (tbls[i].eq & config->masks->eq_sel_mask) << + config->masks->eq_sel_shift; + val &= ~(config->masks->xscale_sel_mask << + config->masks->xscale_sel_shift); + val |= (tbls[i].xscale & config->masks->xscale_sel_mask) << + config->masks->xscale_sel_shift; + val &= ~(config->masks->yscale_sel_mask << + config->masks->yscale_sel_shift); + val |= (tbls[i].yscale & config->masks->yscale_sel_mask) << + config->masks->yscale_sel_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Calculates gpt clk rate for different values of mscale and nscale + * + * Fout= Fin/((2 ^ (N+1)) * (M+1)) + */ +unsigned long gpt_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct gpt_rate_tbl *tbls = clk->rate_config.tbls; + + return rate / ((1 << (tbls[index].nscale + 1)) * + (tbls[index].mscale + 1)); +} + +/* + * calculates current programmed rate of gpt synthesizers + * Fout from synthesizer can be given from below equations: + * Fout= Fin/((2 ^ (N+1)) * (M+1)) + */ +int gpt_clk_recalc(struct clk *clk) +{ + struct gpt_clk_config *config = clk->private_data; + unsigned int div = 1, val; + + val = readl(config->synth_reg); + div += (val >> config->masks->mscale_sel_shift) & + config->masks->mscale_sel_mask; + div *= 1 << (((val >> config->masks->nscale_sel_shift) & + config->masks->nscale_sel_mask) + 1); + + if (!div) + return -EINVAL; + + clk->rate = (unsigned long)clk->pclk->rate / div; + return 0; +} + +/* Configures new clock rate of gptiliary synthesizers used by: UART, FIRDA*/ +int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct gpt_rate_tbl *tbls = clk->rate_config.tbls; + struct gpt_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & ~(config->masks->mscale_sel_mask << + config->masks->mscale_sel_shift); + val |= (tbls[i].mscale & config->masks->mscale_sel_mask) << + config->masks->mscale_sel_shift; + val &= ~(config->masks->nscale_sel_mask << + config->masks->nscale_sel_shift); + val |= (tbls[i].nscale & config->masks->nscale_sel_mask) << + config->masks->nscale_sel_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Calculates clcd clk rate for different values of div + * + * Fout from synthesizer can be given from below equation: + * Fout= Fin/2*div (division factor) + * div is 17 bits:- + * 0-13 (fractional part) + * 14-16 (integer part) + * To calculate Fout we left shift val by 14 bits and divide Fin by + * complete div (including fractional part) and then right shift the + * result by 14 places. + */ +unsigned long clcd_calc_rate(struct clk *clk, int index) +{ + unsigned long rate = clk->pclk->rate; + struct clcd_rate_tbl *tbls = clk->rate_config.tbls; + + rate /= 1000; + rate <<= 12; + rate /= (2 * tbls[index].div); + rate >>= 12; + rate *= 1000; + + return rate; +} + +/* + * calculates current programmed rate of clcd synthesizer + * Fout from synthesizer can be given from below equation: + * Fout= Fin/2*div (division factor) + * div is 17 bits:- + * 0-13 (fractional part) + * 14-16 (integer part) + * To calculate Fout we left shift val by 14 bits and divide Fin by + * complete div (including fractional part) and then right shift the + * result by 14 places. + */ +int clcd_clk_recalc(struct clk *clk) +{ + struct clcd_clk_config *config = clk->private_data; + unsigned int div = 1; + unsigned long prate; + unsigned int val; + + val = readl(config->synth_reg); + div = (val >> config->masks->div_factor_shift) & + config->masks->div_factor_mask; + + if (!div) + return -EINVAL; + + prate = clk->pclk->rate / 1000; /* first level division, make it KHz */ + + clk->rate = (((unsigned long)prate << 12) / (2 * div)) >> 12; + clk->rate *= 1000; + return 0; +} + +/* Configures new clock rate of auxiliary synthesizers used by: UART, FIRDA*/ +int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate) +{ + struct clcd_rate_tbl *tbls = clk->rate_config.tbls; + struct clcd_clk_config *config = clk->private_data; + unsigned long val, rate; + int i; + + i = round_rate_index(clk, desired_rate, &rate); + if (i < 0) + return i; + + val = readl(config->synth_reg) & ~(config->masks->div_factor_mask << + config->masks->div_factor_shift); + val |= (tbls[i].div & config->masks->div_factor_mask) << + config->masks->div_factor_shift; + writel(val, config->synth_reg); + + clk->rate = rate; + + return 0; +} + +/* + * Used for clocks that always have value as the parent clock divided by a + * fixed divisor + */ +int follow_parent(struct clk *clk) +{ + unsigned int div_factor = (clk->div_factor < 1) ? 1 : clk->div_factor; + + clk->rate = clk->pclk->rate/div_factor; + return 0; +} + +/** + * recalc_root_clocks - recalculate and propagate all root clocks + * + * Recalculates all root clocks (clocks with no parent), which if the + * clock's .recalc is set correctly, should also propagate their rates. + */ +void recalc_root_clocks(void) +{ + struct clk *pclk; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&clocks_lock, flags); + list_for_each_entry(pclk, &root_clks, sibling) { + if (pclk->recalc) { + ret = pclk->recalc(pclk); + /* + * recalc will return error if clk out is not programmed + * In this case configure default clock. + */ + if (ret && pclk->set_rate) + pclk->set_rate(pclk, 0); + } + propagate_rate(pclk, 1); + /* Enable clks enabled on init, in software view */ + if (pclk->flags & ENABLED_ON_INIT) + do_clk_enable(pclk); + } + spin_unlock_irqrestore(&clocks_lock, flags); +} + +void __init clk_init(void) +{ + recalc_root_clocks(); +} + +#ifdef CONFIG_DEBUG_FS +/* + * debugfs support to trace clock tree hierarchy and attributes + */ +static struct dentry *clk_debugfs_root; +static int clk_debugfs_register_one(struct clk *c) +{ + int err; + struct dentry *d; + struct clk *pa = c->pclk; + char s[255]; + char *p = s; + + if (c) { + if (c->cl->con_id) + p += sprintf(p, "%s", c->cl->con_id); + if (c->cl->dev_id) + p += sprintf(p, "%s", c->cl->dev_id); + } + d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root); + if (!d) + return -ENOMEM; + c->dent = d; + + d = debugfs_create_u32("usage_count", S_IRUGO, c->dent, + (u32 *)&c->usage_count); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate); + if (!d) { + err = -ENOMEM; + goto err_out; + } + d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags); + if (!d) { + err = -ENOMEM; + goto err_out; + } + return 0; + +err_out: + debugfs_remove_recursive(c->dent); + return err; +} + +static int clk_debugfs_register(struct clk *c) +{ + int err; + struct clk *pa = c->pclk; + + if (pa && !pa->dent) { + err = clk_debugfs_register(pa); + if (err) + return err; + } + + if (!c->dent) { + err = clk_debugfs_register_one(c); + if (err) + return err; + } + return 0; +} + +static int __init clk_debugfs_init(void) +{ + struct clk *c; + struct dentry *d; + int err; + + d = debugfs_create_dir("clock", NULL); + if (!d) + return -ENOMEM; + clk_debugfs_root = d; + + list_for_each_entry(c, &clocks, node) { + err = clk_debugfs_register(c); + if (err) + goto err_out; + } + return 0; +err_out: + debugfs_remove_recursive(clk_debugfs_root); + return err; +} +late_initcall(clk_debugfs_init); + +static int clk_debugfs_reparent(struct clk *c) +{ + debugfs_remove(c->dent); + return clk_debugfs_register_one(c); +} +#endif /* CONFIG_DEBUG_FS */ diff --git a/trunk/arch/arm/plat-spear/include/plat/clock.h b/trunk/arch/arm/plat-spear/include/plat/clock.h new file mode 100644 index 000000000000..0062bafef12d --- /dev/null +++ b/trunk/arch/arm/plat-spear/include/plat/clock.h @@ -0,0 +1,249 @@ +/* + * arch/arm/plat-spear/include/plat/clock.h + * + * Clock framework definitions for SPEAr platform + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_CLOCK_H +#define __PLAT_CLOCK_H + +#include +#include +#include + +/* clk structure flags */ +#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */ +#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */ +#define ENABLED_ON_INIT (1 << 2) /* clocks enabled at init */ + +/** + * struct clkops - clock operations + * @enable: pointer to clock enable function + * @disable: pointer to clock disable function + */ +struct clkops { + int (*enable) (struct clk *); + void (*disable) (struct clk *); +}; + +/** + * struct pclk_info - parents info + * @pclk: pointer to parent clk + * @pclk_val: value to be written for selecting this parent + */ +struct pclk_info { + struct clk *pclk; + u8 pclk_val; +}; + +/** + * struct pclk_sel - parents selection configuration + * @pclk_info: pointer to array of parent clock info + * @pclk_count: number of parents + * @pclk_sel_reg: register for selecting a parent + * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also) + */ +struct pclk_sel { + struct pclk_info *pclk_info; + u8 pclk_count; + void __iomem *pclk_sel_reg; + unsigned int pclk_sel_mask; +}; + +/** + * struct rate_config - clk rate configurations + * @tbls: array of device specific clk rate tables, in ascending order of rates + * @count: size of tbls array + * @default_index: default setting when originally disabled + */ +struct rate_config { + void *tbls; + u8 count; + u8 default_index; +}; + +/** + * struct clk - clock structure + * @usage_count: num of users who enabled this clock + * @flags: flags for clock properties + * @rate: programmed clock rate in Hz + * @en_reg: clk enable/disable reg + * @en_reg_bit: clk enable/disable bit + * @ops: clk enable/disable ops - generic_clkops selected if NULL + * @recalc: pointer to clock rate recalculate function + * @set_rate: pointer to clock set rate function + * @calc_rate: pointer to clock get rate function for index + * @rate_config: rate configuration information, used by set_rate + * @div_factor: division factor to parent clock. + * @pclk: current parent clk + * @pclk_sel: pointer to parent selection structure + * @pclk_sel_shift: register shift for selecting parent of this clock + * @children: list for childrens or this clock + * @sibling: node for list of clocks having same parents + * @private_data: clock specific private data + * @node: list to maintain clocks linearly + * @cl: clocklook up associated with this clock + * @dent: object for debugfs + */ +struct clk { + unsigned int usage_count; + unsigned int flags; + unsigned long rate; + void __iomem *en_reg; + u8 en_reg_bit; + const struct clkops *ops; + int (*recalc) (struct clk *); + int (*set_rate) (struct clk *, unsigned long rate); + unsigned long (*calc_rate)(struct clk *, int index); + struct rate_config rate_config; + unsigned int div_factor; + + struct clk *pclk; + struct pclk_sel *pclk_sel; + unsigned int pclk_sel_shift; + + struct list_head children; + struct list_head sibling; + void *private_data; +#ifdef CONFIG_DEBUG_FS + struct list_head node; + struct clk_lookup *cl; + struct dentry *dent; +#endif +}; + +/* pll configuration structure */ +struct pll_clk_masks { + u32 mode_mask; + u32 mode_shift; + + u32 norm_fdbk_m_mask; + u32 norm_fdbk_m_shift; + u32 dith_fdbk_m_mask; + u32 dith_fdbk_m_shift; + u32 div_p_mask; + u32 div_p_shift; + u32 div_n_mask; + u32 div_n_shift; +}; + +struct pll_clk_config { + void __iomem *mode_reg; + void __iomem *cfg_reg; + struct pll_clk_masks *masks; +}; + +/* pll clk rate config structure */ +struct pll_rate_tbl { + u8 mode; + u16 m; + u8 n; + u8 p; +}; + +/* ahb and apb bus configuration structure */ +struct bus_clk_masks { + u32 mask; + u32 shift; +}; + +struct bus_clk_config { + void __iomem *reg; + struct bus_clk_masks *masks; +}; + +/* ahb and apb clk bus rate config structure */ +struct bus_rate_tbl { + u8 div; +}; + +/* Aux clk configuration structure: applicable to UART and FIRDA */ +struct aux_clk_masks { + u32 eq_sel_mask; + u32 eq_sel_shift; + u32 eq1_mask; + u32 eq2_mask; + u32 xscale_sel_mask; + u32 xscale_sel_shift; + u32 yscale_sel_mask; + u32 yscale_sel_shift; +}; + +struct aux_clk_config { + void __iomem *synth_reg; + struct aux_clk_masks *masks; +}; + +/* aux clk rate config structure */ +struct aux_rate_tbl { + u16 xscale; + u16 yscale; + u8 eq; +}; + +/* GPT clk configuration structure */ +struct gpt_clk_masks { + u32 mscale_sel_mask; + u32 mscale_sel_shift; + u32 nscale_sel_mask; + u32 nscale_sel_shift; +}; + +struct gpt_clk_config { + void __iomem *synth_reg; + struct gpt_clk_masks *masks; +}; + +/* gpt clk rate config structure */ +struct gpt_rate_tbl { + u16 mscale; + u16 nscale; +}; + +/* clcd clk configuration structure */ +struct clcd_synth_masks { + u32 div_factor_mask; + u32 div_factor_shift; +}; + +struct clcd_clk_config { + void __iomem *synth_reg; + struct clcd_synth_masks *masks; +}; + +/* clcd clk rate config structure */ +struct clcd_rate_tbl { + u16 div; +}; + +/* platform specific clock functions */ +void __init clk_init(void); +void clk_register(struct clk_lookup *cl); +void recalc_root_clocks(void); + +/* clock recalc & set rate functions */ +int follow_parent(struct clk *clk); +unsigned long pll_calc_rate(struct clk *clk, int index); +int pll_clk_recalc(struct clk *clk); +int pll_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long bus_calc_rate(struct clk *clk, int index); +int bus_clk_recalc(struct clk *clk); +int bus_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long gpt_calc_rate(struct clk *clk, int index); +int gpt_clk_recalc(struct clk *clk); +int gpt_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long aux_calc_rate(struct clk *clk, int index); +int aux_clk_recalc(struct clk *clk); +int aux_clk_set_rate(struct clk *clk, unsigned long desired_rate); +unsigned long clcd_calc_rate(struct clk *clk, int index); +int clcd_clk_recalc(struct clk *clk); +int clcd_clk_set_rate(struct clk *clk, unsigned long desired_rate); + +#endif /* __PLAT_CLOCK_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/debug-macro.S b/trunk/arch/arm/plat-spear/include/plat/debug-macro.S index 02b160a1ec9b..ab3de721c5db 100644 --- a/trunk/arch/arm/plat-spear/include/plat/debug-macro.S +++ b/trunk/arch/arm/plat-spear/include/plat/debug-macro.S @@ -12,7 +12,7 @@ */ #include -#include +#include .macro addruart, rp, rv, tmp mov \rp, #SPEAR_DBG_UART_BASE @ Physical base diff --git a/trunk/arch/arm/plat-spear/include/plat/hardware.h b/trunk/arch/arm/plat-spear/include/plat/hardware.h deleted file mode 100644 index 70187d763e26..000000000000 --- a/trunk/arch/arm/plat-spear/include/plat/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * arch/arm/plat-spear/include/plat/hardware.h - * - * Hardware definitions for SPEAr - * - * Copyright (C) 2010 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PLAT_HARDWARE_H -#define __PLAT_HARDWARE_H - -#endif /* __PLAT_HARDWARE_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/padmux.h b/trunk/arch/arm/plat-spear/include/plat/padmux.h new file mode 100644 index 000000000000..877f3adcf610 --- /dev/null +++ b/trunk/arch/arm/plat-spear/include/plat/padmux.h @@ -0,0 +1,92 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.h + * + * SPEAr platform specific gpio pads muxing file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __PLAT_PADMUX_H +#define __PLAT_PADMUX_H + +#include + +/* + * struct pmx_reg: configuration structure for mode reg and mux reg + * + * offset: offset of mode reg + * mask: mask of mode reg + */ +struct pmx_reg { + u32 offset; + u32 mask; +}; + +/* + * struct pmx_dev_mode: configuration structure every group of modes of a device + * + * ids: all modes for this configuration + * mask: mask for supported mode + */ +struct pmx_dev_mode { + u32 ids; + u32 mask; +}; + +/* + * struct pmx_mode: mode definition structure + * + * name: mode name + * mask: mode mask + */ +struct pmx_mode { + char *name; + u32 id; + u32 mask; +}; + +/* + * struct pmx_dev: device definition structure + * + * name: device name + * modes: device configuration array for different modes supported + * mode_count: size of modes array + * is_active: is peripheral active/enabled + * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg + */ +struct pmx_dev { + char *name; + struct pmx_dev_mode *modes; + u8 mode_count; + bool is_active; + bool enb_on_reset; +}; + +/* + * struct pmx_driver: driver definition structure + * + * mode: mode to be set + * devs: array of pointer to pmx devices + * devs_count: ARRAY_SIZE of devs + * base: base address of soc config registers + * mode_reg: structure of mode config register + * mux_reg: structure of device mux config register + */ +struct pmx_driver { + struct pmx_mode *mode; + struct pmx_dev **devs; + u8 devs_count; + u32 *base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; +}; + +/* pmx functions */ +int pmx_register(struct pmx_driver *driver); + +#endif /* __PLAT_PADMUX_H */ diff --git a/trunk/arch/arm/plat-spear/include/plat/uncompress.h b/trunk/arch/arm/plat-spear/include/plat/uncompress.h index 1bf84527aee4..6dd455bafdfd 100644 --- a/trunk/arch/arm/plat-spear/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-spear/include/plat/uncompress.h @@ -13,7 +13,7 @@ #include #include -#include +#include #ifndef __PLAT_UNCOMPRESS_H #define __PLAT_UNCOMPRESS_H diff --git a/trunk/arch/arm/plat-spear/padmux.c b/trunk/arch/arm/plat-spear/padmux.c new file mode 100644 index 000000000000..555eec6dc1cb --- /dev/null +++ b/trunk/arch/arm/plat-spear/padmux.c @@ -0,0 +1,164 @@ +/* + * arch/arm/plat-spear/include/plat/padmux.c + * + * SPEAr platform specific gpio pads muxing source file + * + * Copyright (C) 2009 ST Microelectronics + * Viresh Kumar + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +/* + * struct pmx: pmx definition structure + * + * base: base address of configuration registers + * mode_reg: mode configurations + * mux_reg: muxing configurations + * active_mode: pointer to current active mode + */ +struct pmx { + u32 base; + struct pmx_reg mode_reg; + struct pmx_reg mux_reg; + struct pmx_mode *active_mode; +}; + +static struct pmx *pmx; + +/** + * pmx_mode_set - Enables an multiplexing mode + * @mode - pointer to pmx mode + * + * It will set mode of operation in hardware. + * Returns -ve on Err otherwise 0 + */ +static int pmx_mode_set(struct pmx_mode *mode) +{ + u32 val; + + if (!mode->name) + return -EFAULT; + + pmx->active_mode = mode; + + val = readl(pmx->base + pmx->mode_reg.offset); + val &= ~pmx->mode_reg.mask; + val |= mode->mask & pmx->mode_reg.mask; + writel(val, pmx->base + pmx->mode_reg.offset); + + return 0; +} + +/** + * pmx_devs_enable - Enables list of devices + * @devs - pointer to pmx device array + * @count - number of devices to enable + * + * It will enable pads for all required peripherals once and only once. + * If peripheral is not supported by current mode then request is rejected. + * Conflicts between peripherals are not handled and peripherals will be + * enabled in the order they are present in pmx_dev array. + * In case of conflicts last peripheral enabled will be present. + * Returns -ve on Err otherwise 0 + */ +static int pmx_devs_enable(struct pmx_dev **devs, u8 count) +{ + u32 val, i, mask; + + if (!count) + return -EINVAL; + + val = readl(pmx->base + pmx->mux_reg.offset); + for (i = 0; i < count; i++) { + u8 j = 0; + + if (!devs[i]->name || !devs[i]->modes) { + printk(KERN_ERR "padmux: dev name or modes is null\n"); + continue; + } + /* check if peripheral exists in active mode */ + if (pmx->active_mode) { + bool found = false; + for (j = 0; j < devs[i]->mode_count; j++) { + if (devs[i]->modes[j].ids & + pmx->active_mode->id) { + found = true; + break; + } + } + if (found == false) { + printk(KERN_ERR "%s device not available in %s"\ + "mode\n", devs[i]->name, + pmx->active_mode->name); + continue; + } + } + + /* enable peripheral */ + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask; + if (devs[i]->enb_on_reset) + val &= ~mask; + else + val |= mask; + + devs[i]->is_active = true; + } + writel(val, pmx->base + pmx->mux_reg.offset); + kfree(pmx); + + /* this will ensure that multiplexing can't be changed now */ + pmx = (struct pmx *)-1; + + return 0; +} + +/** + * pmx_register - registers a platform requesting pad mux feature + * @driver - pointer to driver structure containing driver specific parameters + * + * Also this must be called only once. This will allocate memory for pmx + * structure, will call pmx_mode_set, will call pmx_devs_enable. + * Returns -ve on Err otherwise 0 + */ +int pmx_register(struct pmx_driver *driver) +{ + int ret = 0; + + if (pmx) + return -EPERM; + if (!driver->base || !driver->devs) + return -EFAULT; + + pmx = kzalloc(sizeof(*pmx), GFP_KERNEL); + if (!pmx) + return -ENOMEM; + + pmx->base = (u32)driver->base; + pmx->mode_reg.offset = driver->mode_reg.offset; + pmx->mode_reg.mask = driver->mode_reg.mask; + pmx->mux_reg.offset = driver->mux_reg.offset; + pmx->mux_reg.mask = driver->mux_reg.mask; + + /* choose mode to enable */ + if (driver->mode) { + ret = pmx_mode_set(driver->mode); + if (ret) + goto pmx_fail; + } + ret = pmx_devs_enable(driver->devs, driver->devs_count); + if (ret) + goto pmx_fail; + + return 0; + +pmx_fail: + return ret; +} diff --git a/trunk/arch/arm/plat-spear/pl080.c b/trunk/arch/arm/plat-spear/pl080.c index d53d75e1af5e..a56a067717c1 100644 --- a/trunk/arch/arm/plat-spear/pl080.c +++ b/trunk/arch/arm/plat-spear/pl080.c @@ -17,6 +17,7 @@ #include #include #include +#include #include static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); diff --git a/trunk/arch/arm/plat-spear/restart.c b/trunk/arch/arm/plat-spear/restart.c index 16f203e78d89..4471a232713a 100644 --- a/trunk/arch/arm/plat-spear/restart.c +++ b/trunk/arch/arm/plat-spear/restart.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include void spear_restart(char mode, const char *cmd) diff --git a/trunk/arch/arm/plat-spear/time.c b/trunk/arch/arm/plat-spear/time.c index 1c94989d725f..9a378987bbb1 100644 --- a/trunk/arch/arm/plat-spear/time.c +++ b/trunk/arch/arm/plat-spear/time.c @@ -15,14 +15,15 @@ #include #include #include +#include #include #include +#include +#include #include #include #include #include -#include -#include /* * We would use TIMER0 and TIMER1 as clockevent and clocksource. @@ -175,7 +176,7 @@ static struct irqaction spear_timer_irq = { .handler = spear_timer_interrupt }; -static void __init spear_clockevent_init(void) +static void __init spear_clockevent_init(int irq) { u32 tick_rate; @@ -195,22 +196,35 @@ static void __init spear_clockevent_init(void) clockevents_register_device(&clkevt); - setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); + setup_irq(irq, &spear_timer_irq); } -void __init spear_setup_timer(void) +const static struct of_device_id timer_of_match[] __initconst = { + { .compatible = "st,spear-timer", }, + { }, +}; + +void __init spear_setup_of_timer(void) { - int ret; + struct device_node *np; + int irq, ret; + + np = of_find_matching_node(NULL, timer_of_match); + if (!np) { + pr_err("%s: No timer passed via DT\n", __func__); + return; + } - if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { - pr_err("%s:cannot get IO addr\n", __func__); + irq = irq_of_parse_and_map(np, 0); + if (!irq) { + pr_err("%s: No irq passed for timer via DT\n", __func__); return; } - gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); + gpt_base = of_iomap(np, 0); if (!gpt_base) { - pr_err("%s:ioremap failed for gpt\n", __func__); - goto err_mem; + pr_err("%s: of iomap failed\n", __func__); + return; } gpt_clk = clk_get_sys("gpt0", NULL); @@ -219,21 +233,19 @@ void __init spear_setup_timer(void) goto err_iomap; } - ret = clk_prepare_enable(gpt_clk); + ret = clk_enable(gpt_clk); if (ret < 0) { - pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); - goto err_prepare_enable_clk; + pr_err("%s:couldn't enable gpt clock\n", __func__); + goto err_clk; } - spear_clockevent_init(); + spear_clockevent_init(irq); spear_clocksource_init(); return; -err_prepare_enable_clk: +err_clk: clk_put(gpt_clk); err_iomap: iounmap(gpt_base); -err_mem: - release_mem_region(SPEAR_GPT0_BASE, SZ_1K); } diff --git a/trunk/arch/ia64/include/asm/futex.h b/trunk/arch/ia64/include/asm/futex.h index d2bf1fd5e44f..0ab82cc2dc8f 100644 --- a/trunk/arch/ia64/include/asm/futex.h +++ b/trunk/arch/ia64/include/asm/futex.h @@ -106,16 +106,15 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, return -EFAULT; { - register unsigned long r8 __asm ("r8"); + register unsigned long r8 __asm ("r8") = 0; unsigned long prev; __asm__ __volatile__( " mf;; \n" - " mov %0=r0 \n" - " mov ar.ccv=%4;; \n" - "[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n" + " mov ar.ccv=%3;; \n" + "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n" " .xdata4 \"__ex_table\", 1b-., 2f-. \n" "[2:]" - : "=r" (r8), "=r" (prev) + : "=r" (prev) : "r" (uaddr), "r" (newval), "rO" ((long) (unsigned) oldval) : "memory"); diff --git a/trunk/arch/ia64/kernel/perfmon.c b/trunk/arch/ia64/kernel/perfmon.c index f00ba025375d..9d0fd7d5bb82 100644 --- a/trunk/arch/ia64/kernel/perfmon.c +++ b/trunk/arch/ia64/kernel/perfmon.c @@ -604,6 +604,12 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f) spin_unlock(&(x)->ctx_lock); } +static inline unsigned int +pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct) +{ + return do_munmap(mm, addr, len); +} + static inline unsigned long pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec) { @@ -1452,9 +1458,8 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu) * a PROTECT_CTX() section. */ static int -pfm_remove_smpl_mapping(void *vaddr, unsigned long size) +pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size) { - struct task_struct *task = current; int r; /* sanity checks */ @@ -1468,8 +1473,13 @@ pfm_remove_smpl_mapping(void *vaddr, unsigned long size) /* * does the actual unmapping */ - r = vm_munmap((unsigned long)vaddr, size); + down_write(&task->mm->mmap_sem); + DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size)); + + r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0); + + up_write(&task->mm->mmap_sem); if (r !=0) { printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size); } @@ -1935,7 +1945,7 @@ pfm_flush(struct file *filp, fl_owner_t id) * because some VM function reenables interrupts. * */ - if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size); + if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size); return 0; } diff --git a/trunk/arch/m68k/configs/m5275evb_defconfig b/trunk/arch/m68k/configs/m5275evb_defconfig index a1230e82bb1e..33c32aeca12b 100644 --- a/trunk/arch/m68k/configs/m5275evb_defconfig +++ b/trunk/arch/m68k/configs/m5275evb_defconfig @@ -49,6 +49,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_FEC=y +CONFIG_FEC2=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set CONFIG_PPP=y diff --git a/trunk/arch/m68k/platform/527x/config.c b/trunk/arch/m68k/platform/527x/config.c index f91a53294c35..7ed848c3b848 100644 --- a/trunk/arch/m68k/platform/527x/config.c +++ b/trunk/arch/m68k/platform/527x/config.c @@ -74,7 +74,9 @@ static void __init m527x_fec_init(void) writew(par | 0xf00, MCF_IPSBAR + 0x100082); v = readb(MCF_IPSBAR + 0x100078); writeb(v | 0xc0, MCF_IPSBAR + 0x100078); +#endif +#ifdef CONFIG_FEC2 /* Set multi-function pins to ethernet mode for fec1 */ par = readw(MCF_IPSBAR + 0x100082); writew(par | 0xa0, MCF_IPSBAR + 0x100082); diff --git a/trunk/arch/m68k/platform/68EZ328/Makefile b/trunk/arch/m68k/platform/68EZ328/Makefile index b44d799b1115..ee97735a242c 100644 --- a/trunk/arch/m68k/platform/68EZ328/Makefile +++ b/trunk/arch/m68k/platform/68EZ328/Makefile @@ -3,3 +3,9 @@ # obj-y := config.o + +extra-y := bootlogo.rh + +$(obj)/bootlogo.rh: $(src)/bootlogo.h + perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \ + > $(obj)/bootlogo.rh diff --git a/trunk/arch/m68k/platform/68VZ328/bootlogo.h b/trunk/arch/m68k/platform/68EZ328/bootlogo.h similarity index 99% rename from trunk/arch/m68k/platform/68VZ328/bootlogo.h rename to trunk/arch/m68k/platform/68EZ328/bootlogo.h index b38e2b255142..e842bdae5839 100644 --- a/trunk/arch/m68k/platform/68VZ328/bootlogo.h +++ b/trunk/arch/m68k/platform/68EZ328/bootlogo.h @@ -1,6 +1,6 @@ #define splash_width 640 #define splash_height 480 -unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = { +static unsigned char splash_bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/trunk/arch/m68k/platform/68VZ328/Makefile b/trunk/arch/m68k/platform/68VZ328/Makefile index a49d75e65489..447ffa0fd7c7 100644 --- a/trunk/arch/m68k/platform/68VZ328/Makefile +++ b/trunk/arch/m68k/platform/68VZ328/Makefile @@ -3,9 +3,14 @@ # obj-y := config.o -extra-$(DRAGEN2):= screen.h +logo-$(UCDIMM) := bootlogo.rh +logo-$(DRAGEN2) := screen.h +extra-y := $(logo-y) + +$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h + perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh $(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h -clean-files := $(obj)/screen.h +clean-files := $(obj)/screen.h $(obj)/bootlogo.rh diff --git a/trunk/arch/m68k/platform/coldfire/device.c b/trunk/arch/m68k/platform/coldfire/device.c index 7af97362b95c..fa50c48292ff 100644 --- a/trunk/arch/m68k/platform/coldfire/device.c +++ b/trunk/arch/m68k/platform/coldfire/device.c @@ -114,7 +114,7 @@ static struct resource mcf_fec1_resources[] = { static struct platform_device mcf_fec1 = { .name = "fec", - .id = 1, + .id = 0, .num_resources = ARRAY_SIZE(mcf_fec1_resources), .resource = mcf_fec1_resources, }; diff --git a/trunk/arch/s390/Kconfig b/trunk/arch/s390/Kconfig index 9015060919a0..2b7c0fbe578e 100644 --- a/trunk/arch/s390/Kconfig +++ b/trunk/arch/s390/Kconfig @@ -90,6 +90,7 @@ config S390 select HAVE_KERNEL_XZ select HAVE_ARCH_MUTEX_CPU_RELAX select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 + select HAVE_RCU_TABLE_FREE if SMP select ARCH_SAVE_PAGE_KEYS if HIBERNATION select HAVE_MEMBLOCK select HAVE_MEMBLOCK_NODE_MAP diff --git a/trunk/arch/s390/defconfig b/trunk/arch/s390/defconfig index 1957a9dd256d..6cf8e26b3137 100644 --- a/trunk/arch/s390/defconfig +++ b/trunk/arch/s390/defconfig @@ -1,12 +1,8 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -CONFIG_FHANDLE=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y +CONFIG_RCU_TRACE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUPS=y @@ -18,22 +14,16 @@ CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y CONFIG_CGROUP_SCHED=y CONFIG_RT_GROUP_SCHED=y CONFIG_BLK_CGROUP=y -CONFIG_NAMESPACES=y CONFIG_BLK_DEV_INITRD=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_EXPERT=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set # CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y CONFIG_PROFILING=y CONFIG_OPROFILE=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_IBM_PARTITION=y CONFIG_DEFAULT_DEADLINE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -44,15 +34,18 @@ CONFIG_KSM=y CONFIG_BINFMT_MISC=m CONFIG_CMM=m CONFIG_HZ_100=y -CONFIG_CRASH_DUMP=y +CONFIG_KEXEC=y +CONFIG_PM=y CONFIG_HIBERNATION=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_NET_KEY=y +CONFIG_AFIUCV=m CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_INET_LRO is not set CONFIG_IPV6=y +CONFIG_NET_SCTPPROBE=m CONFIG_L2TP=m CONFIG_L2TP_DEBUGFS=m CONFIG_VLAN_8021Q=y @@ -91,14 +84,15 @@ CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y CONFIG_SCSI_SCAN_ASYNC=y CONFIG_ZFCP=y +CONFIG_ZFCP_DIF=y CONFIG_NETDEVICES=y -CONFIG_BONDING=m CONFIG_DUMMY=m +CONFIG_BONDING=m CONFIG_EQUALIZER=m CONFIG_TUN=m +CONFIG_NET_ETHERNET=y CONFIG_VIRTIO_NET=y CONFIG_RAW_DRIVER=m -CONFIG_VIRTIO_BALLOON=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set @@ -109,21 +103,27 @@ CONFIG_PROC_KCORE=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_PARTITION_ADVANCED=y +CONFIG_IBM_PARTITION=y +CONFIG_DLM=m CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y CONFIG_TIMER_STATS=y CONFIG_PROVE_LOCKING=y CONFIG_PROVE_RCU=y CONFIG_LOCK_STAT=y CONFIG_DEBUG_LOCKDEP=y +CONFIG_DEBUG_SPINLOCK_SLEEP=y CONFIG_DEBUG_LIST=y CONFIG_DEBUG_NOTIFIERS=y -CONFIG_RCU_TRACE=y +# CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_KPROBES_SANITY_TEST=y CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y CONFIG_CPU_NOTIFIER_ERROR_INJECT=m CONFIG_LATENCYTOP=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_DEBUG_PAGEALLOC=y -CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE is not set # CONFIG_STRICT_DEVMEM is not set CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_CRYPTD=m @@ -173,3 +173,4 @@ CONFIG_CRYPTO_SHA512_S390=m CONFIG_CRYPTO_DES_S390=m CONFIG_CRYPTO_AES_S390=m CONFIG_CRC7=m +CONFIG_VIRTIO_BALLOON=y diff --git a/trunk/arch/s390/include/asm/facility.h b/trunk/arch/s390/include/asm/facility.h index 2ee66a65f2d4..1e5b27edc0c9 100644 --- a/trunk/arch/s390/include/asm/facility.h +++ b/trunk/arch/s390/include/asm/facility.h @@ -38,11 +38,12 @@ static inline void stfle(u64 *stfle_fac_list, int size) unsigned long nr; preempt_disable(); + S390_lowcore.stfl_fac_list = 0; asm volatile( " .insn s,0xb2b10000,0(0)\n" /* stfl */ "0:\n" EX_TABLE(0b, 0b) - : "+m" (S390_lowcore.stfl_fac_list)); + : "=m" (S390_lowcore.stfl_fac_list)); nr = 4; /* bytes stored by stfl */ memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4); if (S390_lowcore.stfl_fac_list & 0x01000000) { diff --git a/trunk/arch/s390/include/asm/pgalloc.h b/trunk/arch/s390/include/asm/pgalloc.h index 78e3041919de..8eef9b5b3cf4 100644 --- a/trunk/arch/s390/include/asm/pgalloc.h +++ b/trunk/arch/s390/include/asm/pgalloc.h @@ -22,7 +22,10 @@ void crst_table_free(struct mm_struct *, unsigned long *); unsigned long *page_table_alloc(struct mm_struct *, unsigned long); void page_table_free(struct mm_struct *, unsigned long *); +#ifdef CONFIG_HAVE_RCU_TABLE_FREE void page_table_free_rcu(struct mmu_gather *, unsigned long *); +void __tlb_remove_table(void *_table); +#endif static inline void clear_table(unsigned long *s, unsigned long val, size_t n) { diff --git a/trunk/arch/s390/include/asm/swab.h b/trunk/arch/s390/include/asm/swab.h index a3e4ebb32090..6bdee21c077e 100644 --- a/trunk/arch/s390/include/asm/swab.h +++ b/trunk/arch/s390/include/asm/swab.h @@ -77,7 +77,7 @@ static inline __u16 __arch_swab16p(const __u16 *x) asm volatile( #ifndef __s390x__ - " icm %0,2,%O1+1(%R1)\n" + " icm %0,2,%O+1(%R1)\n" " ic %0,%1\n" : "=&d" (result) : "Q" (*x) : "cc"); #else /* __s390x__ */ diff --git a/trunk/arch/s390/include/asm/tlb.h b/trunk/arch/s390/include/asm/tlb.h index 775a5eea8f9e..c687a2c83462 100644 --- a/trunk/arch/s390/include/asm/tlb.h +++ b/trunk/arch/s390/include/asm/tlb.h @@ -30,10 +30,14 @@ struct mmu_gather { struct mm_struct *mm; +#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch *batch; +#endif unsigned int fullmm; + unsigned int need_flush; }; +#ifdef CONFIG_HAVE_RCU_TABLE_FREE struct mmu_table_batch { struct rcu_head rcu; unsigned int nr; @@ -45,6 +49,7 @@ struct mmu_table_batch { extern void tlb_table_flush(struct mmu_gather *tlb); extern void tlb_remove_table(struct mmu_gather *tlb, void *table); +#endif static inline void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, @@ -52,20 +57,29 @@ static inline void tlb_gather_mmu(struct mmu_gather *tlb, { tlb->mm = mm; tlb->fullmm = full_mm_flush; + tlb->need_flush = 0; +#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb->batch = NULL; +#endif if (tlb->fullmm) __tlb_flush_mm(mm); } static inline void tlb_flush_mmu(struct mmu_gather *tlb) { + if (!tlb->need_flush) + return; + tlb->need_flush = 0; + __tlb_flush_mm(tlb->mm); +#ifdef CONFIG_HAVE_RCU_TABLE_FREE tlb_table_flush(tlb); +#endif } static inline void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) { - tlb_table_flush(tlb); + tlb_flush_mmu(tlb); } /* @@ -91,8 +105,10 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page) static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long address) { +#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return page_table_free_rcu(tlb, (unsigned long *) pte); +#endif page_table_free(tlb->mm, (unsigned long *) pte); } @@ -109,8 +125,10 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 31)) return; +#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pmd); +#endif crst_table_free(tlb->mm, (unsigned long *) pmd); #endif } @@ -128,8 +146,10 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud, #ifdef __s390x__ if (tlb->mm->context.asce_limit <= (1UL << 42)) return; +#ifdef CONFIG_HAVE_RCU_TABLE_FREE if (!tlb->fullmm) return tlb_remove_table(tlb, pud); +#endif crst_table_free(tlb->mm, (unsigned long *) pud); #endif } diff --git a/trunk/arch/s390/kernel/head.S b/trunk/arch/s390/kernel/head.S index adccd908ebc7..c27a0727f930 100644 --- a/trunk/arch/s390/kernel/head.S +++ b/trunk/arch/s390/kernel/head.S @@ -474,9 +474,9 @@ ENTRY(startup_kdump) stck __LC_LAST_UPDATE_CLOCK spt 5f-.LPG0(%r13) mvc __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13) - xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST #ifndef CONFIG_MARCH_G5 # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10} + xc __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST .insn s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list tm __LC_STFL_FAC_LIST,0x01 # stfle available ? jz 0f diff --git a/trunk/arch/s390/kernel/irq.c b/trunk/arch/s390/kernel/irq.c index 8a22c27219dd..1c2cdd59ccd0 100644 --- a/trunk/arch/s390/kernel/irq.c +++ b/trunk/arch/s390/kernel/irq.c @@ -118,10 +118,9 @@ asmlinkage void do_softirq(void) "a" (__do_softirq) : "0", "1", "2", "3", "4", "5", "14", "cc", "memory" ); - } else { + } else /* We are already on the async stack. */ __do_softirq(); - } } local_irq_restore(flags); @@ -193,12 +192,11 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler) int index = ext_hash(code); spin_lock_irqsave(&ext_int_hash_lock, flags); - list_for_each_entry_rcu(p, &ext_int_hash[index], entry) { + list_for_each_entry_rcu(p, &ext_int_hash[index], entry) if (p->code == code && p->handler == handler) { list_del_rcu(&p->entry); kfree_rcu(p, rcu); } - } spin_unlock_irqrestore(&ext_int_hash_lock, flags); return 0; } @@ -213,10 +211,9 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code, old_regs = set_irq_regs(regs); irq_enter(); - if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) { + if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) /* Serve timer interrupts first. */ clock_comparator_work(); - } kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++; if (ext_code.code != 0x1004) __get_cpu_var(s390_idle).nohz_delay = 1; diff --git a/trunk/arch/s390/kernel/perf_cpum_cf.c b/trunk/arch/s390/kernel/perf_cpum_cf.c index cb019f429e88..46405086479c 100644 --- a/trunk/arch/s390/kernel/perf_cpum_cf.c +++ b/trunk/arch/s390/kernel/perf_cpum_cf.c @@ -178,7 +178,7 @@ static void cpumf_pmu_enable(struct pmu *pmu) err = lcctl(cpuhw->state); if (err) { pr_err("Enabling the performance measuring unit " - "failed with rc=%x\n", err); + "failed with rc=%lx\n", err); return; } @@ -203,7 +203,7 @@ static void cpumf_pmu_disable(struct pmu *pmu) err = lcctl(inactive); if (err) { pr_err("Disabling the performance measuring unit " - "failed with rc=%x\n", err); + "failed with rc=%lx\n", err); return; } diff --git a/trunk/arch/s390/mm/maccess.c b/trunk/arch/s390/mm/maccess.c index e1335dc2b1b7..7bb15fcca75e 100644 --- a/trunk/arch/s390/mm/maccess.c +++ b/trunk/arch/s390/mm/maccess.c @@ -61,14 +61,21 @@ long probe_kernel_write(void *dst, const void *src, size_t size) return copied < 0 ? -EFAULT : 0; } -static int __memcpy_real(void *dest, void *src, size_t count) +/* + * Copy memory in real mode (kernel to kernel) + */ +int memcpy_real(void *dest, void *src, size_t count) { register unsigned long _dest asm("2") = (unsigned long) dest; register unsigned long _len1 asm("3") = (unsigned long) count; register unsigned long _src asm("4") = (unsigned long) src; register unsigned long _len2 asm("5") = (unsigned long) count; + unsigned long flags; int rc = -EFAULT; + if (!count) + return 0; + flags = __arch_local_irq_stnsm(0xf8UL); asm volatile ( "0: mvcle %1,%2,0x0\n" "1: jo 0b\n" @@ -79,23 +86,7 @@ static int __memcpy_real(void *dest, void *src, size_t count) "+d" (_len2), "=m" (*((long *) dest)) : "m" (*((long *) src)) : "cc", "memory"); - return rc; -} - -/* - * Copy memory in real mode (kernel to kernel) - */ -int memcpy_real(void *dest, void *src, size_t count) -{ - unsigned long flags; - int rc; - - if (!count) - return 0; - local_irq_save(flags); - __arch_local_irq_stnsm(0xfbUL); - rc = __memcpy_real(dest, src, count); - local_irq_restore(flags); + arch_local_irq_restore(flags); return rc; } diff --git a/trunk/arch/s390/mm/pgtable.c b/trunk/arch/s390/mm/pgtable.c index 6e765bf00670..373adf69b01c 100644 --- a/trunk/arch/s390/mm/pgtable.c +++ b/trunk/arch/s390/mm/pgtable.c @@ -678,6 +678,8 @@ void page_table_free(struct mm_struct *mm, unsigned long *table) } } +#ifdef CONFIG_HAVE_RCU_TABLE_FREE + static void __page_table_free_rcu(void *table, unsigned bit) { struct page *page; @@ -731,66 +733,7 @@ void __tlb_remove_table(void *_table) free_pages((unsigned long) table, ALLOC_ORDER); } -static void tlb_remove_table_smp_sync(void *arg) -{ - /* Simply deliver the interrupt */ -} - -static void tlb_remove_table_one(void *table) -{ - /* - * This isn't an RCU grace period and hence the page-tables cannot be - * assumed to be actually RCU-freed. - * - * It is however sufficient for software page-table walkers that rely - * on IRQ disabling. See the comment near struct mmu_table_batch. - */ - smp_call_function(tlb_remove_table_smp_sync, NULL, 1); - __tlb_remove_table(table); -} - -static void tlb_remove_table_rcu(struct rcu_head *head) -{ - struct mmu_table_batch *batch; - int i; - - batch = container_of(head, struct mmu_table_batch, rcu); - - for (i = 0; i < batch->nr; i++) - __tlb_remove_table(batch->tables[i]); - - free_page((unsigned long)batch); -} - -void tlb_table_flush(struct mmu_gather *tlb) -{ - struct mmu_table_batch **batch = &tlb->batch; - - if (*batch) { - __tlb_flush_mm(tlb->mm); - call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu); - *batch = NULL; - } -} - -void tlb_remove_table(struct mmu_gather *tlb, void *table) -{ - struct mmu_table_batch **batch = &tlb->batch; - - if (*batch == NULL) { - *batch = (struct mmu_table_batch *) - __get_free_page(GFP_NOWAIT | __GFP_NOWARN); - if (*batch == NULL) { - __tlb_flush_mm(tlb->mm); - tlb_remove_table_one(table); - return; - } - (*batch)->nr = 0; - } - (*batch)->tables[(*batch)->nr++] = table; - if ((*batch)->nr == MAX_TABLE_BATCH) - tlb_table_flush(tlb); -} +#endif /* * switch on pgstes for its userspace process (for kvm) diff --git a/trunk/arch/sparc/kernel/leon_smp.c b/trunk/arch/sparc/kernel/leon_smp.c index 160cac9c4036..1210fde18740 100644 --- a/trunk/arch/sparc/kernel/leon_smp.c +++ b/trunk/arch/sparc/kernel/leon_smp.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -79,8 +78,6 @@ void __cpuinit leon_callin(void) local_flush_tlb_all(); leon_configure_cache_smp(); - notify_cpu_starting(cpuid); - /* Get our local ticker going. */ smp_setup_percpu_timer(); diff --git a/trunk/arch/sparc/kernel/sys_sparc_64.c b/trunk/arch/sparc/kernel/sys_sparc_64.c index 3ee51f189a55..232df9949530 100644 --- a/trunk/arch/sparc/kernel/sys_sparc_64.c +++ b/trunk/arch/sparc/kernel/sys_sparc_64.c @@ -566,10 +566,15 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len) { + long ret; + if (invalid_64bit_range(addr, len)) return -EINVAL; - return vm_munmap(addr, len); + down_write(¤t->mm->mmap_sem); + ret = do_munmap(current->mm, addr, len); + up_write(¤t->mm->mmap_sem); + return ret; } extern unsigned long do_mremap(unsigned long addr, diff --git a/trunk/arch/tile/kernel/single_step.c b/trunk/arch/tile/kernel/single_step.c index 89529c9f0605..9efbc1391b3c 100644 --- a/trunk/arch/tile/kernel/single_step.c +++ b/trunk/arch/tile/kernel/single_step.c @@ -346,10 +346,12 @@ void single_step_once(struct pt_regs *regs) } /* allocate a cache line of writable, executable memory */ - buffer = (void __user *) vm_mmap(NULL, 0, 64, + down_write(¤t->mm->mmap_sem); + buffer = (void __user *) do_mmap(NULL, 0, 64, PROT_EXEC | PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, 0); + up_write(¤t->mm->mmap_sem); if (IS_ERR((void __force *)buffer)) { kfree(state); diff --git a/trunk/arch/x86/ia32/ia32_aout.c b/trunk/arch/x86/ia32/ia32_aout.c index 4824fb45560f..d511d951a052 100644 --- a/trunk/arch/x86/ia32/ia32_aout.c +++ b/trunk/arch/x86/ia32/ia32_aout.c @@ -119,7 +119,9 @@ static void set_brk(unsigned long start, unsigned long end) end = PAGE_ALIGN(end); if (end <= start) return; - vm_brk(start, end - start); + down_write(¤t->mm->mmap_sem); + do_brk(start, end - start); + up_write(¤t->mm->mmap_sem); } #ifdef CORE_DUMP @@ -330,7 +332,9 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) pos = 32; map_size = ex.a_text+ex.a_data; - error = vm_brk(text_addr & PAGE_MASK, map_size); + down_write(¤t->mm->mmap_sem); + error = do_brk(text_addr & PAGE_MASK, map_size); + up_write(¤t->mm->mmap_sem); if (error != (text_addr & PAGE_MASK)) { send_sig(SIGKILL, current, 0); @@ -369,7 +373,9 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) { loff_t pos = fd_offset; - vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); + down_write(¤t->mm->mmap_sem); + do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); + up_write(¤t->mm->mmap_sem); bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex), ex.a_text+ex.a_data, &pos); @@ -379,22 +385,26 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs) goto beyond_if; } - error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, + down_write(¤t->mm->mmap_sem); + error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset); + up_write(¤t->mm->mmap_sem); if (error != N_TXTADDR(ex)) { send_sig(SIGKILL, current, 0); return error; } - error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data, + down_write(¤t->mm->mmap_sem); + error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE | MAP_32BIT, fd_offset + ex.a_text); + up_write(¤t->mm->mmap_sem); if (error != N_DATADDR(ex)) { send_sig(SIGKILL, current, 0); return error; @@ -466,7 +476,9 @@ static int load_aout_library(struct file *file) error_time = jiffies; } #endif - vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); + down_write(¤t->mm->mmap_sem); + do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); + up_write(¤t->mm->mmap_sem); file->f_op->read(file, (char __user *)start_addr, ex.a_text + ex.a_data, &pos); @@ -478,10 +490,12 @@ static int load_aout_library(struct file *file) goto out; } /* Now use mmap to map the library into memory. */ - error = vm_mmap(file, start_addr, ex.a_text + ex.a_data, + down_write(¤t->mm->mmap_sem); + error = do_mmap(file, start_addr, ex.a_text + ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_32BIT, N_TXTOFF(ex)); + up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr) goto out; @@ -489,7 +503,9 @@ static int load_aout_library(struct file *file) len = PAGE_ALIGN(ex.a_text + ex.a_data); bss = ex.a_text + ex.a_data + ex.a_bss; if (bss > len) { - error = vm_brk(start_addr + len, bss - len); + down_write(¤t->mm->mmap_sem); + error = do_brk(start_addr + len, bss - len); + up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr + len) goto out; diff --git a/trunk/arch/x86/kvm/pmu.c b/trunk/arch/x86/kvm/pmu.c index 2e88438ffd83..173df38dbda5 100644 --- a/trunk/arch/x86/kvm/pmu.c +++ b/trunk/arch/x86/kvm/pmu.c @@ -459,17 +459,17 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu) pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1); if (pmu->version == 1) { - pmu->nr_arch_fixed_counters = 0; - } else { - pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), - X86_PMC_MAX_FIXED); - pmu->counter_bitmask[KVM_PMC_FIXED] = - ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; + pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1; + return; } - pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | - (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED); - pmu->global_ctrl_mask = ~pmu->global_ctrl; + pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), + X86_PMC_MAX_FIXED); + pmu->counter_bitmask[KVM_PMC_FIXED] = + ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; + pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1) + | (((1ull << pmu->nr_arch_fixed_counters) - 1) + << X86_PMC_IDX_FIXED)); } void kvm_pmu_init(struct kvm_vcpu *vcpu) diff --git a/trunk/arch/x86/kvm/vmx.c b/trunk/arch/x86/kvm/vmx.c index 4ff0ab9bc3c8..ad85adfef843 100644 --- a/trunk/arch/x86/kvm/vmx.c +++ b/trunk/arch/x86/kvm/vmx.c @@ -2210,12 +2210,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) msr = find_msr_entry(vmx, msr_index); if (msr) { msr->data = data; - if (msr - vmx->guest_msrs < vmx->save_nmsrs) { - preempt_disable(); + if (msr - vmx->guest_msrs < vmx->save_nmsrs) kvm_set_shared_msr(msr->index, msr->data, msr->mask); - preempt_enable(); - } break; } ret = kvm_set_msr_common(vcpu, msr_index, data); diff --git a/trunk/arch/x86/kvm/x86.c b/trunk/arch/x86/kvm/x86.c index 91a5e989abcf..4044ce0bf7c1 100644 --- a/trunk/arch/x86/kvm/x86.c +++ b/trunk/arch/x86/kvm/x86.c @@ -6336,11 +6336,13 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, if (npages && !old.rmap) { unsigned long userspace_addr; - userspace_addr = vm_mmap(NULL, 0, + down_write(¤t->mm->mmap_sem); + userspace_addr = do_mmap(NULL, 0, npages * PAGE_SIZE, PROT_READ | PROT_WRITE, map_flags, 0); + up_write(¤t->mm->mmap_sem); if (IS_ERR((void *)userspace_addr)) return PTR_ERR((void *)userspace_addr); @@ -6364,8 +6366,10 @@ void kvm_arch_commit_memory_region(struct kvm *kvm, if (!user_alloc && !old.user_alloc && old.rmap && !npages) { int ret; - ret = vm_munmap(old.userspace_addr, + down_write(¤t->mm->mmap_sem); + ret = do_munmap(current->mm, old.userspace_addr, old.npages * PAGE_SIZE); + up_write(¤t->mm->mmap_sem); if (ret < 0) printk(KERN_WARNING "kvm_vm_ioctl_set_memory_region: " diff --git a/trunk/arch/x86/lib/insn.c b/trunk/arch/x86/lib/insn.c index b1e6c4b2e8eb..25feb1ae71c5 100644 --- a/trunk/arch/x86/lib/insn.c +++ b/trunk/arch/x86/lib/insn.c @@ -379,8 +379,8 @@ void insn_get_displacement(struct insn *insn) return; } -/* Decode moffset16/32/64. Return 0 if failed */ -static int __get_moffset(struct insn *insn) +/* Decode moffset16/32/64 */ +static void __get_moffset(struct insn *insn) { switch (insn->addr_bytes) { case 2: @@ -397,19 +397,15 @@ static int __get_moffset(struct insn *insn) insn->moffset2.value = get_next(int, insn); insn->moffset2.nbytes = 4; break; - default: /* opnd_bytes must be modified manually */ - goto err_out; } insn->moffset1.got = insn->moffset2.got = 1; - return 1; - err_out: - return 0; + return; } -/* Decode imm v32(Iz). Return 0 if failed */ -static int __get_immv32(struct insn *insn) +/* Decode imm v32(Iz) */ +static void __get_immv32(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -421,18 +417,14 @@ static int __get_immv32(struct insn *insn) insn->immediate.value = get_next(int, insn); insn->immediate.nbytes = 4; break; - default: /* opnd_bytes must be modified manually */ - goto err_out; } - return 1; - err_out: - return 0; + return; } -/* Decode imm v64(Iv/Ov), Return 0 if failed */ -static int __get_immv(struct insn *insn) +/* Decode imm v64(Iv/Ov) */ +static void __get_immv(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -449,18 +441,15 @@ static int __get_immv(struct insn *insn) insn->immediate2.value = get_next(int, insn); insn->immediate2.nbytes = 4; break; - default: /* opnd_bytes must be modified manually */ - goto err_out; } insn->immediate1.got = insn->immediate2.got = 1; - return 1; err_out: - return 0; + return; } /* Decode ptr16:16/32(Ap) */ -static int __get_immptr(struct insn *insn) +static void __get_immptr(struct insn *insn) { switch (insn->opnd_bytes) { case 2: @@ -473,17 +462,14 @@ static int __get_immptr(struct insn *insn) break; case 8: /* ptr16:64 is not exist (no segment) */ - return 0; - default: /* opnd_bytes must be modified manually */ - goto err_out; + return; } insn->immediate2.value = get_next(unsigned short, insn); insn->immediate2.nbytes = 2; insn->immediate1.got = insn->immediate2.got = 1; - return 1; err_out: - return 0; + return; } /** @@ -503,8 +489,7 @@ void insn_get_immediate(struct insn *insn) insn_get_displacement(insn); if (inat_has_moffset(insn->attr)) { - if (!__get_moffset(insn)) - goto err_out; + __get_moffset(insn); goto done; } @@ -532,20 +517,16 @@ void insn_get_immediate(struct insn *insn) insn->immediate2.nbytes = 4; break; case INAT_IMM_PTR: - if (!__get_immptr(insn)) - goto err_out; + __get_immptr(insn); break; case INAT_IMM_VWORD32: - if (!__get_immv32(insn)) - goto err_out; + __get_immv32(insn); break; case INAT_IMM_VWORD: - if (!__get_immv(insn)) - goto err_out; + __get_immv(insn); break; default: - /* Here, insn must have an immediate, but failed */ - goto err_out; + break; } if (inat_has_second_immediate(insn->attr)) { insn->immediate2.value = get_next(char, insn); diff --git a/trunk/crypto/sha512_generic.c b/trunk/crypto/sha512_generic.c index dd30f40af9f5..107f6f7be5e1 100644 --- a/trunk/crypto/sha512_generic.c +++ b/trunk/crypto/sha512_generic.c @@ -174,7 +174,7 @@ sha512_update(struct shash_desc *desc, const u8 *data, unsigned int len) index = sctx->count[0] & 0x7f; /* Update number of bytes */ - if ((sctx->count[0] += len) < len) + if (!(sctx->count[0] += len)) sctx->count[1]++; part_len = 128 - index; diff --git a/trunk/drivers/acpi/acpica/hwxface.c b/trunk/drivers/acpi/acpica/hwxface.c index a716fede4f25..ab513a972c95 100644 --- a/trunk/drivers/acpi/acpica/hwxface.c +++ b/trunk/drivers/acpi/acpica/hwxface.c @@ -74,8 +74,7 @@ acpi_status acpi_reset(void) /* Check if the reset register is supported */ - if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER) || - !reset_reg->address) { + if (!reset_reg->address) { return_ACPI_STATUS(AE_NOT_EXIST); } diff --git a/trunk/drivers/acpi/osl.c b/trunk/drivers/acpi/osl.c index c3881b2eb8b2..ba14fb93c929 100644 --- a/trunk/drivers/acpi/osl.c +++ b/trunk/drivers/acpi/osl.c @@ -607,7 +607,8 @@ acpi_os_install_interrupt_handler(u32 gsi, acpi_osd_handler handler, acpi_irq_handler = handler; acpi_irq_context = context; - if (request_irq(irq, acpi_irq, IRQF_SHARED, "acpi", acpi_irq)) { + if (request_threaded_irq(irq, NULL, acpi_irq, IRQF_SHARED, "acpi", + acpi_irq)) { printk(KERN_ERR PREFIX "SCI (IRQ%d) allocation failed\n", irq); acpi_irq_handler = NULL; return AE_NOT_ACQUIRED; diff --git a/trunk/drivers/acpi/reboot.c b/trunk/drivers/acpi/reboot.c index a6c77e8b37bd..c1d612435939 100644 --- a/trunk/drivers/acpi/reboot.c +++ b/trunk/drivers/acpi/reboot.c @@ -23,8 +23,7 @@ void acpi_reboot(void) /* Is the reset register supported? The spec says we should be * checking the bit width and bit offset, but Windows ignores * these fields */ - if (!(acpi_gbl_FADT.flags & ACPI_FADT_RESET_REGISTER)) - return; + /* Ignore also acpi_gbl_FADT.flags.ACPI_FADT_RESET_REGISTER */ reset_value = acpi_gbl_FADT.reset_value; diff --git a/trunk/drivers/ata/ata_piix.c b/trunk/drivers/ata/ata_piix.c index 7857e8fd0a3e..68013f96729f 100644 --- a/trunk/drivers/ata/ata_piix.c +++ b/trunk/drivers/ata/ata_piix.c @@ -329,8 +329,6 @@ static const struct pci_device_id piix_pci_tbl[] = { { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (Lynx Point) */ { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, - /* SATA Controller IDE (DH89xxCC) */ - { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, { } /* terminate list */ }; diff --git a/trunk/drivers/ata/libata-core.c b/trunk/drivers/ata/libata-core.c index 28db50b57b91..e0bda9ff89cd 100644 --- a/trunk/drivers/ata/libata-core.c +++ b/trunk/drivers/ata/libata-core.c @@ -95,7 +95,7 @@ static unsigned int ata_dev_set_xfermode(struct ata_device *dev); static void ata_dev_xfermask(struct ata_device *dev); static unsigned long ata_dev_blacklisted(const struct ata_device *dev); -atomic_t ata_print_id = ATOMIC_INIT(1); +unsigned int ata_print_id = 1; struct ata_force_param { const char *name; @@ -6029,7 +6029,7 @@ int ata_host_register(struct ata_host *host, struct scsi_host_template *sht) /* give ports names and add SCSI hosts */ for (i = 0; i < host->n_ports; i++) - host->ports[i]->print_id = atomic_inc_return(&ata_print_id); + host->ports[i]->print_id = ata_print_id++; /* Create associated sysfs transport objects */ diff --git a/trunk/drivers/ata/libata-scsi.c b/trunk/drivers/ata/libata-scsi.c index 93dabdcd2cbe..1ee00c8b5b04 100644 --- a/trunk/drivers/ata/libata-scsi.c +++ b/trunk/drivers/ata/libata-scsi.c @@ -3843,7 +3843,7 @@ int ata_sas_async_port_init(struct ata_port *ap) int rc = ap->ops->port_start(ap); if (!rc) { - ap->print_id = atomic_inc_return(&ata_print_id); + ap->print_id = ata_print_id++; __ata_port_probe(ap); } @@ -3867,7 +3867,7 @@ int ata_sas_port_init(struct ata_port *ap) int rc = ap->ops->port_start(ap); if (!rc) { - ap->print_id = atomic_inc_return(&ata_print_id); + ap->print_id = ata_print_id++; rc = ata_port_probe(ap); } diff --git a/trunk/drivers/ata/libata-transport.c b/trunk/drivers/ata/libata-transport.c index c34190485377..74aaee30e264 100644 --- a/trunk/drivers/ata/libata-transport.c +++ b/trunk/drivers/ata/libata-transport.c @@ -294,7 +294,6 @@ int ata_tport_add(struct device *parent, device_enable_async_suspend(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); - pm_runtime_forbid(dev); transport_add_device(dev); transport_configure_device(dev); diff --git a/trunk/drivers/ata/libata.h b/trunk/drivers/ata/libata.h index 9d0fd0b71852..2e26fcaf635b 100644 --- a/trunk/drivers/ata/libata.h +++ b/trunk/drivers/ata/libata.h @@ -53,7 +53,7 @@ enum { ATA_DNXFER_QUIET = (1 << 31), }; -extern atomic_t ata_print_id; +extern unsigned int ata_print_id; extern int atapi_passthru16; extern int libata_fua; extern int libata_noacpi; diff --git a/trunk/drivers/ata/sata_mv.c b/trunk/drivers/ata/sata_mv.c index 7336d4a7ab31..38950ea8398a 100644 --- a/trunk/drivers/ata/sata_mv.c +++ b/trunk/drivers/ata/sata_mv.c @@ -4025,8 +4025,7 @@ static int mv_platform_probe(struct platform_device *pdev) struct ata_host *host; struct mv_host_priv *hpriv; struct resource *res; - int n_ports = 0; - int rc; + int n_ports, rc; ata_print_version_once(&pdev->dev, DRV_VERSION); diff --git a/trunk/drivers/block/virtio_blk.c b/trunk/drivers/block/virtio_blk.c index 0d39f2f4294a..0e4ef3de9d5d 100644 --- a/trunk/drivers/block/virtio_blk.c +++ b/trunk/drivers/block/virtio_blk.c @@ -375,34 +375,6 @@ static int init_vq(struct virtio_blk *vblk) return err; } -/* - * Legacy naming scheme used for virtio devices. We are stuck with it for - * virtio blk but don't ever use it for any new driver. - */ -static int virtblk_name_format(char *prefix, int index, char *buf, int buflen) -{ - const int base = 'z' - 'a' + 1; - char *begin = buf + strlen(prefix); - char *end = buf + buflen; - char *p; - int unit; - - p = end - 1; - *p = '\0'; - unit = base; - do { - if (p == begin) - return -EINVAL; - *--p = 'a' + (index % unit); - index = (index / unit) - 1; - } while (index >= 0); - - memmove(begin, p, end - p); - memcpy(buf, prefix, strlen(prefix)); - - return 0; -} - static int __devinit virtblk_probe(struct virtio_device *vdev) { struct virtio_blk *vblk; @@ -471,7 +443,18 @@ static int __devinit virtblk_probe(struct virtio_device *vdev) q->queuedata = vblk; - virtblk_name_format("vd", index, vblk->disk->disk_name, DISK_NAME_LEN); + if (index < 26) { + sprintf(vblk->disk->disk_name, "vd%c", 'a' + index % 26); + } else if (index < (26 + 1) * 26) { + sprintf(vblk->disk->disk_name, "vd%c%c", + 'a' + index / 26 - 1, 'a' + index % 26); + } else { + const unsigned int m1 = (index / 26 - 1) / 26 - 1; + const unsigned int m2 = (index / 26 - 1) % 26; + const unsigned int m3 = index % 26; + sprintf(vblk->disk->disk_name, "vd%c%c%c", + 'a' + m1, 'a' + m2, 'a' + m3); + } vblk->disk->major = major; vblk->disk->first_minor = index_to_minor(index); diff --git a/trunk/drivers/block/xen-blkback/xenbus.c b/trunk/drivers/block/xen-blkback/xenbus.c index 4f66171c6683..89860f34a7ec 100644 --- a/trunk/drivers/block/xen-blkback/xenbus.c +++ b/trunk/drivers/block/xen-blkback/xenbus.c @@ -416,7 +416,7 @@ static void xen_blkbk_discard(struct xenbus_transaction xbt, struct backend_info "discard-secure", "%d", blkif->vbd.discard_secure); if (err) { - dev_warn(&dev->dev, "writing discard-secure (%d)", err); + dev_warn(dev-dev, "writing discard-secure (%d)", err); return; } } diff --git a/trunk/drivers/clk/Kconfig b/trunk/drivers/clk/Kconfig index 4864407e3fc4..165e1febae53 100644 --- a/trunk/drivers/clk/Kconfig +++ b/trunk/drivers/clk/Kconfig @@ -12,7 +12,6 @@ config HAVE_MACH_CLKDEV config COMMON_CLK bool select HAVE_CLK_PREPARE - select CLKDEV_LOOKUP ---help--- The common clock framework is a single definition of struct clk, useful across many platforms, as well as an @@ -23,6 +22,17 @@ config COMMON_CLK menu "Common Clock Framework" depends on COMMON_CLK +config COMMON_CLK_DISABLE_UNUSED + bool "Disabled unused clocks at boot" + depends on COMMON_CLK + ---help--- + Traverses the entire clock tree and disables any clocks that are + enabled in hardware but have not been enabled by any device drivers. + This saves power and keeps the software model of the clock in line + with reality. + + If in doubt, say "N". + config COMMON_CLK_DEBUG bool "DebugFS representation of clock tree" depends on COMMON_CLK diff --git a/trunk/drivers/clk/Makefile b/trunk/drivers/clk/Makefile index 0f5e03d1ef5c..1f736bc11c4b 100644 --- a/trunk/drivers/clk/Makefile +++ b/trunk/drivers/clk/Makefile @@ -1,7 +1,4 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ - clk-mux.o clk-divider.o clk-fixed-factor.o - -# SoCs specific -obj-$(CONFIG_PLAT_SPEAR) += spear/ + clk-mux.o clk-divider.o diff --git a/trunk/drivers/clk/clk-divider.c b/trunk/drivers/clk/clk-divider.c index 8ea11b444528..d5ac6a75ea57 100644 --- a/trunk/drivers/clk/clk-divider.c +++ b/trunk/drivers/clk/clk-divider.c @@ -45,6 +45,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, return parent_rate / div; } +EXPORT_SYMBOL_GPL(clk_divider_recalc_rate); /* * The reverse of DIV_ROUND_UP: The maximum number which @@ -67,8 +68,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, if (divider->flags & CLK_DIVIDER_ONE_BASED) maxdiv--; - if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) { - parent_rate = *best_parent_rate; + if (!best_parent_rate) { + parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); bestdiv = DIV_ROUND_UP(parent_rate, rate); bestdiv = bestdiv == 0 ? 1 : bestdiv; bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; @@ -108,18 +109,24 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, int div; div = clk_divider_bestdiv(hw, rate, prate); - return *prate / div; + if (prate) + return *prate / div; + else { + unsigned long r; + r = __clk_get_rate(__clk_get_parent(hw->clk)); + return r / div; + } } +EXPORT_SYMBOL_GPL(clk_divider_round_rate); -static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) +static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate) { struct clk_divider *divider = to_clk_divider(hw); unsigned int div; unsigned long flags = 0; u32 val; - div = parent_rate / rate; + div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate; if (!(divider->flags & CLK_DIVIDER_ONE_BASED)) div--; @@ -140,26 +147,15 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +EXPORT_SYMBOL_GPL(clk_divider_set_rate); -const struct clk_ops clk_divider_ops = { +struct clk_ops clk_divider_ops = { .recalc_rate = clk_divider_recalc_rate, .round_rate = clk_divider_round_rate, .set_rate = clk_divider_set_rate, }; EXPORT_SYMBOL_GPL(clk_divider_ops); -/** - * clk_register_divider - register a divider clock with the clock framework - * @dev: device registering this clock - * @name: name of this clock - * @parent_name: name of clock's parent - * @flags: framework-specific flags - * @reg: register address to adjust divider - * @shift: number of bits to shift the bitfield - * @width: width of the bitfield - * @clk_divider_flags: divider-specific flags for this clock - * @lock: shared register lock for this clock - */ struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, @@ -167,34 +163,38 @@ struct clk *clk_register_divider(struct device *dev, const char *name, { struct clk_divider *div; struct clk *clk; - struct clk_init_data init; - /* allocate the divider */ div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); + if (!div) { pr_err("%s: could not allocate divider clk\n", __func__); - return ERR_PTR(-ENOMEM); + return NULL; } - init.name = name; - init.ops = &clk_divider_ops; - init.flags = flags; - init.parent_names = (parent_name ? &parent_name: NULL); - init.num_parents = (parent_name ? 1 : 0); - /* struct clk_divider assignments */ div->reg = reg; div->shift = shift; div->width = width; div->flags = clk_divider_flags; div->lock = lock; - div->hw.init = &init; - /* register the clock */ - clk = clk_register(dev, &div->hw); + if (parent_name) { + div->parent[0] = kstrdup(parent_name, GFP_KERNEL); + if (!div->parent[0]) + goto out; + } + + clk = clk_register(dev, name, + &clk_divider_ops, &div->hw, + div->parent, + (parent_name ? 1 : 0), + flags); + if (clk) + return clk; - if (IS_ERR(clk)) - kfree(div); +out: + kfree(div->parent[0]); + kfree(div); - return clk; + return NULL; } diff --git a/trunk/drivers/clk/clk-fixed-factor.c b/trunk/drivers/clk/clk-fixed-factor.c deleted file mode 100644 index c8c003e217ad..000000000000 --- a/trunk/drivers/clk/clk-fixed-factor.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Standard functionality for the common clock API. - */ -#include -#include -#include -#include - -/* - * DOC: basic fixed multiplier and divider clock that cannot gate - * - * Traits of this clock: - * prepare - clk_prepare only ensures that parents are prepared - * enable - clk_enable only ensures that parents are enabled - * rate - rate is fixed. clk->rate = parent->rate / div * mult - * parent - fixed parent. No clk_set_parent support - */ - -#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) - -static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); - - return parent_rate * fix->mult / fix->div; -} - -static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); - - if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { - unsigned long best_parent; - - best_parent = (rate / fix->mult) * fix->div; - *prate = __clk_round_rate(__clk_get_parent(hw->clk), - best_parent); - } - - return (*prate / fix->div) * fix->mult; -} - -static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - return 0; -} - -struct clk_ops clk_fixed_factor_ops = { - .round_rate = clk_factor_round_rate, - .set_rate = clk_factor_set_rate, - .recalc_rate = clk_factor_recalc_rate, -}; -EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); - -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - unsigned int mult, unsigned int div) -{ - struct clk_fixed_factor *fix; - struct clk_init_data init; - struct clk *clk; - - fix = kmalloc(sizeof(*fix), GFP_KERNEL); - if (!fix) { - pr_err("%s: could not allocate fixed factor clk\n", __func__); - return ERR_PTR(-ENOMEM); - } - - /* struct clk_fixed_factor assignments */ - fix->mult = mult; - fix->div = div; - fix->hw.init = &init; - - init.name = name; - init.ops = &clk_fixed_factor_ops; - init.flags = flags; - init.parent_names = &parent_name; - init.num_parents = 1; - - clk = clk_register(dev, &fix->hw); - - if (IS_ERR(clk)) - kfree(fix); - - return clk; -} diff --git a/trunk/drivers/clk/clk-fixed-rate.c b/trunk/drivers/clk/clk-fixed-rate.c index cbd246229786..90c79fb5d1bd 100644 --- a/trunk/drivers/clk/clk-fixed-rate.c +++ b/trunk/drivers/clk/clk-fixed-rate.c @@ -32,50 +32,51 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, { return to_clk_fixed_rate(hw)->fixed_rate; } +EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate); -const struct clk_ops clk_fixed_rate_ops = { +struct clk_ops clk_fixed_rate_ops = { .recalc_rate = clk_fixed_rate_recalc_rate, }; EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); -/** - * clk_register_fixed_rate - register fixed-rate clock with the clock framework - * @dev: device that is registering this clock - * @name: name of this clock - * @parent_name: name of clock's parent - * @flags: framework-specific flags - * @fixed_rate: non-adjustable clock rate - */ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) { struct clk_fixed_rate *fixed; - struct clk *clk; - struct clk_init_data init; + char **parent_names = NULL; + u8 len; - /* allocate fixed-rate clock */ fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); + if (!fixed) { pr_err("%s: could not allocate fixed clk\n", __func__); return ERR_PTR(-ENOMEM); } - init.name = name; - init.ops = &clk_fixed_rate_ops; - init.flags = flags; - init.parent_names = (parent_name ? &parent_name: NULL); - init.num_parents = (parent_name ? 1 : 0); - /* struct clk_fixed_rate assignments */ fixed->fixed_rate = fixed_rate; - fixed->hw.init = &init; - /* register the clock */ - clk = clk_register(dev, &fixed->hw); + if (parent_name) { + parent_names = kmalloc(sizeof(char *), GFP_KERNEL); + + if (! parent_names) + goto out; - if (IS_ERR(clk)) - kfree(fixed); + len = sizeof(char) * strlen(parent_name); + + parent_names[0] = kmalloc(len, GFP_KERNEL); + + if (!parent_names[0]) + goto out; + + strncpy(parent_names[0], parent_name, len); + } - return clk; +out: + return clk_register(dev, name, + &clk_fixed_rate_ops, &fixed->hw, + parent_names, + (parent_name ? 1 : 0), + flags); } diff --git a/trunk/drivers/clk/clk-gate.c b/trunk/drivers/clk/clk-gate.c index 578465e04be6..b5902e2ef2fd 100644 --- a/trunk/drivers/clk/clk-gate.c +++ b/trunk/drivers/clk/clk-gate.c @@ -28,38 +28,32 @@ #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) -/* - * It works on following logic: - * - * For enabling clock, enable = 1 - * set2dis = 1 -> clear bit -> set = 0 - * set2dis = 0 -> set bit -> set = 1 - * - * For disabling clock, enable = 0 - * set2dis = 1 -> set bit -> set = 1 - * set2dis = 0 -> clear bit -> set = 0 - * - * So, result is always: enable xor set2dis. - */ -static void clk_gate_endisable(struct clk_hw *hw, int enable) +static void clk_gate_set_bit(struct clk_gate *gate) { - struct clk_gate *gate = to_clk_gate(hw); - int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; - unsigned long flags = 0; u32 reg; - - set ^= enable; + unsigned long flags = 0; if (gate->lock) spin_lock_irqsave(gate->lock, flags); reg = readl(gate->reg); + reg |= BIT(gate->bit_idx); + writel(reg, gate->reg); - if (set) - reg |= BIT(gate->bit_idx); - else - reg &= ~BIT(gate->bit_idx); + if (gate->lock) + spin_unlock_irqrestore(gate->lock, flags); +} + +static void clk_gate_clear_bit(struct clk_gate *gate) +{ + u32 reg; + unsigned long flags = 0; + if (gate->lock) + spin_lock_irqsave(gate->lock, flags); + + reg = readl(gate->reg); + reg &= ~BIT(gate->bit_idx); writel(reg, gate->reg); if (gate->lock) @@ -68,15 +62,27 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) static int clk_gate_enable(struct clk_hw *hw) { - clk_gate_endisable(hw, 1); + struct clk_gate *gate = to_clk_gate(hw); + + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + clk_gate_clear_bit(gate); + else + clk_gate_set_bit(gate); return 0; } +EXPORT_SYMBOL_GPL(clk_gate_enable); static void clk_gate_disable(struct clk_hw *hw) { - clk_gate_endisable(hw, 0); + struct clk_gate *gate = to_clk_gate(hw); + + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + clk_gate_set_bit(gate); + else + clk_gate_clear_bit(gate); } +EXPORT_SYMBOL_GPL(clk_gate_disable); static int clk_gate_is_enabled(struct clk_hw *hw) { @@ -93,25 +99,15 @@ static int clk_gate_is_enabled(struct clk_hw *hw) return reg ? 1 : 0; } +EXPORT_SYMBOL_GPL(clk_gate_is_enabled); -const struct clk_ops clk_gate_ops = { +struct clk_ops clk_gate_ops = { .enable = clk_gate_enable, .disable = clk_gate_disable, .is_enabled = clk_gate_is_enabled, }; EXPORT_SYMBOL_GPL(clk_gate_ops); -/** - * clk_register_gate - register a gate clock with the clock framework - * @dev: device that is registering this clock - * @name: name of this clock - * @parent_name: name of this clock's parent - * @flags: framework-specific flags for this clock - * @reg: register address to control gating of this clock - * @bit_idx: which bit in the register controls gating of this clock - * @clk_gate_flags: gate-specific flags for this clock - * @lock: shared register lock for this clock - */ struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -119,32 +115,36 @@ struct clk *clk_register_gate(struct device *dev, const char *name, { struct clk_gate *gate; struct clk *clk; - struct clk_init_data init; - /* allocate the gate */ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); + if (!gate) { pr_err("%s: could not allocate gated clk\n", __func__); - return ERR_PTR(-ENOMEM); + return NULL; } - init.name = name; - init.ops = &clk_gate_ops; - init.flags = flags; - init.parent_names = (parent_name ? &parent_name: NULL); - init.num_parents = (parent_name ? 1 : 0); - /* struct clk_gate assignments */ gate->reg = reg; gate->bit_idx = bit_idx; gate->flags = clk_gate_flags; gate->lock = lock; - gate->hw.init = &init; - clk = clk_register(dev, &gate->hw); - - if (IS_ERR(clk)) - kfree(gate); + if (parent_name) { + gate->parent[0] = kstrdup(parent_name, GFP_KERNEL); + if (!gate->parent[0]) + goto out; + } - return clk; + clk = clk_register(dev, name, + &clk_gate_ops, &gate->hw, + gate->parent, + (parent_name ? 1 : 0), + flags); + if (clk) + return clk; +out: + kfree(gate->parent[0]); + kfree(gate); + + return NULL; } diff --git a/trunk/drivers/clk/clk-mux.c b/trunk/drivers/clk/clk-mux.c index fd36a8ea73d9..c71ad1f41a97 100644 --- a/trunk/drivers/clk/clk-mux.c +++ b/trunk/drivers/clk/clk-mux.c @@ -55,6 +55,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) return val; } +EXPORT_SYMBOL_GPL(clk_mux_get_parent); static int clk_mux_set_parent(struct clk_hw *hw, u8 index) { @@ -81,47 +82,35 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) return 0; } +EXPORT_SYMBOL_GPL(clk_mux_set_parent); -const struct clk_ops clk_mux_ops = { +struct clk_ops clk_mux_ops = { .get_parent = clk_mux_get_parent, .set_parent = clk_mux_set_parent, }; EXPORT_SYMBOL_GPL(clk_mux_ops); struct clk *clk_register_mux(struct device *dev, const char *name, - const char **parent_names, u8 num_parents, unsigned long flags, + char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock) { struct clk_mux *mux; - struct clk *clk; - struct clk_init_data init; - /* allocate the mux */ - mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); + mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL); + if (!mux) { pr_err("%s: could not allocate mux clk\n", __func__); return ERR_PTR(-ENOMEM); } - init.name = name; - init.ops = &clk_mux_ops; - init.flags = flags; - init.parent_names = parent_names; - init.num_parents = num_parents; - /* struct clk_mux assignments */ mux->reg = reg; mux->shift = shift; mux->width = width; mux->flags = clk_mux_flags; mux->lock = lock; - mux->hw.init = &init; - - clk = clk_register(dev, &mux->hw); - - if (IS_ERR(clk)) - kfree(mux); - return clk; + return clk_register(dev, name, &clk_mux_ops, &mux->hw, + parent_names, num_parents, flags); } diff --git a/trunk/drivers/clk/clk.c b/trunk/drivers/clk/clk.c index e5d5dc13bcfd..9cf6f59e3e19 100644 --- a/trunk/drivers/clk/clk.c +++ b/trunk/drivers/clk/clk.c @@ -194,8 +194,9 @@ static int __init clk_debug_init(void) late_initcall(clk_debug_init); #else static inline int clk_debug_register(struct clk *clk) { return 0; } -#endif +#endif /* CONFIG_COMMON_CLK_DEBUG */ +#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED /* caller must hold prepare_lock */ static void clk_disable_unused_subtree(struct clk *clk) { @@ -245,6 +246,9 @@ static int clk_disable_unused(void) return 0; } late_initcall(clk_disable_unused); +#else +static inline int clk_disable_unused(struct clk *clk) { return 0; } +#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */ /*** helper functions ***/ @@ -283,7 +287,7 @@ unsigned long __clk_get_rate(struct clk *clk) unsigned long ret; if (!clk) { - ret = 0; + ret = -EINVAL; goto out; } @@ -293,7 +297,7 @@ unsigned long __clk_get_rate(struct clk *clk) goto out; if (!clk->parent) - ret = 0; + ret = -ENODEV; out: return ret; @@ -558,7 +562,7 @@ EXPORT_SYMBOL_GPL(clk_enable); * @clk: the clk whose rate is being returned * * Simply returns the cached rate of the clk. Does not query the hardware. If - * clk is NULL then returns 0. + * clk is NULL then returns -EINVAL. */ unsigned long clk_get_rate(struct clk *clk) { @@ -580,22 +584,18 @@ EXPORT_SYMBOL_GPL(clk_get_rate); */ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) { - unsigned long parent_rate = 0; + unsigned long unused; if (!clk) return -EINVAL; - if (!clk->ops->round_rate) { - if (clk->flags & CLK_SET_RATE_PARENT) - return __clk_round_rate(clk->parent, rate); - else - return clk->rate; - } + if (!clk->ops->round_rate) + return clk->rate; - if (clk->parent) - parent_rate = clk->parent->rate; - - return clk->ops->round_rate(clk->hw, rate, &parent_rate); + if (clk->flags & CLK_SET_RATE_PARENT) + return clk->ops->round_rate(clk->hw, rate, &unused); + else + return clk->ops->round_rate(clk->hw, rate, NULL); } /** @@ -765,41 +765,25 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate) static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) { struct clk *top = clk; - unsigned long best_parent_rate = 0; + unsigned long best_parent_rate = clk->parent->rate; unsigned long new_rate; - /* sanity */ - if (IS_ERR_OR_NULL(clk)) + if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) { + clk->new_rate = clk->rate; return NULL; - - /* save parent rate, if it exists */ - if (clk->parent) - best_parent_rate = clk->parent->rate; - - /* never propagate up to the parent */ - if (!(clk->flags & CLK_SET_RATE_PARENT)) { - if (!clk->ops->round_rate) { - clk->new_rate = clk->rate; - return NULL; - } - new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); - goto out; } - /* need clk->parent from here on out */ - if (!clk->parent) { - pr_debug("%s: %s has NULL parent\n", __func__, clk->name); - return NULL; - } - - if (!clk->ops->round_rate) { + if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) { top = clk_calc_new_rates(clk->parent, rate); - new_rate = clk->parent->new_rate; + new_rate = clk->new_rate = clk->parent->new_rate; goto out; } - new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); + if (clk->flags & CLK_SET_RATE_PARENT) + new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate); + else + new_rate = clk->ops->round_rate(clk->hw, rate, NULL); if (best_parent_rate != clk->parent->rate) { top = clk_calc_new_rates(clk->parent, best_parent_rate); @@ -855,7 +839,7 @@ static void clk_change_rate(struct clk *clk) old_rate = clk->rate; if (clk->ops->set_rate) - clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate); + clk->ops->set_rate(clk->hw, clk->new_rate); if (clk->ops->recalc_rate) clk->rate = clk->ops->recalc_rate(clk->hw, @@ -875,19 +859,38 @@ static void clk_change_rate(struct clk *clk) * @clk: the clk whose rate is being changed * @rate: the new rate for clk * - * In the simplest case clk_set_rate will only adjust the rate of clk. + * In the simplest case clk_set_rate will only change the rate of clk. * - * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to - * propagate up to clk's parent; whether or not this happens depends on the - * outcome of clk's .round_rate implementation. If *parent_rate is unchanged - * after calling .round_rate then upstream parent propagation is ignored. If - * *parent_rate comes back with a new rate for clk's parent then we propagate - * up to clk's parent and set it's rate. Upward propagation will continue - * until either a clk does not support the CLK_SET_RATE_PARENT flag or - * .round_rate stops requesting changes to clk's parent_rate. + * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call + * will fail; only when the clk is disabled will it be able to change + * its rate. * - * Rate changes are accomplished via tree traversal that also recalculates the - * rates for the clocks and fires off POST_RATE_CHANGE notifiers. + * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to + * recursively propagate up to clk's parent; whether or not this happens + * depends on the outcome of clk's .round_rate implementation. If + * *parent_rate is 0 after calling .round_rate then upstream parent + * propagation is ignored. If *parent_rate comes back with a new rate + * for clk's parent then we propagate up to clk's parent and set it's + * rate. Upward propagation will continue until either a clk does not + * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting + * changes to clk's parent_rate. If there is a failure during upstream + * propagation then clk_set_rate will unwind and restore each clk's rate + * that had been successfully changed. Afterwards a rate change abort + * notification will be propagated downstream, starting from the clk + * that failed. + * + * At the end of all of the rate setting, clk_set_rate internally calls + * __clk_recalc_rates and propagates the rate changes downstream, + * starting from the highest clk whose rate was changed. This has the + * added benefit of propagating post-rate change notifiers. + * + * Note that while post-rate change and rate change abort notifications + * are guaranteed to be sent to a clk only once per call to + * clk_set_rate, pre-change notifications will be sent for every clk + * whose rate is changed. Stacking pre-change notifications is noisy + * for the drivers subscribed to them, but this allows drivers to react + * to intermediate clk rate changes up until the point where the final + * rate is achieved at the end of upstream propagation. * * Returns 0 on success, -EERROR otherwise. */ @@ -903,11 +906,6 @@ int clk_set_rate(struct clk *clk, unsigned long rate) if (rate == clk->rate) goto out; - if ((clk->flags & CLK_SET_RATE_GATE) && __clk_is_enabled(clk)) { - ret = -EBUSY; - goto out; - } - /* calculate new rates and get the topmost changed clock */ top = clk_calc_new_rates(clk, rate); if (!top) { @@ -1177,41 +1175,40 @@ EXPORT_SYMBOL_GPL(clk_set_parent); * * Initializes the lists in struct clk, queries the hardware for the * parent and rate and sets them both. + * + * Any struct clk passed into __clk_init must have the following members + * populated: + * .name + * .ops + * .hw + * .parent_names + * .num_parents + * .flags + * + * Essentially, everything that would normally be passed into clk_register is + * assumed to be initialized already in __clk_init. The other members may be + * populated, but are optional. + * + * __clk_init is only exposed via clk-private.h and is intended for use with + * very large numbers of clocks that need to be statically initialized. It is + * a layering violation to include clk-private.h from any code which implements + * a clock's .ops; as such any statically initialized clock data MUST be in a + * separate C file from the logic that implements it's operations. */ -int __clk_init(struct device *dev, struct clk *clk) +void __clk_init(struct device *dev, struct clk *clk) { - int i, ret = 0; + int i; struct clk *orphan; struct hlist_node *tmp, *tmp2; if (!clk) - return -EINVAL; + return; mutex_lock(&prepare_lock); /* check to see if a clock with this name is already registered */ - if (__clk_lookup(clk->name)) { - pr_debug("%s: clk %s already initialized\n", - __func__, clk->name); - ret = -EEXIST; - goto out; - } - - /* check that clk_ops are sane. See Documentation/clk.txt */ - if (clk->ops->set_rate && - !(clk->ops->round_rate && clk->ops->recalc_rate)) { - pr_warning("%s: %s must implement .round_rate & .recalc_rate\n", - __func__, clk->name); - ret = -EINVAL; + if (__clk_lookup(clk->name)) goto out; - } - - if (clk->ops->set_parent && !clk->ops->get_parent) { - pr_warning("%s: %s must implement .get_parent & .set_parent\n", - __func__, clk->name); - ret = -EINVAL; - goto out; - } /* throw a WARN if any entries in parent_names are NULL */ for (i = 0; i < clk->num_parents; i++) @@ -1305,118 +1302,45 @@ int __clk_init(struct device *dev, struct clk *clk) out: mutex_unlock(&prepare_lock); - return ret; -} - -/** - * __clk_register - register a clock and return a cookie. - * - * Same as clk_register, except that the .clk field inside hw shall point to a - * preallocated (generally statically allocated) struct clk. None of the fields - * of the struct clk need to be initialized. - * - * The data pointed to by .init and .clk field shall NOT be marked as init - * data. - * - * __clk_register is only exposed via clk-private.h and is intended for use with - * very large numbers of clocks that need to be statically initialized. It is - * a layering violation to include clk-private.h from any code which implements - * a clock's .ops; as such any statically initialized clock data MUST be in a - * separate C file from the logic that implements it's operations. Returns 0 - * on success, otherwise an error code. - */ -struct clk *__clk_register(struct device *dev, struct clk_hw *hw) -{ - int ret; - struct clk *clk; - - clk = hw->clk; - clk->name = hw->init->name; - clk->ops = hw->init->ops; - clk->hw = hw; - clk->flags = hw->init->flags; - clk->parent_names = hw->init->parent_names; - clk->num_parents = hw->init->num_parents; - - ret = __clk_init(dev, clk); - if (ret) - return ERR_PTR(ret); - - return clk; + return; } -EXPORT_SYMBOL_GPL(__clk_register); /** * clk_register - allocate a new clock, register it and return an opaque cookie * @dev: device that is registering this clock + * @name: clock name + * @ops: operations this clock supports * @hw: link to hardware-specific clock data + * @parent_names: array of string names for all possible parents + * @num_parents: number of possible parents + * @flags: framework-level hints and quirks * * clk_register is the primary interface for populating the clock tree with new * clock nodes. It returns a pointer to the newly allocated struct clk which * cannot be dereferenced by driver code but may be used in conjuction with the - * rest of the clock API. In the event of an error clk_register will return an - * error code; drivers must test for an error code after calling clk_register. + * rest of the clock API. */ -struct clk *clk_register(struct device *dev, struct clk_hw *hw) +struct clk *clk_register(struct device *dev, const char *name, + const struct clk_ops *ops, struct clk_hw *hw, + char **parent_names, u8 num_parents, unsigned long flags) { - int i, ret; struct clk *clk; clk = kzalloc(sizeof(*clk), GFP_KERNEL); - if (!clk) { - pr_err("%s: could not allocate clk\n", __func__); - ret = -ENOMEM; - goto fail_out; - } + if (!clk) + return NULL; - clk->name = kstrdup(hw->init->name, GFP_KERNEL); - if (!clk->name) { - pr_err("%s: could not allocate clk->name\n", __func__); - ret = -ENOMEM; - goto fail_name; - } - clk->ops = hw->init->ops; + clk->name = name; + clk->ops = ops; clk->hw = hw; - clk->flags = hw->init->flags; - clk->num_parents = hw->init->num_parents; + clk->flags = flags; + clk->parent_names = parent_names; + clk->num_parents = num_parents; hw->clk = clk; - /* allocate local copy in case parent_names is __initdata */ - clk->parent_names = kzalloc((sizeof(char*) * clk->num_parents), - GFP_KERNEL); - - if (!clk->parent_names) { - pr_err("%s: could not allocate clk->parent_names\n", __func__); - ret = -ENOMEM; - goto fail_parent_names; - } - - - /* copy each string name in case parent_names is __initdata */ - for (i = 0; i < clk->num_parents; i++) { - clk->parent_names[i] = kstrdup(hw->init->parent_names[i], - GFP_KERNEL); - if (!clk->parent_names[i]) { - pr_err("%s: could not copy parent_names\n", __func__); - ret = -ENOMEM; - goto fail_parent_names_copy; - } - } + __clk_init(dev, clk); - ret = __clk_init(dev, clk); - if (!ret) - return clk; - -fail_parent_names_copy: - while (--i >= 0) - kfree(clk->parent_names[i]); - kfree(clk->parent_names); -fail_parent_names: - kfree(clk->name); -fail_name: - kfree(clk); -fail_out: - return ERR_PTR(ret); + return clk; } EXPORT_SYMBOL_GPL(clk_register); diff --git a/trunk/drivers/clk/clkdev.c b/trunk/drivers/clk/clkdev.c index c535cf8c5770..6db161f64ae0 100644 --- a/trunk/drivers/clk/clkdev.c +++ b/trunk/drivers/clk/clkdev.c @@ -35,12 +35,7 @@ static DEFINE_MUTEX(clocks_mutex); static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) { struct clk_lookup *p, *cl = NULL; - int match, best_found = 0, best_possible = 0; - - if (dev_id) - best_possible += 2; - if (con_id) - best_possible += 1; + int match, best = 0; list_for_each_entry(p, &clocks, node) { match = 0; @@ -55,10 +50,10 @@ static struct clk_lookup *clk_find(const char *dev_id, const char *con_id) match += 1; } - if (match > best_found) { + if (match > best) { cl = p; - if (match != best_possible) - best_found = match; + if (match != 3) + best = match; else break; } @@ -94,51 +89,6 @@ void clk_put(struct clk *clk) } EXPORT_SYMBOL(clk_put); -static void devm_clk_release(struct device *dev, void *res) -{ - clk_put(*(struct clk **)res); -} - -struct clk *devm_clk_get(struct device *dev, const char *id) -{ - struct clk **ptr, *clk; - - ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL); - if (!ptr) - return ERR_PTR(-ENOMEM); - - clk = clk_get(dev, id); - if (!IS_ERR(clk)) { - *ptr = clk; - devres_add(dev, ptr); - } else { - devres_free(ptr); - } - - return clk; -} -EXPORT_SYMBOL(devm_clk_get); - -static int devm_clk_match(struct device *dev, void *res, void *data) -{ - struct clk **c = res; - if (!c || !*c) { - WARN_ON(!c || !*c); - return 0; - } - return *c == data; -} - -void devm_clk_put(struct device *dev, struct clk *clk) -{ - int ret; - - ret = devres_destroy(dev, devm_clk_release, devm_clk_match, clk); - - WARN_ON(ret); -} -EXPORT_SYMBOL(devm_clk_put); - void clkdev_add(struct clk_lookup *cl) { mutex_lock(&clocks_mutex); @@ -166,9 +116,8 @@ struct clk_lookup_alloc { char con_id[MAX_CON_ID]; }; -static struct clk_lookup * __init_refok -vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, - va_list ap) +struct clk_lookup * __init_refok +clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) { struct clk_lookup_alloc *cla; @@ -183,25 +132,16 @@ vclkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, } if (dev_fmt) { + va_list ap; + + va_start(ap, dev_fmt); vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap); cla->cl.dev_id = cla->dev_id; + va_end(ap); } return &cla->cl; } - -struct clk_lookup * __init_refok -clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); - va_end(ap); - - return cl; -} EXPORT_SYMBOL(clkdev_alloc); int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, @@ -233,65 +173,3 @@ void clkdev_drop(struct clk_lookup *cl) kfree(cl); } EXPORT_SYMBOL(clkdev_drop); - -/** - * clk_register_clkdev - register one clock lookup for a struct clk - * @clk: struct clk to associate with all clk_lookups - * @con_id: connection ID string on device - * @dev_id: format string describing device name - * - * con_id or dev_id may be NULL as a wildcard, just as in the rest of - * clkdev. - * - * To make things easier for mass registration, we detect error clks - * from a previous clk_register() call, and return the error code for - * those. This is to permit this function to be called immediately - * after clk_register(). - */ -int clk_register_clkdev(struct clk *clk, const char *con_id, - const char *dev_fmt, ...) -{ - struct clk_lookup *cl; - va_list ap; - - if (IS_ERR(clk)) - return PTR_ERR(clk); - - va_start(ap, dev_fmt); - cl = vclkdev_alloc(clk, con_id, dev_fmt, ap); - va_end(ap); - - if (!cl) - return -ENOMEM; - - clkdev_add(cl); - - return 0; -} - -/** - * clk_register_clkdevs - register a set of clk_lookup for a struct clk - * @clk: struct clk to associate with all clk_lookups - * @cl: array of clk_lookup structures with con_id and dev_id pre-initialized - * @num: number of clk_lookup structures to register - * - * To make things easier for mass registration, we detect error clks - * from a previous clk_register() call, and return the error code for - * those. This is to permit this function to be called immediately - * after clk_register(). - */ -int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num) -{ - unsigned i; - - if (IS_ERR(clk)) - return PTR_ERR(clk); - - for (i = 0; i < num; i++, cl++) { - cl->clk = clk; - clkdev_add(cl); - } - - return 0; -} -EXPORT_SYMBOL(clk_register_clkdevs); diff --git a/trunk/drivers/clk/spear/Makefile b/trunk/drivers/clk/spear/Makefile deleted file mode 100644 index 335886049c83..000000000000 --- a/trunk/drivers/clk/spear/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPEAr Clock specific Makefile -# - -obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o - -obj-$(CONFIG_ARCH_SPEAR3XX) += spear3xx_clock.o -obj-$(CONFIG_ARCH_SPEAR6XX) += spear6xx_clock.o diff --git a/trunk/drivers/clk/spear/clk-aux-synth.c b/trunk/drivers/clk/spear/clk-aux-synth.c deleted file mode 100644 index af34074e702b..000000000000 --- a/trunk/drivers/clk/spear/clk-aux-synth.c +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Auxiliary Synthesizer clock implementation - */ - -#define pr_fmt(fmt) "clk-aux-synth: " fmt - -#include -#include -#include -#include -#include "clk.h" - -/* - * DOC: Auxiliary Synthesizer clock - * - * Aux synth gives rate for different values of eq, x and y - * - * Fout from synthesizer can be given from two equations: - * Fout1 = (Fin * X/Y)/2 EQ1 - * Fout2 = Fin * X/Y EQ2 - */ - -#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw) - -static struct aux_clk_masks default_aux_masks = { - .eq_sel_mask = AUX_EQ_SEL_MASK, - .eq_sel_shift = AUX_EQ_SEL_SHIFT, - .eq1_mask = AUX_EQ1_SEL, - .eq2_mask = AUX_EQ2_SEL, - .xscale_sel_mask = AUX_XSCALE_MASK, - .xscale_sel_shift = AUX_XSCALE_SHIFT, - .yscale_sel_mask = AUX_YSCALE_MASK, - .yscale_sel_shift = AUX_YSCALE_SHIFT, - .enable_bit = AUX_SYNT_ENB, -}; - -static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate, - int index) -{ - struct clk_aux *aux = to_clk_aux(hw); - struct aux_rate_tbl *rtbl = aux->rtbl; - u8 eq = rtbl[index].eq ? 1 : 2; - - return (((prate / 10000) * rtbl[index].xscale) / - (rtbl[index].yscale * eq)) * 10000; -} - -static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *prate) -{ - struct clk_aux *aux = to_clk_aux(hw); - int unused; - - return clk_round_rate_index(hw, drate, *prate, aux_calc_rate, - aux->rtbl_cnt, &unused); -} - -static unsigned long clk_aux_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_aux *aux = to_clk_aux(hw); - unsigned int num = 1, den = 1, val, eqn; - unsigned long flags = 0; - - if (aux->lock) - spin_lock_irqsave(aux->lock, flags); - - val = readl_relaxed(aux->reg); - - if (aux->lock) - spin_unlock_irqrestore(aux->lock, flags); - - eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; - if (eqn == aux->masks->eq1_mask) - den = 2; - - /* calculate numerator */ - num = (val >> aux->masks->xscale_sel_shift) & - aux->masks->xscale_sel_mask; - - /* calculate denominator */ - den *= (val >> aux->masks->yscale_sel_shift) & - aux->masks->yscale_sel_mask; - - if (!den) - return 0; - - return (((parent_rate / 10000) * num) / den) * 10000; -} - -/* Configures new clock rate of aux */ -static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct clk_aux *aux = to_clk_aux(hw); - struct aux_rate_tbl *rtbl = aux->rtbl; - unsigned long val, flags = 0; - int i; - - clk_round_rate_index(hw, drate, prate, aux_calc_rate, aux->rtbl_cnt, - &i); - - if (aux->lock) - spin_lock_irqsave(aux->lock, flags); - - val = readl_relaxed(aux->reg) & - ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); - val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << - aux->masks->eq_sel_shift; - val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); - val |= (rtbl[i].xscale & aux->masks->xscale_sel_mask) << - aux->masks->xscale_sel_shift; - val &= ~(aux->masks->yscale_sel_mask << aux->masks->yscale_sel_shift); - val |= (rtbl[i].yscale & aux->masks->yscale_sel_mask) << - aux->masks->yscale_sel_shift; - writel_relaxed(val, aux->reg); - - if (aux->lock) - spin_unlock_irqrestore(aux->lock, flags); - - return 0; -} - -static struct clk_ops clk_aux_ops = { - .recalc_rate = clk_aux_recalc_rate, - .round_rate = clk_aux_round_rate, - .set_rate = clk_aux_set_rate, -}; - -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, - const char *parent_name, unsigned long flags, void __iomem *reg, - struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) -{ - struct clk_aux *aux; - struct clk_init_data init; - struct clk *clk; - - if (!aux_name || !parent_name || !reg || !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); - return ERR_PTR(-EINVAL); - } - - aux = kzalloc(sizeof(*aux), GFP_KERNEL); - if (!aux) { - pr_err("could not allocate aux clk\n"); - return ERR_PTR(-ENOMEM); - } - - /* struct clk_aux assignments */ - if (!masks) - aux->masks = &default_aux_masks; - else - aux->masks = masks; - - aux->reg = reg; - aux->rtbl = rtbl; - aux->rtbl_cnt = rtbl_cnt; - aux->lock = lock; - aux->hw.init = &init; - - init.name = aux_name; - init.ops = &clk_aux_ops; - init.flags = flags; - init.parent_names = &parent_name; - init.num_parents = 1; - - clk = clk_register(NULL, &aux->hw); - if (IS_ERR_OR_NULL(clk)) - goto free_aux; - - if (gate_name) { - struct clk *tgate_clk; - - tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg, - aux->masks->enable_bit, 0, lock); - if (IS_ERR_OR_NULL(tgate_clk)) - goto free_aux; - - if (gate_clk) - *gate_clk = tgate_clk; - } - - return clk; - -free_aux: - kfree(aux); - pr_err("clk register failed\n"); - - return NULL; -} diff --git a/trunk/drivers/clk/spear/clk-frac-synth.c b/trunk/drivers/clk/spear/clk-frac-synth.c deleted file mode 100644 index 4dbdb3fe18e0..000000000000 --- a/trunk/drivers/clk/spear/clk-frac-synth.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * Fractional Synthesizer clock implementation - */ - -#define pr_fmt(fmt) "clk-frac-synth: " fmt - -#include -#include -#include -#include -#include "clk.h" - -#define DIV_FACTOR_MASK 0x1FFFF - -/* - * DOC: Fractional Synthesizer clock - * - * Fout from synthesizer can be given from below equation: - * - * Fout= Fin/2*div (division factor) - * div is 17 bits:- - * 0-13 (fractional part) - * 14-16 (integer part) - * div is (16-14 bits).(13-0 bits) (in binary) - * - * Fout = Fin/(2 * div) - * Fout = ((Fin / 10000)/(2 * div)) * 10000 - * Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 - * Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 - * - * div << 14 simply 17 bit value written at register. - * Max error due to scaling down by 10000 is 10 KHz - */ - -#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw) - -static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, - int index) -{ - struct clk_frac *frac = to_clk_frac(hw); - struct frac_rate_tbl *rtbl = frac->rtbl; - - prate /= 10000; - prate <<= 14; - prate /= (2 * rtbl[index].div); - prate *= 10000; - - return prate; -} - -static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *prate) -{ - struct clk_frac *frac = to_clk_frac(hw); - int unused; - - return clk_round_rate_index(hw, drate, *prate, frac_calc_rate, - frac->rtbl_cnt, &unused); -} - -static unsigned long clk_frac_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_frac *frac = to_clk_frac(hw); - unsigned long flags = 0; - unsigned int div = 1, val; - - if (frac->lock) - spin_lock_irqsave(frac->lock, flags); - - val = readl_relaxed(frac->reg); - - if (frac->lock) - spin_unlock_irqrestore(frac->lock, flags); - - div = val & DIV_FACTOR_MASK; - - if (!div) - return 0; - - parent_rate = parent_rate / 10000; - - parent_rate = (parent_rate << 14) / (2 * div); - return parent_rate * 10000; -} - -/* Configures new clock rate of frac */ -static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct clk_frac *frac = to_clk_frac(hw); - struct frac_rate_tbl *rtbl = frac->rtbl; - unsigned long flags = 0, val; - int i; - - clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, - &i); - - if (frac->lock) - spin_lock_irqsave(frac->lock, flags); - - val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; - val |= rtbl[i].div & DIV_FACTOR_MASK; - writel_relaxed(val, frac->reg); - - if (frac->lock) - spin_unlock_irqrestore(frac->lock, flags); - - return 0; -} - -struct clk_ops clk_frac_ops = { - .recalc_rate = clk_frac_recalc_rate, - .round_rate = clk_frac_round_rate, - .set_rate = clk_frac_set_rate, -}; - -struct clk *clk_register_frac(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg, - struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) -{ - struct clk_init_data init; - struct clk_frac *frac; - struct clk *clk; - - if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); - return ERR_PTR(-EINVAL); - } - - frac = kzalloc(sizeof(*frac), GFP_KERNEL); - if (!frac) { - pr_err("could not allocate frac clk\n"); - return ERR_PTR(-ENOMEM); - } - - /* struct clk_frac assignments */ - frac->reg = reg; - frac->rtbl = rtbl; - frac->rtbl_cnt = rtbl_cnt; - frac->lock = lock; - frac->hw.init = &init; - - init.name = name; - init.ops = &clk_frac_ops; - init.flags = flags; - init.parent_names = &parent_name; - init.num_parents = 1; - - clk = clk_register(NULL, &frac->hw); - if (!IS_ERR_OR_NULL(clk)) - return clk; - - pr_err("clk register failed\n"); - kfree(frac); - - return NULL; -} diff --git a/trunk/drivers/clk/spear/clk-gpt-synth.c b/trunk/drivers/clk/spear/clk-gpt-synth.c deleted file mode 100644 index b471c9762a97..000000000000 --- a/trunk/drivers/clk/spear/clk-gpt-synth.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * General Purpose Timer Synthesizer clock implementation - */ - -#define pr_fmt(fmt) "clk-gpt-synth: " fmt - -#include -#include -#include -#include -#include "clk.h" - -#define GPT_MSCALE_MASK 0xFFF -#define GPT_NSCALE_SHIFT 12 -#define GPT_NSCALE_MASK 0xF - -/* - * DOC: General Purpose Timer Synthesizer clock - * - * Calculates gpt synth clk rate for different values of mscale and nscale - * - * Fout= Fin/((2 ^ (N+1)) * (M+1)) - */ - -#define to_clk_gpt(_hw) container_of(_hw, struct clk_gpt, hw) - -static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate, - int index) -{ - struct clk_gpt *gpt = to_clk_gpt(hw); - struct gpt_rate_tbl *rtbl = gpt->rtbl; - - prate /= ((1 << (rtbl[index].nscale + 1)) * (rtbl[index].mscale + 1)); - - return prate; -} - -static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *prate) -{ - struct clk_gpt *gpt = to_clk_gpt(hw); - int unused; - - return clk_round_rate_index(hw, drate, *prate, gpt_calc_rate, - gpt->rtbl_cnt, &unused); -} - -static unsigned long clk_gpt_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_gpt *gpt = to_clk_gpt(hw); - unsigned long flags = 0; - unsigned int div = 1, val; - - if (gpt->lock) - spin_lock_irqsave(gpt->lock, flags); - - val = readl_relaxed(gpt->reg); - - if (gpt->lock) - spin_unlock_irqrestore(gpt->lock, flags); - - div += val & GPT_MSCALE_MASK; - div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1); - - if (!div) - return 0; - - return parent_rate / div; -} - -/* Configures new clock rate of gpt */ -static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct clk_gpt *gpt = to_clk_gpt(hw); - struct gpt_rate_tbl *rtbl = gpt->rtbl; - unsigned long flags = 0, val; - int i; - - clk_round_rate_index(hw, drate, prate, gpt_calc_rate, gpt->rtbl_cnt, - &i); - - if (gpt->lock) - spin_lock_irqsave(gpt->lock, flags); - - val = readl(gpt->reg) & ~GPT_MSCALE_MASK; - val &= ~(GPT_NSCALE_MASK << GPT_NSCALE_SHIFT); - - val |= rtbl[i].mscale & GPT_MSCALE_MASK; - val |= (rtbl[i].nscale & GPT_NSCALE_MASK) << GPT_NSCALE_SHIFT; - - writel_relaxed(val, gpt->reg); - - if (gpt->lock) - spin_unlock_irqrestore(gpt->lock, flags); - - return 0; -} - -static struct clk_ops clk_gpt_ops = { - .recalc_rate = clk_gpt_recalc_rate, - .round_rate = clk_gpt_round_rate, - .set_rate = clk_gpt_set_rate, -}; - -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned - long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 - rtbl_cnt, spinlock_t *lock) -{ - struct clk_init_data init; - struct clk_gpt *gpt; - struct clk *clk; - - if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); - return ERR_PTR(-EINVAL); - } - - gpt = kzalloc(sizeof(*gpt), GFP_KERNEL); - if (!gpt) { - pr_err("could not allocate gpt clk\n"); - return ERR_PTR(-ENOMEM); - } - - /* struct clk_gpt assignments */ - gpt->reg = reg; - gpt->rtbl = rtbl; - gpt->rtbl_cnt = rtbl_cnt; - gpt->lock = lock; - gpt->hw.init = &init; - - init.name = name; - init.ops = &clk_gpt_ops; - init.flags = flags; - init.parent_names = &parent_name; - init.num_parents = 1; - - clk = clk_register(NULL, &gpt->hw); - if (!IS_ERR_OR_NULL(clk)) - return clk; - - pr_err("clk register failed\n"); - kfree(gpt); - - return NULL; -} diff --git a/trunk/drivers/clk/spear/clk-vco-pll.c b/trunk/drivers/clk/spear/clk-vco-pll.c deleted file mode 100644 index dcd4bdf4b0d9..000000000000 --- a/trunk/drivers/clk/spear/clk-vco-pll.c +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * VCO-PLL clock implementation - */ - -#define pr_fmt(fmt) "clk-vco-pll: " fmt - -#include -#include -#include -#include -#include "clk.h" - -/* - * DOC: VCO-PLL clock - * - * VCO and PLL rate are derived from following equations: - * - * In normal mode - * vco = (2 * M[15:8] * Fin)/N - * - * In Dithered mode - * vco = (2 * M[15:0] * Fin)/(256 * N) - * - * pll_rate = pll/2^p - * - * vco and pll are very closely bound to each other, "vco needs to program: - * mode, m & n" and "pll needs to program p", both share common enable/disable - * logic. - * - * clk_register_vco_pll() registers instances of both vco & pll. - * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its - * set_rate to vco. A single rate table exists for both the clocks, which - * configures m, n and p. - */ - -/* PLL_CTR register masks */ -#define PLL_MODE_NORMAL 0 -#define PLL_MODE_FRACTION 1 -#define PLL_MODE_DITH_DSM 2 -#define PLL_MODE_DITH_SSM 3 -#define PLL_MODE_MASK 3 -#define PLL_MODE_SHIFT 3 -#define PLL_ENABLE 2 - -#define PLL_LOCK_SHIFT 0 -#define PLL_LOCK_MASK 1 - -/* PLL FRQ register masks */ -#define PLL_NORM_FDBK_M_MASK 0xFF -#define PLL_NORM_FDBK_M_SHIFT 24 -#define PLL_DITH_FDBK_M_MASK 0xFFFF -#define PLL_DITH_FDBK_M_SHIFT 16 -#define PLL_DIV_P_MASK 0x7 -#define PLL_DIV_P_SHIFT 8 -#define PLL_DIV_N_MASK 0xFF -#define PLL_DIV_N_SHIFT 0 - -#define to_clk_vco(_hw) container_of(_hw, struct clk_vco, hw) -#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) - -/* Calculates pll clk rate for specific value of mode, m, n and p */ -static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl, - unsigned long prate, int index, unsigned long *pll_rate) -{ - unsigned long rate = prate; - unsigned int mode; - - mode = rtbl[index].mode ? 256 : 1; - rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n)); - - if (pll_rate) - *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; - - return rate * 10000; -} - -static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate, - unsigned long *prate, int *index) -{ - struct clk_pll *pll = to_clk_pll(hw); - unsigned long prev_rate, vco_prev_rate, rate = 0; - unsigned long vco_parent_rate = - __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk))); - - if (!prate) { - pr_err("%s: prate is must for pll clk\n", __func__); - return -EINVAL; - } - - for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { - prev_rate = rate; - vco_prev_rate = *prate; - *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, - &rate); - if (drate < rate) { - /* previous clock was best */ - if (*index) { - rate = prev_rate; - *prate = vco_prev_rate; - (*index)--; - } - break; - } - } - - return rate; -} - -static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *prate) -{ - int unused; - - return clk_pll_round_rate_index(hw, drate, prate, &unused); -} - -static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long - parent_rate) -{ - struct clk_pll *pll = to_clk_pll(hw); - unsigned long flags = 0; - unsigned int p; - - if (pll->vco->lock) - spin_lock_irqsave(pll->vco->lock, flags); - - p = readl_relaxed(pll->vco->cfg_reg); - - if (pll->vco->lock) - spin_unlock_irqrestore(pll->vco->lock, flags); - - p = (p >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK; - - return parent_rate / (1 << p); -} - -static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct clk_pll *pll = to_clk_pll(hw); - struct pll_rate_tbl *rtbl = pll->vco->rtbl; - unsigned long flags = 0, val; - int i; - - clk_pll_round_rate_index(hw, drate, NULL, &i); - - if (pll->vco->lock) - spin_lock_irqsave(pll->vco->lock, flags); - - val = readl_relaxed(pll->vco->cfg_reg); - val &= ~(PLL_DIV_P_MASK << PLL_DIV_P_SHIFT); - val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT; - writel_relaxed(val, pll->vco->cfg_reg); - - if (pll->vco->lock) - spin_unlock_irqrestore(pll->vco->lock, flags); - - return 0; -} - -static struct clk_ops clk_pll_ops = { - .recalc_rate = clk_pll_recalc_rate, - .round_rate = clk_pll_round_rate, - .set_rate = clk_pll_set_rate, -}; - -static inline unsigned long vco_calc_rate(struct clk_hw *hw, - unsigned long prate, int index) -{ - struct clk_vco *vco = to_clk_vco(hw); - - return pll_calc_rate(vco->rtbl, prate, index, NULL); -} - -static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *prate) -{ - struct clk_vco *vco = to_clk_vco(hw); - int unused; - - return clk_round_rate_index(hw, drate, *prate, vco_calc_rate, - vco->rtbl_cnt, &unused); -} - -static unsigned long clk_vco_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct clk_vco *vco = to_clk_vco(hw); - unsigned long flags = 0; - unsigned int num = 2, den = 0, val, mode = 0; - - if (vco->lock) - spin_lock_irqsave(vco->lock, flags); - - mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; - - val = readl_relaxed(vco->cfg_reg); - - if (vco->lock) - spin_unlock_irqrestore(vco->lock, flags); - - den = (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK; - - /* calculate numerator & denominator */ - if (!mode) { - /* Normal mode */ - num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK; - } else { - /* Dithered mode */ - num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK; - den *= 256; - } - - if (!den) { - WARN(1, "%s: denominator can't be zero\n", __func__); - return 0; - } - - return (((parent_rate / 10000) * num) / den) * 10000; -} - -/* Configures new clock rate of vco */ -static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate, - unsigned long prate) -{ - struct clk_vco *vco = to_clk_vco(hw); - struct pll_rate_tbl *rtbl = vco->rtbl; - unsigned long flags = 0, val; - int i; - - clk_round_rate_index(hw, drate, prate, vco_calc_rate, vco->rtbl_cnt, - &i); - - if (vco->lock) - spin_lock_irqsave(vco->lock, flags); - - val = readl_relaxed(vco->mode_reg); - val &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT); - val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT; - writel_relaxed(val, vco->mode_reg); - - val = readl_relaxed(vco->cfg_reg); - val &= ~(PLL_DIV_N_MASK << PLL_DIV_N_SHIFT); - val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT; - - val &= ~(PLL_DITH_FDBK_M_MASK << PLL_DITH_FDBK_M_SHIFT); - if (rtbl[i].mode) - val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) << - PLL_DITH_FDBK_M_SHIFT; - else - val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) << - PLL_NORM_FDBK_M_SHIFT; - - writel_relaxed(val, vco->cfg_reg); - - if (vco->lock) - spin_unlock_irqrestore(vco->lock, flags); - - return 0; -} - -static struct clk_ops clk_vco_ops = { - .recalc_rate = clk_vco_recalc_rate, - .round_rate = clk_vco_round_rate, - .set_rate = clk_vco_set_rate, -}; - -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, - const char *vco_gate_name, const char *parent_name, - unsigned long flags, void __iomem *mode_reg, void __iomem - *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk) -{ - struct clk_vco *vco; - struct clk_pll *pll; - struct clk *vco_clk, *tpll_clk, *tvco_gate_clk; - struct clk_init_data vco_init, pll_init; - const char **vco_parent_name; - - if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || - !rtbl || !rtbl_cnt) { - pr_err("Invalid arguments passed"); - return ERR_PTR(-EINVAL); - } - - vco = kzalloc(sizeof(*vco), GFP_KERNEL); - if (!vco) { - pr_err("could not allocate vco clk\n"); - return ERR_PTR(-ENOMEM); - } - - pll = kzalloc(sizeof(*pll), GFP_KERNEL); - if (!pll) { - pr_err("could not allocate pll clk\n"); - goto free_vco; - } - - /* struct clk_vco assignments */ - vco->mode_reg = mode_reg; - vco->cfg_reg = cfg_reg; - vco->rtbl = rtbl; - vco->rtbl_cnt = rtbl_cnt; - vco->lock = lock; - vco->hw.init = &vco_init; - - pll->vco = vco; - pll->hw.init = &pll_init; - - if (vco_gate_name) { - tvco_gate_clk = clk_register_gate(NULL, vco_gate_name, - parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); - if (IS_ERR_OR_NULL(tvco_gate_clk)) - goto free_pll; - - if (vco_gate_clk) - *vco_gate_clk = tvco_gate_clk; - vco_parent_name = &vco_gate_name; - } else { - vco_parent_name = &parent_name; - } - - vco_init.name = vco_name; - vco_init.ops = &clk_vco_ops; - vco_init.flags = flags; - vco_init.parent_names = vco_parent_name; - vco_init.num_parents = 1; - - pll_init.name = pll_name; - pll_init.ops = &clk_pll_ops; - pll_init.flags = CLK_SET_RATE_PARENT; - pll_init.parent_names = &vco_name; - pll_init.num_parents = 1; - - vco_clk = clk_register(NULL, &vco->hw); - if (IS_ERR_OR_NULL(vco_clk)) - goto free_pll; - - tpll_clk = clk_register(NULL, &pll->hw); - if (IS_ERR_OR_NULL(tpll_clk)) - goto free_pll; - - if (pll_clk) - *pll_clk = tpll_clk; - - return vco_clk; - -free_pll: - kfree(pll); -free_vco: - kfree(vco); - - pr_err("Failed to register vco pll clock\n"); - - return ERR_PTR(-ENOMEM); -} diff --git a/trunk/drivers/clk/spear/clk.c b/trunk/drivers/clk/spear/clk.c deleted file mode 100644 index 376d4e5ff326..000000000000 --- a/trunk/drivers/clk/spear/clk.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * SPEAr clk - Common routines - */ - -#include -#include -#include "clk.h" - -long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, - unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, - int *index) -{ - unsigned long prev_rate, rate = 0; - - for (*index = 0; *index < rtbl_cnt; (*index)++) { - prev_rate = rate; - rate = calc_rate(hw, parent_rate, *index); - if (drate < rate) { - /* previous clock was best */ - if (*index) { - rate = prev_rate; - (*index)--; - } - break; - } - } - - return rate; -} diff --git a/trunk/drivers/clk/spear/clk.h b/trunk/drivers/clk/spear/clk.h deleted file mode 100644 index 3321c46a071c..000000000000 --- a/trunk/drivers/clk/spear/clk.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Clock framework definitions for SPEAr platform - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __SPEAR_CLK_H -#define __SPEAR_CLK_H - -#include -#include -#include - -/* Auxiliary Synth clk */ -/* Default masks */ -#define AUX_EQ_SEL_SHIFT 30 -#define AUX_EQ_SEL_MASK 1 -#define AUX_EQ1_SEL 0 -#define AUX_EQ2_SEL 1 -#define AUX_XSCALE_SHIFT 16 -#define AUX_XSCALE_MASK 0xFFF -#define AUX_YSCALE_SHIFT 0 -#define AUX_YSCALE_MASK 0xFFF -#define AUX_SYNT_ENB 31 - -struct aux_clk_masks { - u32 eq_sel_mask; - u32 eq_sel_shift; - u32 eq1_mask; - u32 eq2_mask; - u32 xscale_sel_mask; - u32 xscale_sel_shift; - u32 yscale_sel_mask; - u32 yscale_sel_shift; - u32 enable_bit; -}; - -struct aux_rate_tbl { - u16 xscale; - u16 yscale; - u8 eq; -}; - -struct clk_aux { - struct clk_hw hw; - void __iomem *reg; - struct aux_clk_masks *masks; - struct aux_rate_tbl *rtbl; - u8 rtbl_cnt; - spinlock_t *lock; -}; - -/* Fractional Synth clk */ -struct frac_rate_tbl { - u32 div; -}; - -struct clk_frac { - struct clk_hw hw; - void __iomem *reg; - struct frac_rate_tbl *rtbl; - u8 rtbl_cnt; - spinlock_t *lock; -}; - -/* GPT clk */ -struct gpt_rate_tbl { - u16 mscale; - u16 nscale; -}; - -struct clk_gpt { - struct clk_hw hw; - void __iomem *reg; - struct gpt_rate_tbl *rtbl; - u8 rtbl_cnt; - spinlock_t *lock; -}; - -/* VCO-PLL clk */ -struct pll_rate_tbl { - u8 mode; - u16 m; - u8 n; - u8 p; -}; - -struct clk_vco { - struct clk_hw hw; - void __iomem *mode_reg; - void __iomem *cfg_reg; - struct pll_rate_tbl *rtbl; - u8 rtbl_cnt; - spinlock_t *lock; -}; - -struct clk_pll { - struct clk_hw hw; - struct clk_vco *vco; - const char *parent[1]; - spinlock_t *lock; -}; - -typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate, - int index); - -/* clk register routines */ -struct clk *clk_register_aux(const char *aux_name, const char *gate_name, - const char *parent_name, unsigned long flags, void __iomem *reg, - struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, - u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); -struct clk *clk_register_frac(const char *name, const char *parent_name, - unsigned long flags, void __iomem *reg, - struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned - long flags, void __iomem *reg, struct gpt_rate_tbl *rtbl, u8 - rtbl_cnt, spinlock_t *lock); -struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, - const char *vco_gate_name, const char *parent_name, - unsigned long flags, void __iomem *mode_reg, void __iomem - *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, - spinlock_t *lock, struct clk **pll_clk, - struct clk **vco_gate_clk); - -long clk_round_rate_index(struct clk_hw *hw, unsigned long drate, - unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, - int *index); - -#endif /* __SPEAR_CLK_H */ diff --git a/trunk/drivers/clk/spear/spear3xx_clock.c b/trunk/drivers/clk/spear/spear3xx_clock.c deleted file mode 100644 index 440bb3e4c971..000000000000 --- a/trunk/drivers/clk/spear/spear3xx_clock.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * SPEAr3xx machines clock framework source file - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "clk.h" - -static DEFINE_SPINLOCK(_lock); - -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL2_CTR (MISC_BASE + 0x014) -#define PLL2_FRQ (MISC_BASE + 0x018) -#define PLL_CLK_CFG (MISC_BASE + 0x020) - /* PLL_CLK_CFG register masks */ - #define MCTR_CLK_SHIFT 28 - #define MCTR_CLK_MASK 3 - -#define CORE_CLK_CFG (MISC_BASE + 0x024) - /* CORE CLK CFG register masks */ - #define GEN_SYNTH2_3_CLK_SHIFT 18 - #define GEN_SYNTH2_3_CLK_MASK 1 - - #define HCLK_RATIO_SHIFT 10 - #define HCLK_RATIO_MASK 2 - #define PCLK_RATIO_SHIFT 8 - #define PCLK_RATIO_MASK 2 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) - /* PERIP_CLK_CFG register masks */ - #define UART_CLK_SHIFT 4 - #define UART_CLK_MASK 1 - #define FIRDA_CLK_SHIFT 5 - #define FIRDA_CLK_MASK 2 - #define GPT0_CLK_SHIFT 8 - #define GPT1_CLK_SHIFT 11 - #define GPT2_CLK_SHIFT 12 - #define GPT_CLK_MASK 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) - /* PERIP1_CLK_ENB register masks */ - #define UART_CLK_ENB 3 - #define SSP_CLK_ENB 5 - #define I2C_CLK_ENB 7 - #define JPEG_CLK_ENB 8 - #define FIRDA_CLK_ENB 10 - #define GPT1_CLK_ENB 11 - #define GPT2_CLK_ENB 12 - #define ADC_CLK_ENB 15 - #define RTC_CLK_ENB 17 - #define GPIO_CLK_ENB 18 - #define DMA_CLK_ENB 19 - #define SMI_CLK_ENB 21 - #define GMAC_CLK_ENB 23 - #define USBD_CLK_ENB 24 - #define USBH_CLK_ENB 25 - #define C3_CLK_ENB 31 - -#define RAS_CLK_ENB (MISC_BASE + 0x034) - #define RAS_AHB_CLK_ENB 0 - #define RAS_PLL1_CLK_ENB 1 - #define RAS_APB_CLK_ENB 2 - #define RAS_32K_CLK_ENB 3 - #define RAS_24M_CLK_ENB 4 - #define RAS_48M_CLK_ENB 5 - #define RAS_PLL2_CLK_ENB 7 - #define RAS_SYNT0_CLK_ENB 8 - #define RAS_SYNT1_CLK_ENB 9 - #define RAS_SYNT2_CLK_ENB 10 - #define RAS_SYNT3_CLK_ENB 11 - -#define PRSC0_CLK_CFG (MISC_BASE + 0x044) -#define PRSC1_CLK_CFG (MISC_BASE + 0x048) -#define PRSC2_CLK_CFG (MISC_BASE + 0x04C) -#define AMEM_CLK_CFG (MISC_BASE + 0x050) - #define AMEM_CLK_ENB 0 - -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) -#define GMAC_CLK_SYNT (MISC_BASE + 0x068) -#define GEN0_CLK_SYNT (MISC_BASE + 0x06C) -#define GEN1_CLK_SYNT (MISC_BASE + 0x070) -#define GEN2_CLK_SYNT (MISC_BASE + 0x074) -#define GEN3_CLK_SYNT (MISC_BASE + 0x078) - -/* pll rate configuration table, in ascending order of rates */ -static struct pll_rate_tbl pll_rtbl[] = { - {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */ - {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */ - {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */ -}; - -/* aux rate configuration table, in ascending order of rates */ -static struct aux_rate_tbl aux_rtbl[] = { - /* For PLL1 = 332 MHz */ - {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ - {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ - {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ - {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ -}; - -/* gpt rate configuration table, in ascending order of rates */ -static struct gpt_rate_tbl gpt_rtbl[] = { - /* For pll1 = 332 MHz */ - {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ - {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ - {.mscale = 1, .nscale = 0}, /* 83 MHz */ -}; - -/* clock parents */ -static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; -static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", -}; -static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", }; -static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", }; -static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; -static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; -static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", - "pll2_clk", }; - -#ifdef CONFIG_MACH_SPEAR300 -static void __init spear300_clk_init(void) -{ - struct clk *clk; - - clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, - 1, 1); - clk_register_clkdev(clk, NULL, "60000000.clcd"); - - clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "94000000.flash"); - - clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "70000000.sdhci"); - - clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "a9000000.gpio"); - - clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "a0000000.kbd"); -} -#endif - -/* array of all spear 310 clock lookups */ -#ifdef CONFIG_MACH_SPEAR310 -static void __init spear310_clk_init(void) -{ - struct clk *clk; - - clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, "emi", NULL); - - clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "44000000.flash"); - - clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "tdm"); - - clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "b2000000.serial"); - - clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "b2080000.serial"); - - clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "b2100000.serial"); - - clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "b2180000.serial"); - - clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "b2200000.serial"); -} -#endif - -/* array of all spear 320 clock lookups */ -#ifdef CONFIG_MACH_SPEAR320 - #define SMII_PCLK_SHIFT 18 - #define SMII_PCLK_MASK 2 - #define SMII_PCLK_VAL_PAD 0x0 - #define SMII_PCLK_VAL_PLL2 0x1 - #define SMII_PCLK_VAL_SYNTH0 0x2 - #define SDHCI_PCLK_SHIFT 15 - #define SDHCI_PCLK_MASK 1 - #define SDHCI_PCLK_VAL_48M 0x0 - #define SDHCI_PCLK_VAL_SYNTH3 0x1 - #define I2S_REF_PCLK_SHIFT 8 - #define I2S_REF_PCLK_MASK 1 - #define I2S_REF_PCLK_SYNTH_VAL 0x1 - #define I2S_REF_PCLK_PLL2_VAL 0x0 - #define UART1_PCLK_SHIFT 6 - #define UART1_PCLK_MASK 1 - #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 - #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 - -static const char *i2s_ref_parents[] = { "ras_pll2_clk", - "ras_gen2_synth_gate_clk", }; -static const char *sdhci_parents[] = { "ras_pll3_48m_clk", - "ras_gen3_synth_gate_clk", -}; -static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", - "ras_gen0_synth_gate_clk", }; -static const char *uartx_parents[] = { "ras_gen1_synth_gate_clk", "ras_apb_clk", -}; - -static void __init spear320_clk_init(void) -{ - struct clk *clk; - - clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, - CLK_IS_ROOT, 125000000); - clk_register_clkdev(clk, "smii_125m_pad", NULL); - - clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0, - 1, 1); - clk_register_clkdev(clk, NULL, "90000000.clcd"); - - clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, "emi", NULL); - - clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "4c000000.flash"); - - clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "a7000000.i2c"); - - clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, "pwm", NULL); - - clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "a5000000.spi"); - - clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "a6000000.spi"); - - clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "c_can_platform.0"); - - clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "c_can_platform.1"); - - clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "i2s"); - - clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, - ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG, - I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "i2s_ref_clk", NULL); - - clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1, - 4); - clk_register_clkdev(clk, "i2s_sclk", NULL); - - clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "a9300000.serial"); - - clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, - ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG, - SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "70000000.sdhci"); - - clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, - ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG, - SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "smii_pclk"); - - clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); - clk_register_clkdev(clk, NULL, "smii"); - - clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG, - UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "a3000000.serial"); - - clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "a4000000.serial"); - - clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "a9100000.serial"); - - clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "a9200000.serial"); - - clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "60000000.serial"); - - clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, - ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, - SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, NULL, "60100000.serial"); -} -#endif - -void __init spear3xx_clk_init(void) -{ - struct clk *clk, *clk1; - - clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); - clk_register_clkdev(clk, "apb_pclk", NULL); - - clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, - 32000); - clk_register_clkdev(clk, "osc_32k_clk", NULL); - - clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, - 24000000); - clk_register_clkdev(clk, "osc_24m_clk", NULL); - - /* clock derived from 32 KHz osc clk */ - clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, - PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc900000.rtc"); - - /* clock derived from 24 MHz osc clk */ - clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, - 48000000); - clk_register_clkdev(clk, "pll3_48m_clk", NULL); - - clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "fc880000.wdt"); - - clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, - "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, - ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); - clk_register_clkdev(clk, "vco1_clk", NULL); - clk_register_clkdev(clk1, "pll1_clk", NULL); - - clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, - "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, - ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); - clk_register_clkdev(clk, "vco2_clk", NULL); - clk_register_clkdev(clk1, "pll2_clk", NULL); - - /* clock derived from pll1 clk */ - clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); - clk_register_clkdev(clk, "cpu_clk", NULL); - - clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", - CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, - HCLK_RATIO_MASK, 0, &_lock); - clk_register_clkdev(clk, "ahb_clk", NULL); - - clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", - "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "uart_synth_clk", NULL); - clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents, - ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, - UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "uart0_mux_clk", NULL); - - clk = clk_register_gate(NULL, "uart0", "uart0_mux_clk", 0, - PERIP1_CLK_ENB, UART_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0000000.serial"); - - clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", - "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "firda_synth_clk", NULL); - clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, - ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, - FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "firda_mux_clk", NULL); - - clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, - PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "firda"); - - /* gpt clocks */ - clk_register_gpt("gpt0_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, - ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, - GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt0"); - - clk_register_gpt("gpt1_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt1_parents, - ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, - GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "gpt1_mux_clk", NULL); - clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, - PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt1"); - - clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, - ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, - GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "gpt2_mux_clk", NULL); - clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, - PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt2"); - - /* general synths clocks */ - clk = clk_register_aux("gen0_synth_clk", "gen0_synth_gate_clk", - "pll1_clk", 0, GEN0_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "gen0_synth_clk", NULL); - clk_register_clkdev(clk1, "gen0_synth_gate_clk", NULL); - - clk = clk_register_aux("gen1_synth_clk", "gen1_synth_gate_clk", - "pll1_clk", 0, GEN1_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "gen1_synth_clk", NULL); - clk_register_clkdev(clk1, "gen1_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "gen2_3_parent_clk", gen2_3_parents, - ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, - GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, "gen2_3_parent_clk", NULL); - - clk = clk_register_aux("gen2_synth_clk", "gen2_synth_gate_clk", - "gen2_3_parent_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "gen2_synth_clk", NULL); - clk_register_clkdev(clk1, "gen2_synth_gate_clk", NULL); - - clk = clk_register_aux("gen3_synth_clk", "gen3_synth_gate_clk", - "gen2_3_parent_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "gen3_synth_clk", NULL); - clk_register_clkdev(clk1, "gen3_synth_gate_clk", NULL); - - /* clock derived from pll3 clk */ - clk = clk_register_gate(NULL, "usbh_clk", "pll3_48m_clk", 0, - PERIP1_CLK_ENB, USBH_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "usbh_clk", NULL); - - clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, - 1); - clk_register_clkdev(clk, "usbh.0_clk", NULL); - - clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, - 1); - clk_register_clkdev(clk, "usbh.1_clk", NULL); - - clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, - PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "designware_udc"); - - /* clock derived from ahb clk */ - clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, - 1); - clk_register_clkdev(clk, "ahbmult2_clk", NULL); - - clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, - ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, - MCTR_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "ddr_clk", NULL); - - clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", - CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, - PCLK_RATIO_MASK, 0, &_lock); - clk_register_clkdev(clk, "apb_clk", NULL); - - clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, - AMEM_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "amem_clk", NULL); - - clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - C3_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "c3_clk"); - - clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - DMA_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc400000.dma"); - - clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - GMAC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "e0800000.eth"); - - clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - I2C_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0180000.i2c"); - - clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - JPEG_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "jpeg"); - - clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - SMI_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc000000.flash"); - - /* clock derived from apb clk */ - clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, - ADC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "adc"); - - clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, - GPIO_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc980000.gpio"); - - clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, - SSP_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0100000.spi"); - - /* RAS clk enable */ - clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, - RAS_AHB_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_ahb_clk", NULL); - - clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, - RAS_APB_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_apb_clk", NULL); - - clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, - RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_32k_clk", NULL); - - clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, - RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_24m_clk", NULL); - - clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, - RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_pll1_clk", NULL); - - clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, - RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_pll2_clk", NULL); - - clk = clk_register_gate(NULL, "ras_pll3_48m_clk", "pll3_48m_clk", 0, - RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_pll3_48m_clk", NULL); - - clk = clk_register_gate(NULL, "ras_gen0_synth_gate_clk", - "gen0_synth_gate_clk", 0, RAS_CLK_ENB, - RAS_SYNT0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_gen0_synth_gate_clk", NULL); - - clk = clk_register_gate(NULL, "ras_gen1_synth_gate_clk", - "gen1_synth_gate_clk", 0, RAS_CLK_ENB, - RAS_SYNT1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_gen1_synth_gate_clk", NULL); - - clk = clk_register_gate(NULL, "ras_gen2_synth_gate_clk", - "gen2_synth_gate_clk", 0, RAS_CLK_ENB, - RAS_SYNT2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_gen2_synth_gate_clk", NULL); - - clk = clk_register_gate(NULL, "ras_gen3_synth_gate_clk", - "gen3_synth_gate_clk", 0, RAS_CLK_ENB, - RAS_SYNT3_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, "ras_gen3_synth_gate_clk", NULL); - - if (of_machine_is_compatible("st,spear300")) - spear300_clk_init(); - else if (of_machine_is_compatible("st,spear310")) - spear310_clk_init(); - else if (of_machine_is_compatible("st,spear320")) - spear320_clk_init(); -} diff --git a/trunk/drivers/clk/spear/spear6xx_clock.c b/trunk/drivers/clk/spear/spear6xx_clock.c deleted file mode 100644 index f9a20b382304..000000000000 --- a/trunk/drivers/clk/spear/spear6xx_clock.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * SPEAr6xx machines clock framework source file - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "clk.h" - -static DEFINE_SPINLOCK(_lock); - -#define PLL1_CTR (MISC_BASE + 0x008) -#define PLL1_FRQ (MISC_BASE + 0x00C) -#define PLL2_CTR (MISC_BASE + 0x014) -#define PLL2_FRQ (MISC_BASE + 0x018) -#define PLL_CLK_CFG (MISC_BASE + 0x020) - /* PLL_CLK_CFG register masks */ - #define MCTR_CLK_SHIFT 28 - #define MCTR_CLK_MASK 3 - -#define CORE_CLK_CFG (MISC_BASE + 0x024) - /* CORE CLK CFG register masks */ - #define HCLK_RATIO_SHIFT 10 - #define HCLK_RATIO_MASK 2 - #define PCLK_RATIO_SHIFT 8 - #define PCLK_RATIO_MASK 2 - -#define PERIP_CLK_CFG (MISC_BASE + 0x028) - /* PERIP_CLK_CFG register masks */ - #define CLCD_CLK_SHIFT 2 - #define CLCD_CLK_MASK 2 - #define UART_CLK_SHIFT 4 - #define UART_CLK_MASK 1 - #define FIRDA_CLK_SHIFT 5 - #define FIRDA_CLK_MASK 2 - #define GPT0_CLK_SHIFT 8 - #define GPT1_CLK_SHIFT 10 - #define GPT2_CLK_SHIFT 11 - #define GPT3_CLK_SHIFT 12 - #define GPT_CLK_MASK 1 - -#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) - /* PERIP1_CLK_ENB register masks */ - #define UART0_CLK_ENB 3 - #define UART1_CLK_ENB 4 - #define SSP0_CLK_ENB 5 - #define SSP1_CLK_ENB 6 - #define I2C_CLK_ENB 7 - #define JPEG_CLK_ENB 8 - #define FSMC_CLK_ENB 9 - #define FIRDA_CLK_ENB 10 - #define GPT2_CLK_ENB 11 - #define GPT3_CLK_ENB 12 - #define GPIO2_CLK_ENB 13 - #define SSP2_CLK_ENB 14 - #define ADC_CLK_ENB 15 - #define GPT1_CLK_ENB 11 - #define RTC_CLK_ENB 17 - #define GPIO1_CLK_ENB 18 - #define DMA_CLK_ENB 19 - #define SMI_CLK_ENB 21 - #define CLCD_CLK_ENB 22 - #define GMAC_CLK_ENB 23 - #define USBD_CLK_ENB 24 - #define USBH0_CLK_ENB 25 - #define USBH1_CLK_ENB 26 - -#define PRSC0_CLK_CFG (MISC_BASE + 0x044) -#define PRSC1_CLK_CFG (MISC_BASE + 0x048) -#define PRSC2_CLK_CFG (MISC_BASE + 0x04C) - -#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) -#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) -#define UART_CLK_SYNT (MISC_BASE + 0x064) - -/* vco rate configuration table, in ascending order of rates */ -static struct pll_rate_tbl pll_rtbl[] = { - {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */ - {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */ - {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */ -}; - -/* aux rate configuration table, in ascending order of rates */ -static struct aux_rate_tbl aux_rtbl[] = { - /* For PLL1 = 332 MHz */ - {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ - {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ - {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ -}; - -static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", }; -static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", -}; -static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; -static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", }; -static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; -static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", }; -static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", - "pll2_clk", }; - -/* gpt rate configuration table, in ascending order of rates */ -static struct gpt_rate_tbl gpt_rtbl[] = { - /* For pll1 = 332 MHz */ - {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ - {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ - {.mscale = 1, .nscale = 0}, /* 83 MHz */ -}; - -void __init spear6xx_clk_init(void) -{ - struct clk *clk, *clk1; - - clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); - clk_register_clkdev(clk, "apb_pclk", NULL); - - clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, - 32000); - clk_register_clkdev(clk, "osc_32k_clk", NULL); - - clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, - 30000000); - clk_register_clkdev(clk, "osc_30m_clk", NULL); - - /* clock derived from 32 KHz osc clk */ - clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, - PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "rtc-spear"); - - /* clock derived from 30 MHz osc clk */ - clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, - 48000000); - clk_register_clkdev(clk, "pll3_48m_clk", NULL); - - clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", - 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), - &_lock, &clk1, NULL); - clk_register_clkdev(clk, "vco1_clk", NULL); - clk_register_clkdev(clk1, "pll1_clk", NULL); - - clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, - "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, - ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); - clk_register_clkdev(clk, "vco2_clk", NULL); - clk_register_clkdev(clk1, "pll2_clk", NULL); - - clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, - 1); - clk_register_clkdev(clk, NULL, "wdt"); - - /* clock derived from pll1 clk */ - clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); - clk_register_clkdev(clk, "cpu_clk", NULL); - - clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", - CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, - HCLK_RATIO_MASK, 0, &_lock); - clk_register_clkdev(clk, "ahb_clk", NULL); - - clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", - "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "uart_synth_clk", NULL); - clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents, - ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, - UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "uart_mux_clk", NULL); - - clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0, - PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0000000.serial"); - - clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0, - PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0080000.serial"); - - clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", - "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "firda_synth_clk", NULL); - clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, - ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, - FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "firda_mux_clk", NULL); - - clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, - PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "firda"); - - clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk", - "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, - ARRAY_SIZE(aux_rtbl), &_lock, &clk1); - clk_register_clkdev(clk, "clcd_synth_clk", NULL); - clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL); - - clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents, - ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, - CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "clcd_mux_clk", NULL); - - clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0, - PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "clcd"); - - /* gpt clocks */ - clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL); - - clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents, - ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, - GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt0"); - - clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents, - ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, - GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "gpt1_mux_clk", NULL); - - clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, - PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt1"); - - clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk_register_clkdev(clk, "gpt2_synth_clk", NULL); - - clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, - ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, - GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "gpt2_mux_clk", NULL); - - clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, - PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt2"); - - clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, - gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); - clk_register_clkdev(clk, "gpt3_synth_clk", NULL); - - clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents, - ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, - GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); - clk_register_clkdev(clk, "gpt3_mux_clk", NULL); - - clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, - PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gpt3"); - - /* clock derived from pll3 clk */ - clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0, - PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "usbh.0_clk"); - - clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0, - PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "usbh.1_clk"); - - clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, - PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "designware_udc"); - - /* clock derived from ahb clk */ - clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, - 1); - clk_register_clkdev(clk, "ahbmult2_clk", NULL); - - clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, - ARRAY_SIZE(ddr_parents), - 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, - &_lock); - clk_register_clkdev(clk, "ddr_clk", NULL); - - clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", - CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, - PCLK_RATIO_MASK, 0, &_lock); - clk_register_clkdev(clk, "apb_clk", NULL); - - clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - DMA_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc400000.dma"); - - clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - FSMC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d1800000.flash"); - - clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - GMAC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "gmac"); - - clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - I2C_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d0200000.i2c"); - - clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - JPEG_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "jpeg"); - - clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, - SMI_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc000000.flash"); - - /* clock derived from apb clk */ - clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, - ADC_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "adc"); - - clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); - clk_register_clkdev(clk, NULL, "f0100000.gpio"); - - clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, - GPIO1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "fc980000.gpio"); - - clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, - GPIO2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "d8100000.gpio"); - - clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, - SSP0_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.0"); - - clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, - SSP1_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.1"); - - clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, - SSP2_CLK_ENB, 0, &_lock); - clk_register_clkdev(clk, NULL, "ssp-pl022.2"); -} diff --git a/trunk/drivers/crypto/ixp4xx_crypto.c b/trunk/drivers/crypto/ixp4xx_crypto.c index 8f3f74ce8c7f..0053d7ebb5ca 100644 --- a/trunk/drivers/crypto/ixp4xx_crypto.c +++ b/trunk/drivers/crypto/ixp4xx_crypto.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include diff --git a/trunk/drivers/crypto/talitos.c b/trunk/drivers/crypto/talitos.c index 921039e56f87..dc641c796526 100644 --- a/trunk/drivers/crypto/talitos.c +++ b/trunk/drivers/crypto/talitos.c @@ -124,9 +124,6 @@ struct talitos_private { void __iomem *reg; int irq[2]; - /* SEC global registers lock */ - spinlock_t reg_lock ____cacheline_aligned; - /* SEC version geometry (from device tree node) */ unsigned int num_channels; unsigned int chfifo_len; @@ -415,7 +412,6 @@ static void talitos_done_##name(unsigned long data) \ { \ struct device *dev = (struct device *)data; \ struct talitos_private *priv = dev_get_drvdata(dev); \ - unsigned long flags; \ \ if (ch_done_mask & 1) \ flush_channel(dev, 0, 0, 0); \ @@ -431,10 +427,8 @@ static void talitos_done_##name(unsigned long data) \ out: \ /* At this point, all completed channels have been processed */ \ /* Unmask done interrupts for channels completed later on. */ \ - spin_lock_irqsave(&priv->reg_lock, flags); \ setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \ - spin_unlock_irqrestore(&priv->reg_lock, flags); \ } DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE) DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE) @@ -625,28 +619,22 @@ static irqreturn_t talitos_interrupt_##name(int irq, void *data) \ struct device *dev = data; \ struct talitos_private *priv = dev_get_drvdata(dev); \ u32 isr, isr_lo; \ - unsigned long flags; \ \ - spin_lock_irqsave(&priv->reg_lock, flags); \ isr = in_be32(priv->reg + TALITOS_ISR); \ isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \ /* Acknowledge interrupt */ \ out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \ out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \ \ - if (unlikely(isr & ch_err_mask || isr_lo)) { \ - spin_unlock_irqrestore(&priv->reg_lock, flags); \ - talitos_error(dev, isr & ch_err_mask, isr_lo); \ - } \ - else { \ + if (unlikely((isr & ~TALITOS_ISR_4CHDONE) & ch_err_mask || isr_lo)) \ + talitos_error(dev, isr, isr_lo); \ + else \ if (likely(isr & ch_done_mask)) { \ /* mask further done interrupts. */ \ clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \ /* done_task will unmask done interrupts at exit */ \ tasklet_schedule(&priv->done_task[tlet]); \ } \ - spin_unlock_irqrestore(&priv->reg_lock, flags); \ - } \ \ return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \ IRQ_NONE; \ @@ -2731,8 +2719,6 @@ static int talitos_probe(struct platform_device *ofdev) priv->ofdev = ofdev; - spin_lock_init(&priv->reg_lock); - err = talitos_probe_irq(ofdev); if (err) goto err_out; diff --git a/trunk/drivers/dma/Kconfig b/trunk/drivers/dma/Kconfig index ef378b5b17e4..cf9da362d64f 100644 --- a/trunk/drivers/dma/Kconfig +++ b/trunk/drivers/dma/Kconfig @@ -91,10 +91,11 @@ config DW_DMAC config AT_HDMAC tristate "Atmel AHB DMA support" - depends on ARCH_AT91 + depends on ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 select DMA_ENGINE help - Support the Atmel AHB DMA controller. + Support the Atmel AHB DMA controller. This can be integrated in + chips such as the Atmel AT91SAM9RL. config FSL_DMA tristate "Freescale Elo and Elo Plus DMA support" diff --git a/trunk/drivers/gpu/drm/drm_bufs.c b/trunk/drivers/gpu/drm/drm_bufs.c index 348b367debeb..30372f7b2d45 100644 --- a/trunk/drivers/gpu/drm/drm_bufs.c +++ b/trunk/drivers/gpu/drm/drm_bufs.c @@ -1510,8 +1510,8 @@ int drm_freebufs(struct drm_device *dev, void *data, * \param arg pointer to a drm_buf_map structure. * \return zero on success or a negative number on failure. * - * Maps the AGP, SG or PCI buffer region with vm_mmap(), and copies information - * about each buffer into user space. For PCI buffers, it calls vm_mmap() with + * Maps the AGP, SG or PCI buffer region with do_mmap(), and copies information + * about each buffer into user space. For PCI buffers, it calls do_mmap() with * offset equal to 0, which drm_mmap() interpretes as PCI buffers and calls * drm_mmap_dma(). */ @@ -1553,14 +1553,18 @@ int drm_mapbufs(struct drm_device *dev, void *data, retcode = -EINVAL; goto done; } - virtual = vm_mmap(file_priv->filp, 0, map->size, + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(file_priv->filp, 0, map->size, PROT_READ | PROT_WRITE, MAP_SHARED, token); + up_write(¤t->mm->mmap_sem); } else { - virtual = vm_mmap(file_priv->filp, 0, dma->byte_count, + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(file_priv->filp, 0, dma->byte_count, PROT_READ | PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); } if (virtual > -1024UL) { /* Real error */ diff --git a/trunk/drivers/gpu/drm/drm_crtc.c b/trunk/drivers/gpu/drm/drm_crtc.c index c79870a75c2f..d3aaeb6ae236 100644 --- a/trunk/drivers/gpu/drm/drm_crtc.c +++ b/trunk/drivers/gpu/drm/drm_crtc.c @@ -3335,12 +3335,10 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, ret = crtc->funcs->page_flip(crtc, fb, e); if (ret) { - if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) { - spin_lock_irqsave(&dev->event_lock, flags); - file_priv->event_space += sizeof e->event; - spin_unlock_irqrestore(&dev->event_lock, flags); - kfree(e); - } + spin_lock_irqsave(&dev->event_lock, flags); + file_priv->event_space += sizeof e->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + kfree(e); } out: diff --git a/trunk/drivers/gpu/drm/drm_fops.c b/trunk/drivers/gpu/drm/drm_fops.c index 123de28f94ef..cdfbf27b2b3c 100644 --- a/trunk/drivers/gpu/drm/drm_fops.c +++ b/trunk/drivers/gpu/drm/drm_fops.c @@ -507,12 +507,12 @@ int drm_release(struct inode *inode, struct file *filp) drm_events_release(file_priv); - if (dev->driver->driver_features & DRIVER_MODESET) - drm_fb_release(file_priv); - if (dev->driver->driver_features & DRIVER_GEM) drm_gem_release(dev, file_priv); + if (dev->driver->driver_features & DRIVER_MODESET) + drm_fb_release(file_priv); + mutex_lock(&dev->ctxlist_mutex); if (!list_empty(&dev->ctxlist)) { struct drm_ctx_list *pos, *n; diff --git a/trunk/drivers/gpu/drm/drm_usb.c b/trunk/drivers/gpu/drm/drm_usb.c index 37c9a523dd1c..c8c83dad2ce1 100644 --- a/trunk/drivers/gpu/drm/drm_usb.c +++ b/trunk/drivers/gpu/drm/drm_usb.c @@ -1,6 +1,6 @@ #include "drmP.h" #include -#include +#include int drm_get_usb_dev(struct usb_interface *interface, const struct usb_device_id *id, @@ -114,7 +114,3 @@ void drm_usb_exit(struct drm_driver *driver, usb_deregister(udriver); } EXPORT_SYMBOL(drm_usb_exit); - -MODULE_AUTHOR("David Airlie"); -MODULE_DESCRIPTION("USB DRM support"); -MODULE_LICENSE("GPL and additional rights"); diff --git a/trunk/drivers/gpu/drm/exynos/exynos_drm_gem.c b/trunk/drivers/gpu/drm/exynos/exynos_drm_gem.c index 392ce71ed6a1..26d51979116b 100644 --- a/trunk/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/trunk/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -581,8 +581,10 @@ int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data, obj->filp->f_op = &exynos_drm_gem_fops; obj->filp->private_data = obj; - addr = vm_mmap(obj->filp, 0, args->size, + down_write(¤t->mm->mmap_sem); + addr = do_mmap(obj->filp, 0, args->size, PROT_READ | PROT_WRITE, MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); drm_gem_object_unreference_unlocked(obj); diff --git a/trunk/drivers/gpu/drm/gma500/mdfld_dsi_output.h b/trunk/drivers/gpu/drm/gma500/mdfld_dsi_output.h index 36eb0744841c..21071cef92a4 100644 --- a/trunk/drivers/gpu/drm/gma500/mdfld_dsi_output.h +++ b/trunk/drivers/gpu/drm/gma500/mdfld_dsi_output.h @@ -29,6 +29,7 @@ #define __MDFLD_DSI_OUTPUT_H__ #include +#include #include #include #include diff --git a/trunk/drivers/gpu/drm/i810/i810_dma.c b/trunk/drivers/gpu/drm/i810/i810_dma.c index f920fb5e42b6..2c8a60c3b98e 100644 --- a/trunk/drivers/gpu/drm/i810/i810_dma.c +++ b/trunk/drivers/gpu/drm/i810/i810_dma.c @@ -129,7 +129,6 @@ static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv) if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; - /* This is all entirely broken */ down_write(¤t->mm->mmap_sem); old_fops = file_priv->filp->f_op; file_priv->filp->f_op = &i810_buffer_fops; @@ -158,8 +157,11 @@ static int i810_unmap_buffer(struct drm_buf *buf) if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EINVAL; - retcode = vm_munmap((unsigned long)buf_priv->virtual, + down_write(¤t->mm->mmap_sem); + retcode = do_munmap(current->mm, + (unsigned long)buf_priv->virtual, (size_t) buf->total); + up_write(¤t->mm->mmap_sem); buf_priv->currently_mapped = I810_BUF_UNMAPPED; buf_priv->virtual = NULL; diff --git a/trunk/drivers/gpu/drm/i915/i915_gem.c b/trunk/drivers/gpu/drm/i915/i915_gem.c index 0d1e4b7b4b99..0e3c6acde955 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem.c @@ -1087,9 +1087,11 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, if (obj == NULL) return -ENOENT; - addr = vm_mmap(obj->filp, 0, args->size, + down_write(¤t->mm->mmap_sem); + addr = do_mmap(obj->filp, 0, args->size, PROT_READ | PROT_WRITE, MAP_SHARED, args->offset); + up_write(¤t->mm->mmap_sem); drm_gem_object_unreference_unlocked(obj); if (IS_ERR((void *)addr)) return addr; diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 5908cd563400..bae38acf44dc 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -3478,11 +3478,8 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, return false; } - /* All interlaced capable intel hw wants timings in frames. Note though - * that intel_lvds_mode_fixup does some funny tricks with the crtc - * timings, so we need to be careful not to clobber these.*/ - if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) - drm_mode_set_crtcinfo(adjusted_mode, 0); + /* All interlaced capable intel hw wants timings in frames. */ + drm_mode_set_crtcinfo(adjusted_mode, 0); return true; } @@ -7468,13 +7465,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev, OUT_RING(fb->pitches[0] | obj->tiling_mode); OUT_RING(obj->gtt_offset); - /* Contrary to the suggestions in the documentation, - * "Enable Panel Fitter" does not seem to be required when page - * flipping with a non-native mode, and worse causes a normal - * modeset to fail. - * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; - */ - pf = 0; + pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); ADVANCE_LP_RING(); diff --git a/trunk/drivers/gpu/drm/i915/intel_drv.h b/trunk/drivers/gpu/drm/i915/intel_drv.h index 715afa153025..5a14149b3794 100644 --- a/trunk/drivers/gpu/drm/i915/intel_drv.h +++ b/trunk/drivers/gpu/drm/i915/intel_drv.h @@ -105,10 +105,6 @@ #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) #define INTEL_MODE_DP_FORCE_6BPC (0x10) -/* This flag must be set by the encoder's mode_fixup if it changes the crtc - * timings in the mode to prevent the crtc fixup from overwriting them. - * Currently only lvds needs that. */ -#define INTEL_MODE_CRTC_TIMINGS_SET (0x20) static inline void intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, diff --git a/trunk/drivers/gpu/drm/i915/intel_fb.c b/trunk/drivers/gpu/drm/i915/intel_fb.c index 6e9ee33fd412..19ecd78b8a2c 100644 --- a/trunk/drivers/gpu/drm/i915/intel_fb.c +++ b/trunk/drivers/gpu/drm/i915/intel_fb.c @@ -279,8 +279,6 @@ void intel_fb_restore_mode(struct drm_device *dev) struct drm_mode_config *config = &dev->mode_config; struct drm_plane *plane; - mutex_lock(&dev->mode_config.mutex); - ret = drm_fb_helper_restore_fbdev_mode(&dev_priv->fbdev->helper); if (ret) DRM_DEBUG("failed to restore crtc mode\n"); @@ -288,6 +286,4 @@ void intel_fb_restore_mode(struct drm_device *dev) /* Be sure to shut off any planes that may be active */ list_for_each_entry(plane, &config->plane_list, head) plane->funcs->disable_plane(plane); - - mutex_unlock(&dev->mode_config.mutex); } diff --git a/trunk/drivers/gpu/drm/i915/intel_lvds.c b/trunk/drivers/gpu/drm/i915/intel_lvds.c index 30e2c82101de..95db2e988227 100644 --- a/trunk/drivers/gpu/drm/i915/intel_lvds.c +++ b/trunk/drivers/gpu/drm/i915/intel_lvds.c @@ -187,8 +187,6 @@ centre_horizontally(struct drm_display_mode *mode, mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; - - mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; } static void @@ -210,8 +208,6 @@ centre_vertically(struct drm_display_mode *mode, mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; - - mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; } static inline u32 panel_fitter_scaling(u32 source, u32 target) @@ -287,8 +283,6 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, for_each_pipe(pipe) I915_WRITE(BCLRPAT(pipe), 0); - drm_mode_set_crtcinfo(adjusted_mode, 0); - switch (intel_lvds->fitting_mode) { case DRM_MODE_SCALE_CENTER: /* diff --git a/trunk/drivers/gpu/drm/i915/intel_panel.c b/trunk/drivers/gpu/drm/i915/intel_panel.c index 48177ec4720e..230a141dbea3 100644 --- a/trunk/drivers/gpu/drm/i915/intel_panel.c +++ b/trunk/drivers/gpu/drm/i915/intel_panel.c @@ -47,6 +47,8 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, adjusted_mode->vtotal = fixed_mode->vtotal; adjusted_mode->clock = fixed_mode->clock; + + drm_mode_set_crtcinfo(adjusted_mode, 0); } /* adjusted_mode has been preset to be the panel's fixed mode */ diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c index da3e7c3abab7..34d591b7d4ef 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_pm.c @@ -235,7 +235,6 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) return -EPERM; strncpy(string, profile, sizeof(string)); - string[sizeof(string) - 1] = 0; if ((ptr = strchr(string, '\n'))) *ptr = '\0'; diff --git a/trunk/drivers/gpu/drm/nouveau/nv50_sor.c b/trunk/drivers/gpu/drm/nouveau/nv50_sor.c index 274640212475..a7844ab6a50c 100644 --- a/trunk/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/trunk/drivers/gpu/drm/nouveau/nv50_sor.c @@ -42,7 +42,7 @@ nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) struct drm_nouveau_private *dev_priv = dev->dev_private; static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ static const u8 nv50[] = { 16, 8, 0, 24 }; - if (dev_priv->chipset == 0xaf) + if (dev_priv->card_type == 0xaf) return nvaf[lane]; return nv50[lane]; } diff --git a/trunk/drivers/gpu/drm/radeon/r600.c b/trunk/drivers/gpu/drm/radeon/r600.c index c8187c4b6ae8..de71243b591f 100644 --- a/trunk/drivers/gpu/drm/radeon/r600.c +++ b/trunk/drivers/gpu/drm/radeon/r600.c @@ -1135,7 +1135,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; - size_af = 0xFFFFFFFF - mc->gtt_end; + size_af = 0xFFFFFFFF - mc->gtt_end + 1; if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); @@ -1149,7 +1149,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } - mc->vram_start = mc->gtt_end + 1; + mc->vram_start = mc->gtt_end; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", diff --git a/trunk/drivers/gpu/drm/radeon/radeon_connectors.c b/trunk/drivers/gpu/drm/radeon/radeon_connectors.c index 3c2e7a000a2a..bd05156edbdb 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_connectors.c @@ -970,7 +970,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) encoder = obj_to_encoder(obj); - if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && + if (encoder->encoder_type != DRM_MODE_ENCODER_DAC || encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1000,7 +1000,6 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) * cases the DVI port is actually a virtual KVM port connected to the service * processor. */ -out: if ((!rdev->is_atom_bios) && (ret == connector_status_disconnected) && rdev->mode_info.bios_hardcoded_edid_size) { @@ -1008,6 +1007,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) ret = connector_status_connected; } +out: /* updated in get modes as well since we need to know if it's analog or digital */ radeon_connector_update_scratch_regs(connector, ret); return ret; diff --git a/trunk/drivers/gpu/drm/radeon/radeon_irq_kms.c b/trunk/drivers/gpu/drm/radeon/radeon_irq_kms.c index 65060b77c805..66d5fe1c8174 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -147,12 +147,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev) (rdev->pdev->subsystem_device == 0x01fd)) return true; - /* RV515 seems to have MSI issues where it loses - * MSI rearms occasionally. This leads to lockups and freezes. - * disable it by default. - */ - if (rdev->family == CHIP_RV515) - return false; if (rdev->flags & RADEON_IS_IGP) { /* APUs work fine with MSIs */ if (rdev->family >= CHIP_PALM) diff --git a/trunk/drivers/gpu/drm/radeon/rv770.c b/trunk/drivers/gpu/drm/radeon/rv770.c index cdab1aeaed6e..c62ae4be3845 100644 --- a/trunk/drivers/gpu/drm/radeon/rv770.c +++ b/trunk/drivers/gpu/drm/radeon/rv770.c @@ -969,7 +969,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; - size_af = 0xFFFFFFFF - mc->gtt_end; + size_af = 0xFFFFFFFF - mc->gtt_end + 1; if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); @@ -983,7 +983,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } - mc->vram_start = mc->gtt_end + 1; + mc->vram_start = mc->gtt_end; } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", diff --git a/trunk/drivers/gpu/drm/radeon/si.c b/trunk/drivers/gpu/drm/radeon/si.c index 27bda986fc2b..ac7a199ffece 100644 --- a/trunk/drivers/gpu/drm/radeon/si.c +++ b/trunk/drivers/gpu/drm/radeon/si.c @@ -2999,8 +2999,8 @@ int si_rlc_init(struct radeon_device *rdev) } r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.save_restore_gpu_addr); - radeon_bo_unreserve(rdev->rlc.save_restore_obj); if (r) { + radeon_bo_unreserve(rdev->rlc.save_restore_obj); dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); si_rlc_fini(rdev); return r; @@ -3023,8 +3023,9 @@ int si_rlc_init(struct radeon_device *rdev) } r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, &rdev->rlc.clear_state_gpu_addr); - radeon_bo_unreserve(rdev->rlc.clear_state_obj); if (r) { + + radeon_bo_unreserve(rdev->rlc.clear_state_obj); dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); si_rlc_fini(rdev); return r; diff --git a/trunk/drivers/hid/Kconfig b/trunk/drivers/hid/Kconfig index ffddcba32af6..a3d033252995 100644 --- a/trunk/drivers/hid/Kconfig +++ b/trunk/drivers/hid/Kconfig @@ -34,7 +34,7 @@ config HID config HID_BATTERY_STRENGTH bool depends on HID && POWER_SUPPLY && HID = POWER_SUPPLY - default n + default y config HIDRAW bool "/dev/hidraw raw HID device support" diff --git a/trunk/drivers/hid/hid-tivo.c b/trunk/drivers/hid/hid-tivo.c index 9f85f827607f..de47039c708c 100644 --- a/trunk/drivers/hid/hid-tivo.c +++ b/trunk/drivers/hid/hid-tivo.c @@ -62,7 +62,7 @@ static int tivo_input_mapping(struct hid_device *hdev, struct hid_input *hi, static const struct hid_device_id tivo_devices[] = { /* TiVo Slide Bluetooth remote, pairs with a Broadcom dongle */ - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) }, + { HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE_BT) }, { HID_USB_DEVICE(USB_VENDOR_ID_TIVO, USB_DEVICE_ID_TIVO_SLIDE) }, { } }; diff --git a/trunk/drivers/hwmon/ads1015.c b/trunk/drivers/hwmon/ads1015.c index 1958f03efd7a..7765e4f74ec5 100644 --- a/trunk/drivers/hwmon/ads1015.c +++ b/trunk/drivers/hwmon/ads1015.c @@ -59,11 +59,14 @@ struct ads1015_data { struct ads1015_channel_data channel_data[ADS1015_CHANNELS]; }; -static int ads1015_read_adc(struct i2c_client *client, unsigned int channel) +static int ads1015_read_value(struct i2c_client *client, unsigned int channel, + int *value) { u16 config; + s16 conversion; struct ads1015_data *data = i2c_get_clientdata(client); unsigned int pga = data->channel_data[channel].pga; + int fullscale; unsigned int data_rate = data->channel_data[channel].data_rate; unsigned int conversion_time_ms; int res; @@ -75,6 +78,7 @@ static int ads1015_read_adc(struct i2c_client *client, unsigned int channel) if (res < 0) goto err_unlock; config = res; + fullscale = fullscale_table[pga]; conversion_time_ms = DIV_ROUND_UP(1000, data_rate_table[data_rate]); /* setup and start single conversion */ @@ -101,20 +105,19 @@ static int ads1015_read_adc(struct i2c_client *client, unsigned int channel) } res = i2c_smbus_read_word_swapped(client, ADS1015_CONVERSION); + if (res < 0) + goto err_unlock; + conversion = res; -err_unlock: mutex_unlock(&data->update_lock); - return res; -} -static int ads1015_reg_to_mv(struct i2c_client *client, unsigned int channel, - s16 reg) -{ - struct ads1015_data *data = i2c_get_clientdata(client); - unsigned int pga = data->channel_data[channel].pga; - int fullscale = fullscale_table[pga]; + *value = DIV_ROUND_CLOSEST(conversion * fullscale, 0x7ff0); + + return 0; - return DIV_ROUND_CLOSEST(reg * fullscale, 0x7ff0); +err_unlock: + mutex_unlock(&data->update_lock); + return res; } /* sysfs callback function */ @@ -123,14 +126,12 @@ static ssize_t show_in(struct device *dev, struct device_attribute *da, { struct sensor_device_attribute *attr = to_sensor_dev_attr(da); struct i2c_client *client = to_i2c_client(dev); + int in; int res; - int index = attr->index; - res = ads1015_read_adc(client, index); - if (res < 0) - return res; + res = ads1015_read_value(client, attr->index, &in); - return sprintf(buf, "%d\n", ads1015_reg_to_mv(client, index, res)); + return (res < 0) ? res : sprintf(buf, "%d\n", in); } static const struct sensor_device_attribute ads1015_in[] = { diff --git a/trunk/drivers/hwmon/fam15h_power.c b/trunk/drivers/hwmon/fam15h_power.c index 37a8fc92b44a..b7494af1e4a9 100644 --- a/trunk/drivers/hwmon/fam15h_power.c +++ b/trunk/drivers/hwmon/fam15h_power.c @@ -122,38 +122,6 @@ static bool __devinit fam15h_power_is_internal_node0(struct pci_dev *f4) return true; } -/* - * Newer BKDG versions have an updated recommendation on how to properly - * initialize the running average range (was: 0xE, now: 0x9). This avoids - * counter saturations resulting in bogus power readings. - * We correct this value ourselves to cope with older BIOSes. - */ -static void __devinit tweak_runavg_range(struct pci_dev *pdev) -{ - u32 val; - const struct pci_device_id affected_device = { - PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) }; - - /* - * let this quirk apply only to the current version of the - * northbridge, since future versions may change the behavior - */ - if (!pci_match_id(&affected_device, pdev)) - return; - - pci_bus_read_config_dword(pdev->bus, - PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), - REG_TDP_RUNNING_AVERAGE, &val); - if ((val & 0xf) != 0xe) - return; - - val &= ~0xf; - val |= 0x9; - pci_bus_write_config_dword(pdev->bus, - PCI_DEVFN(PCI_SLOT(pdev->devfn), 5), - REG_TDP_RUNNING_AVERAGE, val); -} - static void __devinit fam15h_power_init_data(struct pci_dev *f4, struct fam15h_power_data *data) { @@ -187,13 +155,6 @@ static int __devinit fam15h_power_probe(struct pci_dev *pdev, struct device *dev; int err; - /* - * though we ignore every other northbridge, we still have to - * do the tweaking on _each_ node in MCM processors as the counters - * are working hand-in-hand - */ - tweak_runavg_range(pdev); - if (!fam15h_power_is_internal_node0(pdev)) { err = -ENODEV; goto exit; diff --git a/trunk/drivers/input/misc/Kconfig b/trunk/drivers/input/misc/Kconfig index 7faf4a7fcaa9..2d787796bf50 100644 --- a/trunk/drivers/input/misc/Kconfig +++ b/trunk/drivers/input/misc/Kconfig @@ -380,7 +380,8 @@ config INPUT_TWL4030_VIBRA config INPUT_TWL6040_VIBRA tristate "Support for TWL6040 Vibrator" - depends on TWL6040_CORE + depends on TWL4030_CORE + select TWL6040_CORE select INPUT_FF_MEMLESS help This option enables support for TWL6040 Vibrator Driver. diff --git a/trunk/drivers/input/misc/twl6040-vibra.c b/trunk/drivers/input/misc/twl6040-vibra.c index 14e94f56cb7d..45874fed523a 100644 --- a/trunk/drivers/input/misc/twl6040-vibra.c +++ b/trunk/drivers/input/misc/twl6040-vibra.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include @@ -257,7 +257,7 @@ static SIMPLE_DEV_PM_OPS(twl6040_vibra_pm_ops, twl6040_vibra_suspend, NULL); static int __devinit twl6040_vibra_probe(struct platform_device *pdev) { - struct twl6040_vibra_data *pdata = pdev->dev.platform_data; + struct twl4030_vibra_data *pdata = pdev->dev.platform_data; struct vibra_info *info; int ret; diff --git a/trunk/drivers/leds/leds-atmel-pwm.c b/trunk/drivers/leds/leds-atmel-pwm.c index 64ad702a2ecc..800243b6037e 100644 --- a/trunk/drivers/leds/leds-atmel-pwm.c +++ b/trunk/drivers/leds/leds-atmel-pwm.c @@ -35,7 +35,7 @@ static void pwmled_brightness(struct led_classdev *cdev, enum led_brightness b) * NOTE: we reuse the platform_data structure of GPIO leds, * but repurpose its "gpio" number as a PWM channel number. */ -static int __devinit pwmled_probe(struct platform_device *pdev) +static int __init pwmled_probe(struct platform_device *pdev) { const struct gpio_led_platform_data *pdata; struct pwmled *leds; diff --git a/trunk/drivers/media/common/tuners/xc5000.c b/trunk/drivers/media/common/tuners/xc5000.c index eab2ea424200..7f98984e4fad 100644 --- a/trunk/drivers/media/common/tuners/xc5000.c +++ b/trunk/drivers/media/common/tuners/xc5000.c @@ -54,7 +54,6 @@ struct xc5000_priv { struct list_head hybrid_tuner_instance_list; u32 if_khz; - u32 xtal_khz; u32 freq_hz; u32 bandwidth; u8 video_standard; @@ -215,9 +214,9 @@ static const struct xc5000_fw_cfg xc5000a_1_6_114 = { .size = 12401, }; -static const struct xc5000_fw_cfg xc5000c_41_024_5 = { - .name = "dvb-fe-xc5000c-41.024.5.fw", - .size = 16497, +static const struct xc5000_fw_cfg xc5000c_41_024_5_31875 = { + .name = "dvb-fe-xc5000c-41.024.5-31875.fw", + .size = 16503, }; static inline const struct xc5000_fw_cfg *xc5000_assign_firmware(int chip_id) @@ -227,7 +226,7 @@ static inline const struct xc5000_fw_cfg *xc5000_assign_firmware(int chip_id) case XC5000A: return &xc5000a_1_6_114; case XC5000C: - return &xc5000c_41_024_5; + return &xc5000c_41_024_5_31875; } } @@ -573,31 +572,6 @@ static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz, int mode) return found; } -static int xc_set_xtal(struct dvb_frontend *fe) -{ - struct xc5000_priv *priv = fe->tuner_priv; - int ret = XC_RESULT_SUCCESS; - - switch (priv->chip_id) { - default: - case XC5000A: - /* 32.000 MHz xtal is default */ - break; - case XC5000C: - switch (priv->xtal_khz) { - default: - case 32000: - /* 32.000 MHz xtal is default */ - break; - case 31875: - /* 31.875 MHz xtal configuration */ - ret = xc_write_reg(priv, 0x000f, 0x8081); - break; - } - break; - } - return ret; -} static int xc5000_fwupload(struct dvb_frontend *fe) { @@ -629,8 +603,6 @@ static int xc5000_fwupload(struct dvb_frontend *fe) } else { printk(KERN_INFO "xc5000: firmware uploading...\n"); ret = xc_load_i2c_sequence(fe, fw->data); - if (XC_RESULT_SUCCESS == ret) - ret = xc_set_xtal(fe); printk(KERN_INFO "xc5000: firmware upload complete...\n"); } @@ -1192,9 +1164,6 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, priv->if_khz = cfg->if_khz; } - if (priv->xtal_khz == 0) - priv->xtal_khz = cfg->xtal_khz; - if (priv->radio_input == 0) priv->radio_input = cfg->radio_input; diff --git a/trunk/drivers/media/common/tuners/xc5000.h b/trunk/drivers/media/common/tuners/xc5000.h index 39a73bf01406..3396f8e02b40 100644 --- a/trunk/drivers/media/common/tuners/xc5000.h +++ b/trunk/drivers/media/common/tuners/xc5000.h @@ -34,7 +34,6 @@ struct xc5000_config { u8 i2c_address; u32 if_khz; u8 radio_input; - u32 xtal_khz; int chip_id; }; diff --git a/trunk/drivers/media/dvb/dvb-core/dvb_frontend.c b/trunk/drivers/media/dvb/dvb-core/dvb_frontend.c index 0f64d7182657..39696c6a4ed7 100644 --- a/trunk/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/trunk/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1446,28 +1446,6 @@ static int set_delivery_system(struct dvb_frontend *fe, u32 desired_system) __func__); return -EINVAL; } - /* - * Get a delivery system that is compatible with DVBv3 - * NOTE: in order for this to work with softwares like Kaffeine that - * uses a DVBv5 call for DVB-S2 and a DVBv3 call to go back to - * DVB-S, drivers that support both should put the SYS_DVBS entry - * before the SYS_DVBS2, otherwise it won't switch back to DVB-S. - * The real fix is that userspace applications should not use DVBv3 - * and not trust on calling FE_SET_FRONTEND to switch the delivery - * system. - */ - ncaps = 0; - while (fe->ops.delsys[ncaps] && ncaps < MAX_DELSYS) { - if (fe->ops.delsys[ncaps] == desired_system) { - delsys = desired_system; - break; - } - ncaps++; - } - if (delsys == SYS_UNDEFINED) { - dprintk("%s() Couldn't find a delivery system that matches %d\n", - __func__, desired_system); - } } else { /* * This is a DVBv5 call. So, it likely knows the supported @@ -1516,10 +1494,9 @@ static int set_delivery_system(struct dvb_frontend *fe, u32 desired_system) __func__); return -EINVAL; } + c->delivery_system = delsys; } - c->delivery_system = delsys; - /* * The DVBv3 or DVBv5 call is requesting a different system. So, * emulation is needed. diff --git a/trunk/drivers/media/dvb/frontends/drxk_hard.c b/trunk/drivers/media/dvb/frontends/drxk_hard.c index a414b1f2b6a5..36d11756492f 100644 --- a/trunk/drivers/media/dvb/frontends/drxk_hard.c +++ b/trunk/drivers/media/dvb/frontends/drxk_hard.c @@ -1520,10 +1520,8 @@ static int scu_command(struct drxk_state *state, dprintk(1, "\n"); if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || - ((resultLen > 0) && (result == NULL))) { - printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } + ((resultLen > 0) && (result == NULL))) + goto error; mutex_lock(&state->mutex); diff --git a/trunk/drivers/media/rc/winbond-cir.c b/trunk/drivers/media/rc/winbond-cir.c index af526586fa26..b09c5fae489b 100644 --- a/trunk/drivers/media/rc/winbond-cir.c +++ b/trunk/drivers/media/rc/winbond-cir.c @@ -1046,7 +1046,6 @@ wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) goto exit_unregister_led; } - data->dev->driver_type = RC_DRIVER_IR_RAW; data->dev->driver_name = WBCIR_NAME; data->dev->input_name = WBCIR_NAME; data->dev->input_phys = "wbcir/cir0"; diff --git a/trunk/drivers/media/video/Kconfig b/trunk/drivers/media/video/Kconfig index ce1e7ba940f6..f2479c5c0eb2 100644 --- a/trunk/drivers/media/video/Kconfig +++ b/trunk/drivers/media/video/Kconfig @@ -492,7 +492,7 @@ config VIDEO_VS6624 config VIDEO_MT9M032 tristate "MT9M032 camera sensor support" - depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API + depends on I2C && VIDEO_V4L2 select VIDEO_APTINA_PLL ---help--- This driver supports MT9M032 camera sensors from Aptina, monochrome diff --git a/trunk/drivers/media/video/mt9m032.c b/trunk/drivers/media/video/mt9m032.c index 645973c5feb0..7636672c3548 100644 --- a/trunk/drivers/media/video/mt9m032.c +++ b/trunk/drivers/media/video/mt9m032.c @@ -392,11 +392,10 @@ static int mt9m032_set_pad_format(struct v4l2_subdev *subdev, } /* Scaling is not supported, the format is thus fixed. */ - fmt->format = *__mt9m032_get_pad_format(sensor, fh, fmt->which); - ret = 0; + ret = mt9m032_get_pad_format(subdev, fh, fmt); done: - mutex_unlock(&sensor->lock); + mutex_lock(&sensor->lock); return ret; } diff --git a/trunk/drivers/mfd/Kconfig b/trunk/drivers/mfd/Kconfig index 11e44386fa9b..29f463cc09cb 100644 --- a/trunk/drivers/mfd/Kconfig +++ b/trunk/drivers/mfd/Kconfig @@ -268,17 +268,10 @@ config TWL6030_PWM This is used to control charging LED brightness. config TWL6040_CORE - bool "Support for TWL6040 audio codec" - depends on I2C=y && GENERIC_HARDIRQS + bool + depends on TWL4030_CORE && GENERIC_HARDIRQS select MFD_CORE - select REGMAP_I2C default n - help - Say yes here if you want support for Texas Instruments TWL6040 audio - codec. - This driver provides common support for accessing the device, - additional drivers must be enabled in order to use the - functionality of the device (audio, vibra). config MFD_STMPE bool "Support STMicroelectronics STMPE" diff --git a/trunk/drivers/mfd/asic3.c b/trunk/drivers/mfd/asic3.c index 1582c3d95257..1895cf9fab8c 100644 --- a/trunk/drivers/mfd/asic3.c +++ b/trunk/drivers/mfd/asic3.c @@ -527,9 +527,7 @@ static void asic3_gpio_set(struct gpio_chip *chip, static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset) { - struct asic3 *asic = container_of(chip, struct asic3, gpio); - - return (offset < ASIC3_NUM_GPIOS) ? asic->irq_base + offset : -ENXIO; + return (offset < ASIC3_NUM_GPIOS) ? IRQ_BOARD_START + offset : -ENXIO; } static __init int asic3_gpio_probe(struct platform_device *pdev, diff --git a/trunk/drivers/mfd/omap-usb-host.c b/trunk/drivers/mfd/omap-usb-host.c index c8aae6640e64..95a2e546a489 100644 --- a/trunk/drivers/mfd/omap-usb-host.c +++ b/trunk/drivers/mfd/omap-usb-host.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -501,6 +502,19 @@ static void omap_usbhs_init(struct device *dev) pm_runtime_get_sync(dev); spin_lock_irqsave(&omap->lock, flags); + if (pdata->ehci_data->phy_reset) { + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_request_one(pdata->ehci_data->reset_gpio_port[0], + GPIOF_OUT_INIT_LOW, "USB1 PHY reset"); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_request_one(pdata->ehci_data->reset_gpio_port[1], + GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); + + /* Hold the PHY in RESET for enough time till DIR is high */ + udelay(10); + } + omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); @@ -579,10 +593,39 @@ static void omap_usbhs_init(struct device *dev) usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); } + if (pdata->ehci_data->phy_reset) { + /* Hold the PHY in RESET for enough time till + * PHY is settled and ready + */ + udelay(10); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_set_value + (pdata->ehci_data->reset_gpio_port[0], 1); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_set_value + (pdata->ehci_data->reset_gpio_port[1], 1); + } + spin_unlock_irqrestore(&omap->lock, flags); pm_runtime_put_sync(dev); } +static void omap_usbhs_deinit(struct device *dev) +{ + struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); + struct usbhs_omap_platform_data *pdata = &omap->platdata; + + if (pdata->ehci_data->phy_reset) { + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) + gpio_free(pdata->ehci_data->reset_gpio_port[0]); + + if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) + gpio_free(pdata->ehci_data->reset_gpio_port[1]); + } +} + /** * usbhs_omap_probe - initialize TI-based HCDs @@ -817,6 +860,7 @@ static int __devexit usbhs_omap_remove(struct platform_device *pdev) { struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); + omap_usbhs_deinit(&pdev->dev); iounmap(omap->tll_base); iounmap(omap->uhh_base); clk_put(omap->init_60m_fclk); diff --git a/trunk/drivers/mfd/rc5t583.c b/trunk/drivers/mfd/rc5t583.c index 44afae0a69ce..99ef944c621d 100644 --- a/trunk/drivers/mfd/rc5t583.c +++ b/trunk/drivers/mfd/rc5t583.c @@ -80,6 +80,44 @@ static struct mfd_cell rc5t583_subdevs[] = { {.name = "rc5t583-key", } }; +int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) +{ + struct rc5t583 *rc5t583 = dev_get_drvdata(dev); + return regmap_write(rc5t583->regmap, reg, val); +} + +int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) +{ + struct rc5t583 *rc5t583 = dev_get_drvdata(dev); + unsigned int ival; + int ret; + ret = regmap_read(rc5t583->regmap, reg, &ival); + if (!ret) + *val = (uint8_t)ival; + return ret; +} + +int rc5t583_set_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask) +{ + struct rc5t583 *rc5t583 = dev_get_drvdata(dev); + return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask); +} + +int rc5t583_clear_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask) +{ + struct rc5t583 *rc5t583 = dev_get_drvdata(dev); + return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0); +} + +int rc5t583_update(struct device *dev, unsigned int reg, + unsigned int val, unsigned int mask) +{ + struct rc5t583 *rc5t583 = dev_get_drvdata(dev); + return regmap_update_bits(rc5t583->regmap, reg, mask, val); +} + static int __rc5t583_set_ext_pwrreq1_control(struct device *dev, int id, int ext_pwr, int slots) { @@ -159,7 +197,6 @@ int rc5t583_ext_power_req_config(struct device *dev, int ds_id, ds_id, ext_pwr_req); return 0; } -EXPORT_SYMBOL(rc5t583_ext_power_req_config); static int rc5t583_clear_ext_power_req(struct rc5t583 *rc5t583, struct rc5t583_platform_data *pdata) diff --git a/trunk/drivers/mfd/twl6040-core.c b/trunk/drivers/mfd/twl6040-core.c index 2d6bedadca09..b2d8e512d3cb 100644 --- a/trunk/drivers/mfd/twl6040-core.c +++ b/trunk/drivers/mfd/twl6040-core.c @@ -30,9 +30,7 @@ #include #include #include -#include -#include -#include +#include #include #include @@ -41,7 +39,7 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg) { int ret; - unsigned int val; + u8 val = 0; mutex_lock(&twl6040->io_mutex); /* Vibra control registers from cache */ @@ -49,7 +47,7 @@ int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg) reg == TWL6040_REG_VIBCTLR)) { val = twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)]; } else { - ret = regmap_read(twl6040->regmap, reg, &val); + ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); if (ret < 0) { mutex_unlock(&twl6040->io_mutex); return ret; @@ -66,7 +64,7 @@ int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val) int ret; mutex_lock(&twl6040->io_mutex); - ret = regmap_write(twl6040->regmap, reg, val); + ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); /* Cache the vibra control registers */ if (reg == TWL6040_REG_VIBCTLL || reg == TWL6040_REG_VIBCTLR) twl6040->vibra_ctrl_cache[VIBRACTRL_MEMBER(reg)] = val; @@ -79,9 +77,16 @@ EXPORT_SYMBOL(twl6040_reg_write); int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) { int ret; + u8 val; mutex_lock(&twl6040->io_mutex); - ret = regmap_update_bits(twl6040->regmap, reg, mask, mask); + ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); + if (ret) + goto out; + + val |= mask; + ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); +out: mutex_unlock(&twl6040->io_mutex); return ret; } @@ -90,9 +95,16 @@ EXPORT_SYMBOL(twl6040_set_bits); int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask) { int ret; + u8 val; mutex_lock(&twl6040->io_mutex); - ret = regmap_update_bits(twl6040->regmap, reg, mask, 0); + ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg); + if (ret) + goto out; + + val &= ~mask; + ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg); +out: mutex_unlock(&twl6040->io_mutex); return ret; } @@ -482,58 +494,32 @@ static struct resource twl6040_codec_rsrc[] = { }, }; -static bool twl6040_readable_reg(struct device *dev, unsigned int reg) +static int __devinit twl6040_probe(struct platform_device *pdev) { - /* Register 0 is not readable */ - if (!reg) - return false; - return true; -} - -static struct regmap_config twl6040_regmap_config = { - .reg_bits = 8, - .val_bits = 8, - .max_register = TWL6040_REG_STATUS, /* 0x2e */ - - .readable_reg = twl6040_readable_reg, -}; - -static int __devinit twl6040_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct twl6040_platform_data *pdata = client->dev.platform_data; + struct twl4030_audio_data *pdata = pdev->dev.platform_data; struct twl6040 *twl6040; struct mfd_cell *cell = NULL; int ret, children = 0; if (!pdata) { - dev_err(&client->dev, "Platform data is missing\n"); + dev_err(&pdev->dev, "Platform data is missing\n"); return -EINVAL; } /* In order to operate correctly we need valid interrupt config */ - if (!client->irq || !pdata->irq_base) { - dev_err(&client->dev, "Invalid IRQ configuration\n"); + if (!pdata->naudint_irq || !pdata->irq_base) { + dev_err(&pdev->dev, "Invalid IRQ configuration\n"); return -EINVAL; } - twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040), - GFP_KERNEL); - if (!twl6040) { - ret = -ENOMEM; - goto err; - } - - twl6040->regmap = regmap_init_i2c(client, &twl6040_regmap_config); - if (IS_ERR(twl6040->regmap)) { - ret = PTR_ERR(twl6040->regmap); - goto err; - } + twl6040 = kzalloc(sizeof(struct twl6040), GFP_KERNEL); + if (!twl6040) + return -ENOMEM; - i2c_set_clientdata(client, twl6040); + platform_set_drvdata(pdev, twl6040); - twl6040->dev = &client->dev; - twl6040->irq = client->irq; + twl6040->dev = &pdev->dev; + twl6040->irq = pdata->naudint_irq; twl6040->irq_base = pdata->irq_base; mutex_init(&twl6040->mutex); @@ -602,12 +588,12 @@ static int __devinit twl6040_probe(struct i2c_client *client, } if (children) { - ret = mfd_add_devices(&client->dev, -1, twl6040->cells, + ret = mfd_add_devices(&pdev->dev, pdev->id, twl6040->cells, children, NULL, 0); if (ret) goto mfd_err; } else { - dev_err(&client->dev, "No platform data found for children\n"); + dev_err(&pdev->dev, "No platform data found for children\n"); ret = -ENODEV; goto mfd_err; } @@ -622,15 +608,14 @@ static int __devinit twl6040_probe(struct i2c_client *client, if (gpio_is_valid(twl6040->audpwron)) gpio_free(twl6040->audpwron); gpio1_err: - i2c_set_clientdata(client, NULL); - regmap_exit(twl6040->regmap); -err: + platform_set_drvdata(pdev, NULL); + kfree(twl6040); return ret; } -static int __devexit twl6040_remove(struct i2c_client *client) +static int __devexit twl6040_remove(struct platform_device *pdev) { - struct twl6040 *twl6040 = i2c_get_clientdata(client); + struct twl6040 *twl6040 = platform_get_drvdata(pdev); if (twl6040->power_count) twl6040_power(twl6040, 0); @@ -641,30 +626,23 @@ static int __devexit twl6040_remove(struct i2c_client *client) free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040); twl6040_irq_exit(twl6040); - mfd_remove_devices(&client->dev); - i2c_set_clientdata(client, NULL); - regmap_exit(twl6040->regmap); + mfd_remove_devices(&pdev->dev); + platform_set_drvdata(pdev, NULL); + kfree(twl6040); return 0; } -static const struct i2c_device_id twl6040_i2c_id[] = { - { "twl6040", 0, }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id); - -static struct i2c_driver twl6040_driver = { - .driver = { - .name = "twl6040", - .owner = THIS_MODULE, - }, +static struct platform_driver twl6040_driver = { .probe = twl6040_probe, .remove = __devexit_p(twl6040_remove), - .id_table = twl6040_i2c_id, + .driver = { + .owner = THIS_MODULE, + .name = "twl6040", + }, }; -module_i2c_driver(twl6040_driver); +module_platform_driver(twl6040_driver); MODULE_DESCRIPTION("TWL6040 MFD"); MODULE_AUTHOR("Misael Lopez Cruz "); diff --git a/trunk/drivers/mmc/card/block.c b/trunk/drivers/mmc/card/block.c index dabec556ebb8..b1809650b7aa 100644 --- a/trunk/drivers/mmc/card/block.c +++ b/trunk/drivers/mmc/card/block.c @@ -873,7 +873,7 @@ static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, { struct mmc_blk_data *md = mq->data; struct mmc_card *card = md->queue.card; - unsigned int from, nr, arg, trim_arg, erase_arg; + unsigned int from, nr, arg; int err = 0, type = MMC_BLK_SECDISCARD; if (!(mmc_can_secure_erase_trim(card) || mmc_can_sanitize(card))) { @@ -881,26 +881,20 @@ static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, goto out; } - from = blk_rq_pos(req); - nr = blk_rq_sectors(req); - /* The sanitize operation is supported at v4.5 only */ if (mmc_can_sanitize(card)) { - erase_arg = MMC_ERASE_ARG; - trim_arg = MMC_TRIM_ARG; - } else { - erase_arg = MMC_SECURE_ERASE_ARG; - trim_arg = MMC_SECURE_TRIM1_ARG; - } - - if (mmc_erase_group_aligned(card, from, nr)) - arg = erase_arg; - else if (mmc_can_trim(card)) - arg = trim_arg; - else { - err = -EINVAL; + err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_SANITIZE_START, 1, 0); goto out; } + + from = blk_rq_pos(req); + nr = blk_rq_sectors(req); + + if (mmc_can_trim(card) && !mmc_erase_group_aligned(card, from, nr)) + arg = MMC_SECURE_TRIM1_ARG; + else + arg = MMC_SECURE_ERASE_ARG; retry: if (card->quirks & MMC_QUIRK_INAND_CMD38) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, @@ -910,41 +904,25 @@ static int mmc_blk_issue_secdiscard_rq(struct mmc_queue *mq, INAND_CMD38_ARG_SECERASE, 0); if (err) - goto out_retry; + goto out; } - err = mmc_erase(card, from, nr, arg); - if (err == -EIO) - goto out_retry; - if (err) - goto out; - - if (arg == MMC_SECURE_TRIM1_ARG) { + if (!err && arg == MMC_SECURE_TRIM1_ARG) { if (card->quirks & MMC_QUIRK_INAND_CMD38) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, INAND_CMD38_ARG_EXT_CSD, INAND_CMD38_ARG_SECTRIM2, 0); if (err) - goto out_retry; + goto out; } - err = mmc_erase(card, from, nr, MMC_SECURE_TRIM2_ARG); - if (err == -EIO) - goto out_retry; - if (err) - goto out; } - - if (mmc_can_sanitize(card)) - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_SANITIZE_START, 1, 0); -out_retry: - if (err && !mmc_blk_reset(md, card->host, type)) +out: + if (err == -EIO && !mmc_blk_reset(md, card->host, type)) goto retry; if (!err) mmc_blk_reset_success(md, type); -out: spin_lock_irq(&md->lock); __blk_end_request(req, err, blk_rq_bytes(req)); spin_unlock_irq(&md->lock); @@ -1824,7 +1802,7 @@ static void mmc_blk_remove(struct mmc_card *card) } #ifdef CONFIG_PM -static int mmc_blk_suspend(struct mmc_card *card) +static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state) { struct mmc_blk_data *part_md; struct mmc_blk_data *md = mmc_get_drvdata(card); diff --git a/trunk/drivers/mmc/card/queue.c b/trunk/drivers/mmc/card/queue.c index 996f8e36e23d..2517547b4366 100644 --- a/trunk/drivers/mmc/card/queue.c +++ b/trunk/drivers/mmc/card/queue.c @@ -139,7 +139,7 @@ static void mmc_queue_setup_discard(struct request_queue *q, queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, q); q->limits.max_discard_sectors = max_discard; - if (card->erased_byte == 0 && !mmc_can_discard(card)) + if (card->erased_byte == 0) q->limits.discard_zeroes_data = 1; q->limits.discard_granularity = card->pref_erase << 9; /* granularity must not be greater than max. discard */ diff --git a/trunk/drivers/mmc/core/bus.c b/trunk/drivers/mmc/core/bus.c index c60cee92a2b2..3f606068d552 100644 --- a/trunk/drivers/mmc/core/bus.c +++ b/trunk/drivers/mmc/core/bus.c @@ -122,14 +122,14 @@ static int mmc_bus_remove(struct device *dev) return 0; } -static int mmc_bus_suspend(struct device *dev) +static int mmc_bus_suspend(struct device *dev, pm_message_t state) { struct mmc_driver *drv = to_mmc_driver(dev->driver); struct mmc_card *card = mmc_dev_to_card(dev); int ret = 0; if (dev->driver && drv->suspend) - ret = drv->suspend(card); + ret = drv->suspend(card, state); return ret; } @@ -165,14 +165,20 @@ static int mmc_runtime_idle(struct device *dev) return pm_runtime_suspend(dev); } -#endif /* !CONFIG_PM_RUNTIME */ - static const struct dev_pm_ops mmc_bus_pm_ops = { - SET_RUNTIME_PM_OPS(mmc_runtime_suspend, mmc_runtime_resume, - mmc_runtime_idle) - SET_SYSTEM_SLEEP_PM_OPS(mmc_bus_suspend, mmc_bus_resume) + .runtime_suspend = mmc_runtime_suspend, + .runtime_resume = mmc_runtime_resume, + .runtime_idle = mmc_runtime_idle, }; +#define MMC_PM_OPS_PTR (&mmc_bus_pm_ops) + +#else /* !CONFIG_PM_RUNTIME */ + +#define MMC_PM_OPS_PTR NULL + +#endif /* !CONFIG_PM_RUNTIME */ + static struct bus_type mmc_bus_type = { .name = "mmc", .dev_attrs = mmc_dev_attrs, @@ -180,7 +186,9 @@ static struct bus_type mmc_bus_type = { .uevent = mmc_bus_uevent, .probe = mmc_bus_probe, .remove = mmc_bus_remove, - .pm = &mmc_bus_pm_ops, + .suspend = mmc_bus_suspend, + .resume = mmc_bus_resume, + .pm = MMC_PM_OPS_PTR, }; int mmc_register_bus(void) diff --git a/trunk/drivers/mmc/core/cd-gpio.c b/trunk/drivers/mmc/core/cd-gpio.c index 2c14be73254c..29de31e260dd 100644 --- a/trunk/drivers/mmc/core/cd-gpio.c +++ b/trunk/drivers/mmc/core/cd-gpio.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/trunk/drivers/mmc/core/core.c b/trunk/drivers/mmc/core/core.c index ba821fe70bca..7474c47b9c08 100644 --- a/trunk/drivers/mmc/core/core.c +++ b/trunk/drivers/mmc/core/core.c @@ -1409,10 +1409,7 @@ static unsigned int mmc_mmc_erase_timeout(struct mmc_card *card, { unsigned int erase_timeout; - if (arg == MMC_DISCARD_ARG || - (arg == MMC_TRIM_ARG && card->ext_csd.rev >= 6)) { - erase_timeout = card->ext_csd.trim_timeout; - } else if (card->ext_csd.erase_group_def & 1) { + if (card->ext_csd.erase_group_def & 1) { /* High Capacity Erase Group Size uses HC timeouts */ if (arg == MMC_TRIM_ARG) erase_timeout = card->ext_csd.trim_timeout; @@ -1684,6 +1681,8 @@ int mmc_can_trim(struct mmc_card *card) { if (card->ext_csd.sec_feature_support & EXT_CSD_SEC_GB_CL_EN) return 1; + if (mmc_can_discard(card)) + return 1; return 0; } EXPORT_SYMBOL(mmc_can_trim); @@ -1702,8 +1701,6 @@ EXPORT_SYMBOL(mmc_can_discard); int mmc_can_sanitize(struct mmc_card *card) { - if (!mmc_can_trim(card) && !mmc_can_erase(card)) - return 0; if (card->ext_csd.sec_feature_support & EXT_CSD_SEC_SANITIZE) return 1; return 0; @@ -2238,7 +2235,6 @@ int mmc_cache_ctrl(struct mmc_host *host, u8 enable) mmc_card_is_removable(host)) return err; - mmc_claim_host(host); if (card && mmc_card_mmc(card) && (card->ext_csd.cache_size > 0)) { enable = !!enable; @@ -2256,7 +2252,6 @@ int mmc_cache_ctrl(struct mmc_host *host, u8 enable) card->ext_csd.cache_ctrl = enable; } } - mmc_release_host(host); return err; } @@ -2274,32 +2269,49 @@ int mmc_suspend_host(struct mmc_host *host) cancel_delayed_work(&host->detect); mmc_flush_scheduled_work(); + if (mmc_try_claim_host(host)) { + err = mmc_cache_ctrl(host, 0); + mmc_release_host(host); + } else { + err = -EBUSY; + } - err = mmc_cache_ctrl(host, 0); if (err) goto out; mmc_bus_get(host); if (host->bus_ops && !host->bus_dead) { - if (host->bus_ops->suspend) - err = host->bus_ops->suspend(host); - - if (err == -ENOSYS || !host->bus_ops->resume) { - /* - * We simply "remove" the card in this case. - * It will be redetected on resume. (Calling - * bus_ops->remove() with a claimed host can - * deadlock.) - */ - if (host->bus_ops->remove) - host->bus_ops->remove(host); - mmc_claim_host(host); - mmc_detach_bus(host); - mmc_power_off(host); + /* + * A long response time is not acceptable for device drivers + * when doing suspend. Prevent mmc_claim_host in the suspend + * sequence, to potentially wait "forever" by trying to + * pre-claim the host. + */ + if (mmc_try_claim_host(host)) { + if (host->bus_ops->suspend) { + err = host->bus_ops->suspend(host); + } mmc_release_host(host); - host->pm_flags = 0; - err = 0; + + if (err == -ENOSYS || !host->bus_ops->resume) { + /* + * We simply "remove" the card in this case. + * It will be redetected on resume. (Calling + * bus_ops->remove() with a claimed host can + * deadlock.) + */ + if (host->bus_ops->remove) + host->bus_ops->remove(host); + mmc_claim_host(host); + mmc_detach_bus(host); + mmc_power_off(host); + mmc_release_host(host); + host->pm_flags = 0; + err = 0; + } + } else { + err = -EBUSY; } } mmc_bus_put(host); diff --git a/trunk/drivers/mmc/host/dw_mmc.c b/trunk/drivers/mmc/host/dw_mmc.c index ab3fc4617107..bf3c9b456aaf 100644 --- a/trunk/drivers/mmc/host/dw_mmc.c +++ b/trunk/drivers/mmc/host/dw_mmc.c @@ -526,10 +526,8 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) return -ENODEV; sg_len = dw_mci_pre_dma_transfer(host, data, 0); - if (sg_len < 0) { - host->dma_ops->stop(host); + if (sg_len < 0) return sg_len; - } host->using_dma = 1; @@ -1881,8 +1879,7 @@ static void dw_mci_init_dma(struct dw_mci *host) if (!host->dma_ops) goto no_dma; - if (host->dma_ops->init && host->dma_ops->start && - host->dma_ops->stop && host->dma_ops->cleanup) { + if (host->dma_ops->init) { if (host->dma_ops->init(host)) { dev_err(&host->dev, "%s: Unable to initialize " "DMA Controller.\n", __func__); diff --git a/trunk/drivers/mmc/host/omap_hsmmc.c b/trunk/drivers/mmc/host/omap_hsmmc.c index 56d4499d4388..5c2b1c10af9c 100644 --- a/trunk/drivers/mmc/host/omap_hsmmc.c +++ b/trunk/drivers/mmc/host/omap_hsmmc.c @@ -249,7 +249,7 @@ static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, * the pbias cell programming support is still missing when * booting with Device tree */ - if (dev->of_node && !vdd) + if (of_have_populated_dt() && !vdd) return 0; if (mmc_slot(host).before_set_reg) @@ -1549,7 +1549,7 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * can't be allowed when booting with device * tree. */ - !host->dev->of_node) { + (!of_have_populated_dt())) { /* * The mmc_select_voltage fn of the core does * not seem to set the power_mode to @@ -1741,7 +1741,7 @@ static const struct of_device_id omap_mmc_of_match[] = { .data = &omap4_reg_offset, }, {}, -}; +} MODULE_DEVICE_TABLE(of, omap_mmc_of_match); static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) diff --git a/trunk/drivers/mmc/host/sdhci-esdhc-imx.c b/trunk/drivers/mmc/host/sdhci-esdhc-imx.c index 8abdaf6697a8..6193a0d7bde5 100644 --- a/trunk/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/trunk/drivers/mmc/host/sdhci-esdhc-imx.c @@ -467,7 +467,8 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) clk_prepare_enable(clk); pltfm_host->clk = clk; - host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; + if (!is_imx25_esdhc(imx_data)) + host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ diff --git a/trunk/drivers/mmc/host/sdhci.c b/trunk/drivers/mmc/host/sdhci.c index ccefdebeff14..9aa77f3f04a8 100644 --- a/trunk/drivers/mmc/host/sdhci.c +++ b/trunk/drivers/mmc/host/sdhci.c @@ -147,7 +147,7 @@ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) u32 present, irqs; if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || - (host->mmc->caps & MMC_CAP_NONREMOVABLE)) + !mmc_card_is_removable(host->mmc)) return; present = sdhci_readl(host, SDHCI_PRESENT_STATE) & diff --git a/trunk/drivers/of/address.c b/trunk/drivers/of/address.c index 66d96f14c274..7e262a6124c5 100644 --- a/trunk/drivers/of/address.c +++ b/trunk/drivers/of/address.c @@ -1,4 +1,5 @@ +#include #include #include #include diff --git a/trunk/drivers/of/base.c b/trunk/drivers/of/base.c index d9bfd49b1935..580644986945 100644 --- a/trunk/drivers/of/base.c +++ b/trunk/drivers/of/base.c @@ -1260,44 +1260,3 @@ int of_alias_get_id(struct device_node *np, const char *stem) return id; } EXPORT_SYMBOL_GPL(of_alias_get_id); - -const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, - u32 *pu) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) { - curv = prop->value; - goto out_val; - } - - curv += sizeof(*cur); - if (curv >= prop->value + prop->length) - return NULL; - -out_val: - *pu = be32_to_cpup(curv); - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_u32); - -const char *of_prop_next_string(struct property *prop, const char *cur) -{ - const void *curv = cur; - - if (!prop) - return NULL; - - if (!cur) - return prop->value; - - curv += strlen(cur) + 1; - if (curv >= prop->value + prop->length) - return NULL; - - return curv; -} -EXPORT_SYMBOL_GPL(of_prop_next_string); diff --git a/trunk/drivers/pci/pci.c b/trunk/drivers/pci/pci.c index 111569ccab43..d20f1334792b 100644 --- a/trunk/drivers/pci/pci.c +++ b/trunk/drivers/pci/pci.c @@ -991,8 +991,8 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset, } } -static void pci_restore_config_space_range(struct pci_dev *pdev, - int start, int end, int retry) +static void pci_restore_config_space(struct pci_dev *pdev, int start, int end, + int retry) { int index; @@ -1002,18 +1002,6 @@ static void pci_restore_config_space_range(struct pci_dev *pdev, retry); } -static void pci_restore_config_space(struct pci_dev *pdev) -{ - if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { - pci_restore_config_space_range(pdev, 10, 15, 0); - /* Restore BARs before the command register. */ - pci_restore_config_space_range(pdev, 4, 9, 10); - pci_restore_config_space_range(pdev, 0, 3, 0); - } else { - pci_restore_config_space_range(pdev, 0, 15, 0); - } -} - /** * pci_restore_state - Restore the saved state of a PCI device * @dev: - PCI device that we're dealing with @@ -1027,7 +1015,13 @@ void pci_restore_state(struct pci_dev *dev) pci_restore_pcie_state(dev); pci_restore_ats_state(dev); - pci_restore_config_space(dev); + pci_restore_config_space(dev, 10, 15, 0); + /* + * The Base Address register should be programmed before the command + * register(s) + */ + pci_restore_config_space(dev, 4, 9, 10); + pci_restore_config_space(dev, 0, 3, 0); pci_restore_pcix_state(dev); pci_restore_msi_state(dev); diff --git a/trunk/drivers/pinctrl/Kconfig b/trunk/drivers/pinctrl/Kconfig index a54a93112cba..abfb96408779 100644 --- a/trunk/drivers/pinctrl/Kconfig +++ b/trunk/drivers/pinctrl/Kconfig @@ -4,6 +4,7 @@ config PINCTRL bool + depends on EXPERIMENTAL if PINCTRL @@ -26,19 +27,6 @@ config DEBUG_PINCTRL help Say Y here to add some extra checks and diagnostics to PINCTRL calls. -config PINCTRL_IMX - bool - select PINMUX - select PINCONF - -config PINCTRL_IMX6Q - bool "IMX6Q pinctrl driver" - depends on OF - depends on SOC_IMX6Q - select PINCTRL_IMX - help - Say Y here to enable the imx6q pinctrl driver - config PINCTRL_PXA3xx bool select PINMUX @@ -49,21 +37,6 @@ config PINCTRL_MMP2 select PINCTRL_PXA3xx select PINCONF -config PINCTRL_MXS - bool - -config PINCTRL_IMX23 - bool - select PINMUX - select PINCONF - select PINCTRL_MXS - -config PINCTRL_IMX28 - bool - select PINMUX - select PINCONF - select PINCTRL_MXS - config PINCTRL_PXA168 bool "PXA168 pin controller driver" depends on ARCH_MMP @@ -111,8 +84,6 @@ config PINCTRL_COH901 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 ports of 8 GPIO pins each. -source "drivers/pinctrl/spear/Kconfig" - endmenu endif diff --git a/trunk/drivers/pinctrl/Makefile b/trunk/drivers/pinctrl/Makefile index c9b0be56ff49..6d4150b4eced 100644 --- a/trunk/drivers/pinctrl/Makefile +++ b/trunk/drivers/pinctrl/Makefile @@ -5,17 +5,9 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG obj-$(CONFIG_PINCTRL) += core.o obj-$(CONFIG_PINMUX) += pinmux.o obj-$(CONFIG_PINCONF) += pinconf.o -ifeq ($(CONFIG_OF),y) -obj-$(CONFIG_PINCTRL) += devicetree.o -endif obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o -obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o -obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o -obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o -obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o -obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o @@ -24,5 +16,3 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o - -obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/trunk/drivers/pinctrl/core.c b/trunk/drivers/pinctrl/core.c index c3b331b74fa0..ec3b8cc188af 100644 --- a/trunk/drivers/pinctrl/core.c +++ b/trunk/drivers/pinctrl/core.c @@ -23,11 +23,9 @@ #include #include #include -#include #include #include #include "core.h" -#include "devicetree.h" #include "pinmux.h" #include "pinconf.h" @@ -43,13 +41,11 @@ struct pinctrl_maps { unsigned num_maps; }; -static bool pinctrl_dummy_state; - /* Mutex taken by all entry points */ DEFINE_MUTEX(pinctrl_mutex); /* Global list of pin control devices (struct pinctrl_dev) */ -LIST_HEAD(pinctrldev_list); +static LIST_HEAD(pinctrldev_list); /* List of pin controller handles (struct pinctrl) */ static LIST_HEAD(pinctrl_list); @@ -63,19 +59,6 @@ static LIST_HEAD(pinctrl_maps); _i_ < _maps_node_->num_maps; \ i++, _map_ = &_maps_node_->maps[_i_]) -/** - * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support - * - * Usually this function is called by platforms without pinctrl driver support - * but run with some shared drivers using pinctrl APIs. - * After calling this function, the pinctrl core will return successfully - * with creating a dummy state for the driver to keep going smoothly. - */ -void pinctrl_provide_dummies(void) -{ - pinctrl_dummy_state = true; -} - const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) { /* We're not allowed to register devices without name */ @@ -140,25 +123,6 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name) return -EINVAL; } -/** - * pin_get_name_from_id() - look up a pin name from a pin id - * @pctldev: the pin control device to lookup the pin on - * @name: the name of the pin to look up - */ -const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) -{ - const struct pin_desc *desc; - - desc = pin_desc_get(pctldev, pin); - if (desc == NULL) { - dev_err(pctldev->dev, "failed to get pin(%d) name\n", - pin); - return NULL; - } - - return desc->name; -} - /** * pin_is_valid() - check if pin exists on controller * @pctldev: the pin control device to check the pin on @@ -291,8 +255,7 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio) * * Find the pin controller handling a certain GPIO pin from the pinspace of * the GPIO subsystem, return the device and the matching GPIO range. Returns - * -EPROBE_DEFER if the GPIO range could not be found in any device since it - * may still have not been registered. + * negative if the GPIO range could not be found in any device. */ static int pinctrl_get_device_gpio_range(unsigned gpio, struct pinctrl_dev **outdev, @@ -312,7 +275,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, } } - return -EPROBE_DEFER; + return -EINVAL; } /** @@ -355,10 +318,9 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, const char *pin_group) { const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - unsigned ngroups = pctlops->get_groups_count(pctldev); unsigned group_selector = 0; - while (group_selector < ngroups) { + while (pctlops->list_groups(pctldev, group_selector) >= 0) { const char *gname = pctlops->get_group_name(pctldev, group_selector); if (!strcmp(gname, pin_group)) { @@ -398,7 +360,7 @@ int pinctrl_request_gpio(unsigned gpio) ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); if (ret) { mutex_unlock(&pinctrl_mutex); - return ret; + return -EINVAL; } /* Convert to the pin controllers number space */ @@ -554,14 +516,11 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map) setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); if (setting->pctldev == NULL) { - dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe", + dev_err(p->dev, "unknown pinctrl device %s in map entry", map->ctrl_dev_name); kfree(setting); - /* - * OK let us guess that the driver is not there yet, and - * let's defer obtaining this pinctrl handle to later... - */ - return -EPROBE_DEFER; + /* Eventually, this should trigger deferred probe */ + return -ENODEV; } switch (map->type) { @@ -620,13 +579,6 @@ static struct pinctrl *create_pinctrl(struct device *dev) } p->dev = dev; INIT_LIST_HEAD(&p->states); - INIT_LIST_HEAD(&p->dt_maps); - - ret = pinctrl_dt_to_map(p); - if (ret < 0) { - kfree(p); - return ERR_PTR(ret); - } devname = dev_name(dev); @@ -710,8 +662,6 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist) kfree(state); } - pinctrl_dt_free_maps(p); - if (inlist) list_del(&p->node); kfree(p); @@ -735,18 +685,8 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p, struct pinctrl_state *state; state = find_state(p, name); - if (!state) { - if (pinctrl_dummy_state) { - /* create dummy state */ - dev_dbg(p->dev, "using pinctrl dummy state (%s)\n", - name); - state = create_state(p, name); - if (IS_ERR(state)) - return state; - } else { - return ERR_PTR(-ENODEV); - } - } + if (!state) + return ERR_PTR(-ENODEV); return state; } @@ -847,63 +787,15 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state) } EXPORT_SYMBOL_GPL(pinctrl_select_state); -static void devm_pinctrl_release(struct device *dev, void *res) -{ - pinctrl_put(*(struct pinctrl **)res); -} - -/** - * struct devm_pinctrl_get() - Resource managed pinctrl_get() - * @dev: the device to obtain the handle for - * - * If there is a need to explicitly destroy the returned struct pinctrl, - * devm_pinctrl_put() should be used, rather than plain pinctrl_put(). - */ -struct pinctrl *devm_pinctrl_get(struct device *dev) -{ - struct pinctrl **ptr, *p; - - ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL); - if (!ptr) - return ERR_PTR(-ENOMEM); - - p = pinctrl_get(dev); - if (!IS_ERR(p)) { - *ptr = p; - devres_add(dev, ptr); - } else { - devres_free(ptr); - } - - return p; -} -EXPORT_SYMBOL_GPL(devm_pinctrl_get); - -static int devm_pinctrl_match(struct device *dev, void *res, void *data) -{ - struct pinctrl **p = res; - - return *p == data; -} - /** - * devm_pinctrl_put() - Resource managed pinctrl_put() - * @p: the pinctrl handle to release - * - * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally - * this function will not need to be called and the resource management - * code will ensure that the resource is freed. + * pinctrl_register_mappings() - register a set of pin controller mappings + * @maps: the pincontrol mappings table to register. This should probably be + * marked with __initdata so it can be discarded after boot. This + * function will perform a shallow copy for the mapping entries. + * @num_maps: the number of maps in the mapping table */ -void devm_pinctrl_put(struct pinctrl *p) -{ - WARN_ON(devres_destroy(p->dev, devm_pinctrl_release, - devm_pinctrl_match, p)); - pinctrl_put(p); -} -EXPORT_SYMBOL_GPL(devm_pinctrl_put); - -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, - bool dup, bool locked) +int pinctrl_register_mappings(struct pinctrl_map const *maps, + unsigned num_maps) { int i, ret; struct pinctrl_maps *maps_node; @@ -937,13 +829,13 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, case PIN_MAP_TYPE_MUX_GROUP: ret = pinmux_validate_map(&maps[i], i); if (ret < 0) - return ret; + return 0; break; case PIN_MAP_TYPE_CONFIGS_PIN: case PIN_MAP_TYPE_CONFIGS_GROUP: ret = pinconf_validate_map(&maps[i], i); if (ret < 0) - return ret; + return 0; break; default: pr_err("failed to register map %s (%d): invalid type given\n", @@ -959,52 +851,20 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, } maps_node->num_maps = num_maps; - if (dup) { - maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, - GFP_KERNEL); - if (!maps_node->maps) { - pr_err("failed to duplicate mapping table\n"); - kfree(maps_node); - return -ENOMEM; - } - } else { - maps_node->maps = maps; + maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); + if (!maps_node->maps) { + pr_err("failed to duplicate mapping table\n"); + kfree(maps_node); + return -ENOMEM; } - if (!locked) - mutex_lock(&pinctrl_mutex); + mutex_lock(&pinctrl_mutex); list_add_tail(&maps_node->node, &pinctrl_maps); - if (!locked) - mutex_unlock(&pinctrl_mutex); + mutex_unlock(&pinctrl_mutex); return 0; } -/** - * pinctrl_register_mappings() - register a set of pin controller mappings - * @maps: the pincontrol mappings table to register. This should probably be - * marked with __initdata so it can be discarded after boot. This - * function will perform a shallow copy for the mapping entries. - * @num_maps: the number of maps in the mapping table - */ -int pinctrl_register_mappings(struct pinctrl_map const *maps, - unsigned num_maps) -{ - return pinctrl_register_map(maps, num_maps, true, false); -} - -void pinctrl_unregister_map(struct pinctrl_map const *map) -{ - struct pinctrl_maps *maps_node; - - list_for_each_entry(maps_node, &pinctrl_maps, node) { - if (maps_node->maps == map) { - list_del(&maps_node->node); - return; - } - } -} - #ifdef CONFIG_DEBUG_FS static int pinctrl_pins_show(struct seq_file *s, void *what) @@ -1046,17 +906,19 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *ops = pctldev->desc->pctlops; - unsigned ngroups, selector = 0; + unsigned selector = 0; + + /* No grouping */ + if (!ops) + return 0; - ngroups = ops->get_groups_count(pctldev); mutex_lock(&pinctrl_mutex); seq_puts(s, "registered pin groups:\n"); - while (selector < ngroups) { + while (ops->list_groups(pctldev, selector) >= 0) { const unsigned *pins; unsigned num_pins; const char *gname = ops->get_group_name(pctldev, selector); - const char *pname; int ret; int i; @@ -1066,14 +928,10 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) seq_printf(s, "%s [ERROR GETTING PINS]\n", gname); else { - seq_printf(s, "group: %s\n", gname); - for (i = 0; i < num_pins; i++) { - pname = pin_get_name(pctldev, pins[i]); - if (WARN_ON(!pname)) - return -EINVAL; - seq_printf(s, "pin %d (%s)\n", pins[i], pname); - } - seq_puts(s, "\n"); + seq_printf(s, "group: %s, pins = [ ", gname); + for (i = 0; i < num_pins; i++) + seq_printf(s, "%d ", pins[i]); + seq_puts(s, "]\n"); } selector++; } @@ -1367,22 +1225,6 @@ static void pinctrl_remove_device_debugfs(struct pinctrl_dev *pctldev) #endif -static int pinctrl_check_ops(struct pinctrl_dev *pctldev) -{ - const struct pinctrl_ops *ops = pctldev->desc->pctlops; - - if (!ops || - !ops->get_groups_count || - !ops->get_group_name || - !ops->get_group_pins) - return -EINVAL; - - if (ops->dt_node_to_map && !ops->dt_free_map) - return -EINVAL; - - return 0; -} - /** * pinctrl_register() - register a pin controller device * @pctldesc: descriptor for this pin controller @@ -1414,32 +1256,32 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, INIT_LIST_HEAD(&pctldev->gpio_ranges); pctldev->dev = dev; - /* check core ops for sanity */ - ret = pinctrl_check_ops(pctldev); - if (ret) { - dev_err(dev, "pinctrl ops lacks necessary functions\n"); - goto out_err; - } - /* If we're implementing pinmuxing, check the ops for sanity */ if (pctldesc->pmxops) { ret = pinmux_check_ops(pctldev); - if (ret) + if (ret) { + pr_err("%s pinmux ops lacks necessary functions\n", + pctldesc->name); goto out_err; + } } /* If we're implementing pinconfig, check the ops for sanity */ if (pctldesc->confops) { ret = pinconf_check_ops(pctldev); - if (ret) + if (ret) { + pr_err("%s pin config ops lacks necessary functions\n", + pctldesc->name); goto out_err; + } } /* Register all the pins */ - dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins); + pr_debug("try to register %d pins on %s...\n", + pctldesc->npins, pctldesc->name); ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins); if (ret) { - dev_err(dev, "error during pin registration\n"); + pr_err("error during pin registration\n"); pinctrl_free_pindescs(pctldev, pctldesc->pins, pctldesc->npins); goto out_err; @@ -1454,15 +1296,8 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc, struct pinctrl_state *s = pinctrl_lookup_state_locked(pctldev->p, PINCTRL_STATE_DEFAULT); - if (IS_ERR(s)) { - dev_dbg(dev, "failed to lookup the default state\n"); - } else { - ret = pinctrl_select_state_locked(pctldev->p, s); - if (ret) { - dev_err(dev, - "failed to select default state\n"); - } - } + if (!IS_ERR(s)) + pinctrl_select_state_locked(pctldev->p, s); } mutex_unlock(&pinctrl_mutex); diff --git a/trunk/drivers/pinctrl/core.h b/trunk/drivers/pinctrl/core.h index 1f40ff68a8c4..17ecf651b123 100644 --- a/trunk/drivers/pinctrl/core.h +++ b/trunk/drivers/pinctrl/core.h @@ -52,15 +52,12 @@ struct pinctrl_dev { * @dev: the device using this pin control handle * @states: a list of states for this device * @state: the current state - * @dt_maps: the mapping table chunks dynamically parsed from device tree for - * this device, if any */ struct pinctrl { struct list_head node; struct device *dev; struct list_head states; struct pinctrl_state *state; - struct list_head dt_maps; }; /** @@ -103,8 +100,7 @@ struct pinctrl_setting_configs { * struct pinctrl_setting - an individual mux or config setting * @node: list node for struct pinctrl_settings's @settings field * @type: the type of setting - * @pctldev: pin control device handling to be programmed. Not used for - * PIN_MAP_TYPE_DUMMY_STATE. + * @pctldev: pin control device handling to be programmed * @data: Data specific to the setting type */ struct pinctrl_setting { @@ -148,7 +144,6 @@ struct pin_desc { struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); -const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin); int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, const char *pin_group); @@ -158,9 +153,4 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev, return radix_tree_lookup(&pctldev->pin_desc_tree, pin); } -int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps, - bool dup, bool locked); -void pinctrl_unregister_map(struct pinctrl_map const *map); - extern struct mutex pinctrl_mutex; -extern struct list_head pinctrldev_list; diff --git a/trunk/drivers/pinctrl/devicetree.c b/trunk/drivers/pinctrl/devicetree.c deleted file mode 100644 index fcb1de45473c..000000000000 --- a/trunk/drivers/pinctrl/devicetree.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Device tree integration for the pin control subsystem - * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include "core.h" -#include "devicetree.h" - -/** - * struct pinctrl_dt_map - mapping table chunk parsed from device tree - * @node: list node for struct pinctrl's @dt_maps field - * @pctldev: the pin controller that allocated this struct, and will free it - * @maps: the mapping table entries - */ -struct pinctrl_dt_map { - struct list_head node; - struct pinctrl_dev *pctldev; - struct pinctrl_map *map; - unsigned num_maps; -}; - -static void dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - if (pctldev) { - struct pinctrl_ops *ops = pctldev->desc->pctlops; - ops->dt_free_map(pctldev, map, num_maps); - } else { - /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ - kfree(map); - } -} - -void pinctrl_dt_free_maps(struct pinctrl *p) -{ - struct pinctrl_dt_map *dt_map, *n1; - - list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) { - pinctrl_unregister_map(dt_map->map); - list_del(&dt_map->node); - dt_free_map(dt_map->pctldev, dt_map->map, - dt_map->num_maps); - kfree(dt_map); - } - - of_node_put(p->dev->of_node); -} - -static int dt_remember_or_free_map(struct pinctrl *p, const char *statename, - struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - struct pinctrl_dt_map *dt_map; - - /* Initialize common mapping table entry fields */ - for (i = 0; i < num_maps; i++) { - map[i].dev_name = dev_name(p->dev); - map[i].name = statename; - if (pctldev) - map[i].ctrl_dev_name = dev_name(pctldev->dev); - } - - /* Remember the converted mapping table entries */ - dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL); - if (!dt_map) { - dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n"); - dt_free_map(pctldev, map, num_maps); - return -ENOMEM; - } - - dt_map->pctldev = pctldev; - dt_map->map = map; - dt_map->num_maps = num_maps; - list_add_tail(&dt_map->node, &p->dt_maps); - - return pinctrl_register_map(map, num_maps, false, true); -} - -static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np) -{ - struct pinctrl_dev *pctldev; - - list_for_each_entry(pctldev, &pinctrldev_list, node) - if (pctldev->dev->of_node == np) - return pctldev; - - return NULL; -} - -static int dt_to_map_one_config(struct pinctrl *p, const char *statename, - struct device_node *np_config) -{ - struct device_node *np_pctldev; - struct pinctrl_dev *pctldev; - struct pinctrl_ops *ops; - int ret; - struct pinctrl_map *map; - unsigned num_maps; - - /* Find the pin controller containing np_config */ - np_pctldev = of_node_get(np_config); - for (;;) { - np_pctldev = of_get_next_parent(np_pctldev); - if (!np_pctldev || of_node_is_root(np_pctldev)) { - dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n", - np_config->full_name); - of_node_put(np_pctldev); - /* OK let's just assume this will appear later then */ - return -EPROBE_DEFER; - } - pctldev = find_pinctrl_by_of_node(np_pctldev); - if (pctldev) - break; - } - of_node_put(np_pctldev); - - /* - * Call pinctrl driver to parse device tree node, and - * generate mapping table entries - */ - ops = pctldev->desc->pctlops; - if (!ops->dt_node_to_map) { - dev_err(p->dev, "pctldev %s doesn't support DT\n", - dev_name(pctldev->dev)); - return -ENODEV; - } - ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps); - if (ret < 0) - return ret; - - /* Stash the mapping table chunk away for later use */ - return dt_remember_or_free_map(p, statename, pctldev, map, num_maps); -} - -static int dt_remember_dummy_state(struct pinctrl *p, const char *statename) -{ - struct pinctrl_map *map; - - map = kzalloc(sizeof(*map), GFP_KERNEL); - if (!map) { - dev_err(p->dev, "failed to alloc struct pinctrl_map\n"); - return -ENOMEM; - } - - /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ - map->type = PIN_MAP_TYPE_DUMMY_STATE; - - return dt_remember_or_free_map(p, statename, NULL, map, 1); -} - -int pinctrl_dt_to_map(struct pinctrl *p) -{ - struct device_node *np = p->dev->of_node; - int state, ret; - char *propname; - struct property *prop; - const char *statename; - const __be32 *list; - int size, config; - phandle phandle; - struct device_node *np_config; - - /* CONFIG_OF enabled, p->dev not instantiated from DT */ - if (!np) { - dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n"); - return 0; - } - - /* We may store pointers to property names within the node */ - of_node_get(np); - - /* For each defined state ID */ - for (state = 0; ; state++) { - /* Retrieve the pinctrl-* property */ - propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state); - prop = of_find_property(np, propname, &size); - kfree(propname); - if (!prop) - break; - list = prop->value; - size /= sizeof(*list); - - /* Determine whether pinctrl-names property names the state */ - ret = of_property_read_string_index(np, "pinctrl-names", - state, &statename); - /* - * If not, statename is just the integer state ID. But rather - * than dynamically allocate it and have to free it later, - * just point part way into the property name for the string. - */ - if (ret < 0) { - /* strlen("pinctrl-") == 8 */ - statename = prop->name + 8; - } - - /* For every referenced pin configuration node in it */ - for (config = 0; config < size; config++) { - phandle = be32_to_cpup(list++); - - /* Look up the pin configuration node */ - np_config = of_find_node_by_phandle(phandle); - if (!np_config) { - dev_err(p->dev, - "prop %s index %i invalid phandle\n", - prop->name, config); - ret = -EINVAL; - goto err; - } - - /* Parse the node */ - ret = dt_to_map_one_config(p, statename, np_config); - of_node_put(np_config); - if (ret < 0) - goto err; - } - - /* No entries in DT? Generate a dummy state table entry */ - if (!size) { - ret = dt_remember_dummy_state(p, statename); - if (ret < 0) - goto err; - } - } - - return 0; - -err: - pinctrl_dt_free_maps(p); - return ret; -} diff --git a/trunk/drivers/pinctrl/devicetree.h b/trunk/drivers/pinctrl/devicetree.h deleted file mode 100644 index 760bc4960f58..000000000000 --- a/trunk/drivers/pinctrl/devicetree.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Internal interface to pinctrl device tree integration - * - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifdef CONFIG_OF - -void pinctrl_dt_free_maps(struct pinctrl *p); -int pinctrl_dt_to_map(struct pinctrl *p); - -#else - -static inline int pinctrl_dt_to_map(struct pinctrl *p) -{ - return 0; -} - -static inline void pinctrl_dt_free_maps(struct pinctrl *p) -{ -} - -#endif diff --git a/trunk/drivers/pinctrl/pinconf.c b/trunk/drivers/pinctrl/pinconf.c index 7ce139ef7e64..7321e8601294 100644 --- a/trunk/drivers/pinctrl/pinconf.c +++ b/trunk/drivers/pinctrl/pinconf.c @@ -28,17 +28,11 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev) const struct pinconf_ops *ops = pctldev->desc->confops; /* We must be able to read out pin status */ - if (!ops->pin_config_get && !ops->pin_config_group_get) { - dev_err(pctldev->dev, - "pinconf must be able to read out pin status\n"); + if (!ops->pin_config_get && !ops->pin_config_group_get) return -EINVAL; - } /* We have to be able to config the pins in SOME way */ - if (!ops->pin_config_set && !ops->pin_config_group_set) { - dev_err(pctldev->dev, - "pinconf has to be able to set a pins config\n"); + if (!ops->pin_config_set && !ops->pin_config_group_set) return -EINVAL; - } return 0; } @@ -385,16 +379,8 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting) void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) { - struct pinctrl_dev *pctldev; - const struct pinconf_ops *confops; int i; - pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); - if (pctldev) - confops = pctldev->desc->confops; - else - confops = NULL; - switch (map->type) { case PIN_MAP_TYPE_CONFIGS_PIN: seq_printf(s, "pin "); @@ -408,15 +394,8 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) seq_printf(s, "%s\n", map->data.configs.group_or_pin); - for (i = 0; i < map->data.configs.num_configs; i++) { - seq_printf(s, "config "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - map->data.configs.configs[i]); - else - seq_printf(s, "%08lx", map->data.configs.configs[i]); - seq_printf(s, "\n"); - } + for (i = 0; i < map->data.configs.num_configs; i++) + seq_printf(s, "config %08lx\n", map->data.configs.configs[i]); } void pinconf_show_setting(struct seq_file *s, @@ -424,7 +403,6 @@ void pinconf_show_setting(struct seq_file *s, { struct pinctrl_dev *pctldev = setting->pctldev; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; - const struct pinconf_ops *confops = pctldev->desc->confops; struct pin_desc *desc; int i; @@ -450,15 +428,8 @@ void pinconf_show_setting(struct seq_file *s, * FIXME: We should really get the pin controler to dump the config * values, so they can be decoded to something meaningful. */ - for (i = 0; i < setting->data.configs.num_configs; i++) { - seq_printf(s, " "); - if (confops && confops->pin_config_config_dbg_show) - confops->pin_config_config_dbg_show(pctldev, s, - setting->data.configs.configs[i]); - else - seq_printf(s, "%08lx", - setting->data.configs.configs[i]); - } + for (i = 0; i < setting->data.configs.num_configs; i++) + seq_printf(s, " %08lx", setting->data.configs.configs[i]); seq_printf(s, "\n"); } @@ -477,14 +448,10 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev, static int pinconf_pins_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; - const struct pinconf_ops *ops = pctldev->desc->confops; unsigned i, pin; - if (!ops || !ops->pin_config_get) - return 0; - seq_puts(s, "Pin config settings per pin\n"); - seq_puts(s, "Format: pin (name): configs\n"); + seq_puts(s, "Format: pin (name): pinmux setting array\n"); mutex_lock(&pinctrl_mutex); @@ -528,18 +495,17 @@ static int pinconf_groups_show(struct seq_file *s, void *what) struct pinctrl_dev *pctldev = s->private; const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; const struct pinconf_ops *ops = pctldev->desc->confops; - unsigned ngroups = pctlops->get_groups_count(pctldev); unsigned selector = 0; if (!ops || !ops->pin_config_group_get) return 0; seq_puts(s, "Pin config settings per pin group\n"); - seq_puts(s, "Format: group (name): configs\n"); + seq_puts(s, "Format: group (name): pinmux setting array\n"); mutex_lock(&pinctrl_mutex); - while (selector < ngroups) { + while (pctlops->list_groups(pctldev, selector) >= 0) { const char *gname = pctlops->get_group_name(pctldev, selector); seq_printf(s, "%u (%s):", selector, gname); diff --git a/trunk/drivers/pinctrl/pinconf.h b/trunk/drivers/pinctrl/pinconf.h index e3ed8cb072a5..54510de5e8c6 100644 --- a/trunk/drivers/pinctrl/pinconf.h +++ b/trunk/drivers/pinctrl/pinconf.h @@ -19,6 +19,11 @@ int pinconf_map_to_setting(struct pinctrl_map const *map, struct pinctrl_setting *setting); void pinconf_free_setting(struct pinctrl_setting const *setting); int pinconf_apply_setting(struct pinctrl_setting const *setting); +void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinconf_show_setting(struct seq_file *s, + struct pinctrl_setting const *setting); +void pinconf_init_device_debugfs(struct dentry *devroot, + struct pinctrl_dev *pctldev); /* * You will only be interested in these if you're using PINCONF @@ -56,18 +61,6 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting) return 0; } -#endif - -#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS) - -void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map); -void pinconf_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); -void pinconf_init_device_debugfs(struct dentry *devroot, - struct pinctrl_dev *pctldev); - -#else - static inline void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) { diff --git a/trunk/drivers/pinctrl/pinctrl-coh901.c b/trunk/drivers/pinctrl/pinctrl-coh901.c index 55697a5d7482..0797eba3e33a 100644 --- a/trunk/drivers/pinctrl/pinctrl-coh901.c +++ b/trunk/drivers/pinctrl/pinctrl-coh901.c @@ -174,7 +174,7 @@ struct u300_gpio_confdata { /* Initial configuration */ -static const struct __initconst u300_gpio_confdata +static const struct __initdata u300_gpio_confdata bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { @@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { } }; -static const struct __initconst u300_gpio_confdata +static const struct __initdata u300_gpio_confdata bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { diff --git a/trunk/drivers/pinctrl/pinctrl-imx.c b/trunk/drivers/pinctrl/pinctrl-imx.c deleted file mode 100644 index 8faf613ff1b2..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx.c +++ /dev/null @@ -1,627 +0,0 @@ -/* - * Core driver for the imx pin controller - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" -#include "pinctrl-imx.h" - -#define IMX_PMX_DUMP(info, p, m, c, n) \ -{ \ - int i, j; \ - printk("Format: Pin Mux Config\n"); \ - for (i = 0; i < n; i++) { \ - j = p[i]; \ - printk("%s %d 0x%lx\n", \ - info->pins[j].name, \ - m[i], c[i]); \ - } \ -} - -/* The bits in CONFIG cell defined in binding doc*/ -#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ -#define IMX_PAD_SION 0x40000000 /* set SION */ - -/** - * @dev: a pointer back to containing device - * @base: the offset to the controller in virtual memory - */ -struct imx_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - const struct imx_pinctrl_soc_info *info; -}; - -static const struct imx_pin_reg *imx_find_pin_reg( - const struct imx_pinctrl_soc_info *info, - unsigned pin, bool is_mux, unsigned mux) -{ - const struct imx_pin_reg *pin_reg = NULL; - int i; - - for (i = 0; i < info->npin_regs; i++) { - pin_reg = &info->pin_regs[i]; - if (pin_reg->pid != pin) - continue; - if (!is_mux) - break; - else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK)) - break; - } - - if (!pin_reg) { - dev_err(info->dev, "Pin(%s): unable to find pin reg map\n", - info->pins[pin].name); - return NULL; - } - - return pin_reg; -} - -static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name( - const struct imx_pinctrl_soc_info *info, - const char *name) -{ - const struct imx_pin_group *grp = NULL; - int i; - - for (i = 0; i < info->ngroups; i++) { - if (!strcmp(info->groups[i].name, name)) { - grp = &info->groups[i]; - break; - } - } - - return grp; -} - -static int imx_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->ngroups; -} - -static const char *imx_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->groups[selector].name; -} - -static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *npins) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - if (selector >= info->ngroups) - return -EINVAL; - - *pins = info->groups[selector].pins; - *npins = info->groups[selector].npins; - - return 0; -} - -static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, "%s", dev_name(pctldev->dev)); -} - -static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_group *grp; - struct pinctrl_map *new_map; - struct device_node *parent; - int map_num = 1; - int i; - - /* - * first find the group of this node and check if we need create - * config maps for pins - */ - grp = imx_pinctrl_find_group_by_name(info, np->name); - if (!grp) { - dev_err(info->dev, "unable to find group for node %s\n", - np->name); - return -EINVAL; - } - - for (i = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) - map_num++; - } - - new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - *map = new_map; - *num_maps = map_num; - - /* create mux map */ - parent = of_get_parent(np); - if (!parent) - return -EINVAL; - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = parent->name; - new_map[0].data.mux.group = np->name; - of_node_put(parent); - - /* create config map */ - new_map++; - for (i = 0; i < grp->npins; i++) { - if (!(grp->configs[i] & IMX_NO_PAD_CTL)) { - new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[i].data.configs.group_or_pin = - pin_get_name(pctldev, grp->pins[i]); - new_map[i].data.configs.configs = &grp->configs[i]; - new_map[i].data.configs.num_configs = 1; - } - } - - dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", - new_map->data.mux.function, new_map->data.mux.group, map_num); - - return 0; -} - -static void imx_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - kfree(map); -} - -static struct pinctrl_ops imx_pctrl_ops = { - .get_groups_count = imx_get_groups_count, - .get_group_name = imx_get_group_name, - .get_group_pins = imx_get_group_pins, - .pin_dbg_show = imx_pin_dbg_show, - .dt_node_to_map = imx_dt_node_to_map, - .dt_free_map = imx_dt_free_map, - -}; - -static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - const unsigned *pins, *mux; - unsigned int npins, pin_id; - int i; - - /* - * Configure the mux mode for each pin in the group for a specific - * function. - */ - pins = info->groups[group].pins; - npins = info->groups[group].npins; - mux = info->groups[group].mux_mode; - - WARN_ON(!pins || !npins || !mux); - - dev_dbg(ipctl->dev, "enable function %s group %s\n", - info->functions[selector].name, info->groups[group].name); - - for (i = 0; i < npins; i++) { - pin_id = pins[i]; - - pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->mux_reg) { - dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - writel(mux[i], ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, mux[i]); - - /* some pins also need select input setting, set it if found */ - if (pin_reg->input_reg) { - writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg); - dev_dbg(ipctl->dev, - "==>select_input: offset 0x%x val 0x%x\n", - pin_reg->input_reg, pin_reg->input_val); - } - } - - return 0; -} - -static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector, - unsigned group_selector) -{ - /* nothing to do here */ -} - -static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->nfunctions; -} - -static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - return info->functions[selector].name; -} - -static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - - *groups = info->functions[selector].groups; - *num_groups = info->functions[selector].num_groups; - - return 0; -} - -static struct pinmux_ops imx_pmx_ops = { - .get_functions_count = imx_pmx_get_funcs_count, - .get_function_name = imx_pmx_get_func_name, - .get_function_groups = imx_pmx_get_groups, - .enable = imx_pmx_enable, - .disable = imx_pmx_disable, -}; - -static int imx_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - *config = readl(ipctl->base + pin_reg->conf_reg); - - return 0; -} - -static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long config) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg) - return -EINVAL; - - if (!pin_reg->conf_reg) { - dev_err(info->dev, "Pin(%s) does not support config function\n", - info->pins[pin_id].name); - return -EINVAL; - } - - dev_dbg(ipctl->dev, "pinconf set pin %s\n", - info->pins[pin_id].name); - - writel(config, ipctl->base + pin_reg->conf_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, config); - - return 0; -} - -static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin_id) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - unsigned long config; - - pin_reg = imx_find_pin_reg(info, pin_id, 0, 0); - if (!pin_reg || !pin_reg->conf_reg) { - seq_printf(s, "N/A"); - return; - } - - config = readl(ipctl->base + pin_reg->conf_reg); - seq_printf(s, "0x%lx", config); -} - -static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pinctrl_soc_info *info = ipctl->info; - struct imx_pin_group *grp; - unsigned long config; - const char *name; - int i, ret; - - if (group > info->ngroups) - return; - - seq_printf(s, "\n"); - grp = &info->groups[group]; - for (i = 0; i < grp->npins; i++) { - name = pin_get_name(pctldev, grp->pins[i]); - ret = imx_pinconf_get(pctldev, grp->pins[i], &config); - if (ret) - return; - seq_printf(s, "%s: 0x%lx", name, config); - } -} - -struct pinconf_ops imx_pinconf_ops = { - .pin_config_get = imx_pinconf_get, - .pin_config_set = imx_pinconf_set, - .pin_config_dbg_show = imx_pinconf_dbg_show, - .pin_config_group_dbg_show = imx_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc imx_pinctrl_desc = { - .pctlops = &imx_pctrl_ops, - .pmxops = &imx_pmx_ops, - .confops = &imx_pinconf_ops, - .owner = THIS_MODULE, -}; - -/* decode pin id and mux from pin function id got from device tree*/ -static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info, - unsigned int pin_func_id, unsigned int *pin_id, - unsigned int *mux) -{ - if (pin_func_id > info->npin_regs) - return -EINVAL; - - *pin_id = info->pin_regs[pin_func_id].pid; - *mux = info->pin_regs[pin_func_id].mux_mode; - - return 0; -} - -static int __devinit imx_pinctrl_parse_groups(struct device_node *np, - struct imx_pin_group *grp, - struct imx_pinctrl_soc_info *info, - u32 index) -{ - unsigned int pin_func_id; - int ret, size; - const const __be32 *list; - int i, j; - u32 config; - - dev_dbg(info->dev, "group(%d): %s\n", index, np->name); - - /* Initialise group */ - grp->name = np->name; - - /* - * the binding format is fsl,pins = , - * do sanity check and calculate pins number - */ - list = of_get_property(np, "fsl,pins", &size); - /* we do not check return since it's safe node passed down */ - size /= sizeof(*list); - if (!size || size % 2) { - dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n"); - return -EINVAL; - } - - grp->npins = size / 2; - grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), - GFP_KERNEL); - grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long), - GFP_KERNEL); - for (i = 0, j = 0; i < size; i += 2, j++) { - pin_func_id = be32_to_cpu(*list++); - ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id, - &grp->pins[j], &grp->mux_mode[j]); - if (ret) { - dev_err(info->dev, "get invalid pin function id\n"); - return -EINVAL; - } - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - grp->mux_mode[j] |= IOMUXC_CONFIG_SION; - grp->configs[j] = config & ~IMX_PAD_SION; - } - -#ifdef DEBUG - IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins); -#endif - return 0; -} - -static int __devinit imx_pinctrl_parse_functions(struct device_node *np, - struct imx_pinctrl_soc_info *info, u32 index) -{ - struct device_node *child; - struct imx_pmx_func *func; - struct imx_pin_group *grp; - int ret; - static u32 grp_index; - u32 i = 0; - - dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); - - func = &info->functions[index]; - - /* Initialise function */ - func->name = np->name; - func->num_groups = of_get_child_count(np); - if (func->num_groups <= 0) { - dev_err(info->dev, "no groups defined\n"); - return -EINVAL; - } - func->groups = devm_kzalloc(info->dev, - func->num_groups * sizeof(char *), GFP_KERNEL); - - for_each_child_of_node(np, child) { - func->groups[i] = child->name; - grp = &info->groups[grp_index++]; - ret = imx_pinctrl_parse_groups(child, grp, info, i++); - if (ret) - return ret; - } - - return 0; -} - -static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - int ret; - u32 nfuncs = 0; - u32 i = 0; - - if (!np) - return -ENODEV; - - nfuncs = of_get_child_count(np); - if (nfuncs <= 0) { - dev_err(&pdev->dev, "no functions defined\n"); - return -EINVAL; - } - - info->nfunctions = nfuncs; - info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func), - GFP_KERNEL); - if (!info->functions) - return -ENOMEM; - - info->ngroups = 0; - for_each_child_of_node(np, child) - info->ngroups += of_get_child_count(child); - info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group), - GFP_KERNEL); - if (!info->groups) - return -ENOMEM; - - for_each_child_of_node(np, child) { - ret = imx_pinctrl_parse_functions(child, info, i++); - if (ret) { - dev_err(&pdev->dev, "failed to parse function\n"); - return ret; - } - } - - return 0; -} - -int __devinit imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info) -{ - struct imx_pinctrl *ipctl; - struct resource *res; - int ret; - - if (!info || !info->pins || !info->npins - || !info->pin_regs || !info->npin_regs) { - dev_err(&pdev->dev, "wrong pinctrl info\n"); - return -EINVAL; - } - info->dev = &pdev->dev; - - /* Create state holders etc for this driver */ - ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL); - if (!ipctl) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENOENT; - - ipctl->base = devm_request_and_ioremap(&pdev->dev, res); - if (!ipctl->base) - return -EBUSY; - - imx_pinctrl_desc.name = dev_name(&pdev->dev); - imx_pinctrl_desc.pins = info->pins; - imx_pinctrl_desc.npins = info->npins; - - ret = imx_pinctrl_probe_dt(pdev, info); - if (ret) { - dev_err(&pdev->dev, "fail to probe dt properties\n"); - return ret; - } - - ipctl->info = info; - ipctl->dev = info->dev; - platform_set_drvdata(pdev, ipctl); - ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl); - if (!ipctl->pctl) { - dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - return -EINVAL; - } - - dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); - - return 0; -} - -int __devexit imx_pinctrl_remove(struct platform_device *pdev) -{ - struct imx_pinctrl *ipctl = platform_get_drvdata(pdev); - - pinctrl_unregister(ipctl->pctl); - - return 0; -} diff --git a/trunk/drivers/pinctrl/pinctrl-imx.h b/trunk/drivers/pinctrl/pinctrl-imx.h deleted file mode 100644 index 9b65e7828f1d..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * IMX pinmux core definitions - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro Ltd. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __DRIVERS_PINCTRL_IMX_H -#define __DRIVERS_PINCTRL_IMX_H - -struct platform_device; - -/** - * struct imx_pin_group - describes an IMX pin group - * @name: the name of this specific pin group - * @pins: an array of discrete physical pins used in this group, taken - * from the driver-local pin enumeration space - * @npins: the number of pins in this group array, i.e. the number of - * elements in .pins so we can iterate over that array - * @mux_mode: the mux mode for each pin in this group. The size of this - * array is the same as pins. - * @configs: the config for each pin in this group. The size of this - * array is the same as pins. - */ -struct imx_pin_group { - const char *name; - unsigned int *pins; - unsigned npins; - unsigned int *mux_mode; - unsigned long *configs; -}; - -/** - * struct imx_pmx_func - describes IMX pinmux functions - * @name: the name of this specific function - * @groups: corresponding pin groups - * @num_groups: the number of groups - */ -struct imx_pmx_func { - const char *name; - const char **groups; - unsigned num_groups; -}; - -/** - * struct imx_pin_reg - describe a pin reg map - * The last 3 members are used for select input setting - * @pid: pin id - * @mux_reg: mux register offset - * @conf_reg: config register offset - * @mux_mode: mux mode - * @input_reg: select input register offset for this mux if any - * 0 if no select input setting needed. - * @input_val: the value set to select input register - */ -struct imx_pin_reg { - u16 pid; - u16 mux_reg; - u16 conf_reg; - u8 mux_mode; - u16 input_reg; - u8 input_val; -}; - -struct imx_pinctrl_soc_info { - struct device *dev; - const struct pinctrl_pin_desc *pins; - unsigned int npins; - const struct imx_pin_reg *pin_regs; - unsigned int npin_regs; - struct imx_pin_group *groups; - unsigned int ngroups; - struct imx_pmx_func *functions; - unsigned int nfunctions; -}; - -#define NO_MUX 0x0 -#define NO_PAD 0x0 - -#define IMX_PIN_REG(id, conf, mux, mode, input, val) \ - { \ - .pid = id, \ - .conf_reg = conf, \ - .mux_reg = mux, \ - .mux_mode = mode, \ - .input_reg = input, \ - .input_val = val, \ - } - -#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) - -#define PAD_CTL_MASK(len) ((1 << len) - 1) -#define IMX_MUX_MASK 0x7 -#define IOMUXC_CONFIG_SION (0x1 << 4) - -int imx_pinctrl_probe(struct platform_device *pdev, - struct imx_pinctrl_soc_info *info); -int imx_pinctrl_remove(struct platform_device *pdev); -#endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-imx23.c b/trunk/drivers/pinctrl/pinctrl-imx23.c deleted file mode 100644 index 75d3eff94296..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx23.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx23_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_D08 = PINID(0, 8), - GPMI_D09 = PINID(0, 9), - GPMI_D10 = PINID(0, 10), - GPMI_D11 = PINID(0, 11), - GPMI_D12 = PINID(0, 12), - GPMI_D13 = PINID(0, 13), - GPMI_D14 = PINID(0, 14), - GPMI_D15 = PINID(0, 15), - GPMI_CLE = PINID(0, 16), - GPMI_ALE = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_RDY0 = PINID(0, 19), - GPMI_RDY1 = PINID(0, 20), - GPMI_RDY2 = PINID(0, 21), - GPMI_RDY3 = PINID(0, 22), - GPMI_WPN = PINID(0, 23), - GPMI_WRN = PINID(0, 24), - GPMI_RDN = PINID(0, 25), - AUART1_CTS = PINID(0, 26), - AUART1_RTS = PINID(0, 27), - AUART1_RX = PINID(0, 28), - AUART1_TX = PINID(0, 29), - I2C_SCL = PINID(0, 30), - I2C_SDA = PINID(0, 31), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_RESET = PINID(1, 18), - LCD_RS = PINID(1, 19), - LCD_WR = PINID(1, 20), - LCD_CS = PINID(1, 21), - LCD_DOTCK = PINID(1, 22), - LCD_ENABLE = PINID(1, 23), - LCD_HSYNC = PINID(1, 24), - LCD_VSYNC = PINID(1, 25), - PWM0 = PINID(1, 26), - PWM1 = PINID(1, 27), - PWM2 = PINID(1, 28), - PWM3 = PINID(1, 29), - PWM4 = PINID(1, 30), - SSP1_CMD = PINID(2, 0), - SSP1_DETECT = PINID(2, 1), - SSP1_DATA0 = PINID(2, 2), - SSP1_DATA1 = PINID(2, 3), - SSP1_DATA2 = PINID(2, 4), - SSP1_DATA3 = PINID(2, 5), - SSP1_SCK = PINID(2, 6), - ROTARYA = PINID(2, 7), - ROTARYB = PINID(2, 8), - EMI_A00 = PINID(2, 9), - EMI_A01 = PINID(2, 10), - EMI_A02 = PINID(2, 11), - EMI_A03 = PINID(2, 12), - EMI_A04 = PINID(2, 13), - EMI_A05 = PINID(2, 14), - EMI_A06 = PINID(2, 15), - EMI_A07 = PINID(2, 16), - EMI_A08 = PINID(2, 17), - EMI_A09 = PINID(2, 18), - EMI_A10 = PINID(2, 19), - EMI_A11 = PINID(2, 20), - EMI_A12 = PINID(2, 21), - EMI_BA0 = PINID(2, 22), - EMI_BA1 = PINID(2, 23), - EMI_CASN = PINID(2, 24), - EMI_CE0N = PINID(2, 25), - EMI_CE1N = PINID(2, 26), - GPMI_CE1N = PINID(2, 27), - GPMI_CE0N = PINID(2, 28), - EMI_CKE = PINID(2, 29), - EMI_RASN = PINID(2, 30), - EMI_WEN = PINID(2, 31), - EMI_D00 = PINID(3, 0), - EMI_D01 = PINID(3, 1), - EMI_D02 = PINID(3, 2), - EMI_D03 = PINID(3, 3), - EMI_D04 = PINID(3, 4), - EMI_D05 = PINID(3, 5), - EMI_D06 = PINID(3, 6), - EMI_D07 = PINID(3, 7), - EMI_D08 = PINID(3, 8), - EMI_D09 = PINID(3, 9), - EMI_D10 = PINID(3, 10), - EMI_D11 = PINID(3, 11), - EMI_D12 = PINID(3, 12), - EMI_D13 = PINID(3, 13), - EMI_D14 = PINID(3, 14), - EMI_D15 = PINID(3, 15), - EMI_DQM0 = PINID(3, 16), - EMI_DQM1 = PINID(3, 17), - EMI_DQS0 = PINID(3, 18), - EMI_DQS1 = PINID(3, 19), - EMI_CLK = PINID(3, 20), - EMI_CLKN = PINID(3, 21), -}; - -static const struct pinctrl_pin_desc imx23_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_D08), - MXS_PINCTRL_PIN(GPMI_D09), - MXS_PINCTRL_PIN(GPMI_D10), - MXS_PINCTRL_PIN(GPMI_D11), - MXS_PINCTRL_PIN(GPMI_D12), - MXS_PINCTRL_PIN(GPMI_D13), - MXS_PINCTRL_PIN(GPMI_D14), - MXS_PINCTRL_PIN(GPMI_D15), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_WPN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(I2C_SCL), - MXS_PINCTRL_PIN(I2C_SDA), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_WR), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_DOTCK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DETECT), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA1), - MXS_PINCTRL_PIN(SSP1_DATA2), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(ROTARYA), - MXS_PINCTRL_PIN(ROTARYB), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(EMI_CKE), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_CLKN), -}; - -static struct mxs_regs imx23_regs = { - .muxsel = 0x100, - .drive = 0x200, - .pull = 0x400, -}; - -static struct mxs_pinctrl_soc_data imx23_pinctrl_data = { - .regs = &imx23_regs, - .pins = imx23_pins, - .npins = ARRAY_SIZE(imx23_pins), -}; - -static int __devinit imx23_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); -} - -static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx23-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match); - -static struct platform_driver imx23_pinctrl_driver = { - .driver = { - .name = "imx23-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx23_pinctrl_of_match, - }, - .probe = imx23_pinctrl_probe, - .remove = __devexit_p(mxs_pinctrl_remove), -}; - -static int __init imx23_pinctrl_init(void) -{ - return platform_driver_register(&imx23_pinctrl_driver); -} -arch_initcall(imx23_pinctrl_init); - -static void __exit imx23_pinctrl_exit(void) -{ - platform_driver_unregister(&imx23_pinctrl_driver); -} -module_exit(imx23_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-imx28.c b/trunk/drivers/pinctrl/pinctrl-imx28.c deleted file mode 100644 index b973026811a2..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx28.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include "pinctrl-mxs.h" - -enum imx28_pin_enum { - GPMI_D00 = PINID(0, 0), - GPMI_D01 = PINID(0, 1), - GPMI_D02 = PINID(0, 2), - GPMI_D03 = PINID(0, 3), - GPMI_D04 = PINID(0, 4), - GPMI_D05 = PINID(0, 5), - GPMI_D06 = PINID(0, 6), - GPMI_D07 = PINID(0, 7), - GPMI_CE0N = PINID(0, 16), - GPMI_CE1N = PINID(0, 17), - GPMI_CE2N = PINID(0, 18), - GPMI_CE3N = PINID(0, 19), - GPMI_RDY0 = PINID(0, 20), - GPMI_RDY1 = PINID(0, 21), - GPMI_RDY2 = PINID(0, 22), - GPMI_RDY3 = PINID(0, 23), - GPMI_RDN = PINID(0, 24), - GPMI_WRN = PINID(0, 25), - GPMI_ALE = PINID(0, 26), - GPMI_CLE = PINID(0, 27), - GPMI_RESETN = PINID(0, 28), - LCD_D00 = PINID(1, 0), - LCD_D01 = PINID(1, 1), - LCD_D02 = PINID(1, 2), - LCD_D03 = PINID(1, 3), - LCD_D04 = PINID(1, 4), - LCD_D05 = PINID(1, 5), - LCD_D06 = PINID(1, 6), - LCD_D07 = PINID(1, 7), - LCD_D08 = PINID(1, 8), - LCD_D09 = PINID(1, 9), - LCD_D10 = PINID(1, 10), - LCD_D11 = PINID(1, 11), - LCD_D12 = PINID(1, 12), - LCD_D13 = PINID(1, 13), - LCD_D14 = PINID(1, 14), - LCD_D15 = PINID(1, 15), - LCD_D16 = PINID(1, 16), - LCD_D17 = PINID(1, 17), - LCD_D18 = PINID(1, 18), - LCD_D19 = PINID(1, 19), - LCD_D20 = PINID(1, 20), - LCD_D21 = PINID(1, 21), - LCD_D22 = PINID(1, 22), - LCD_D23 = PINID(1, 23), - LCD_RD_E = PINID(1, 24), - LCD_WR_RWN = PINID(1, 25), - LCD_RS = PINID(1, 26), - LCD_CS = PINID(1, 27), - LCD_VSYNC = PINID(1, 28), - LCD_HSYNC = PINID(1, 29), - LCD_DOTCLK = PINID(1, 30), - LCD_ENABLE = PINID(1, 31), - SSP0_DATA0 = PINID(2, 0), - SSP0_DATA1 = PINID(2, 1), - SSP0_DATA2 = PINID(2, 2), - SSP0_DATA3 = PINID(2, 3), - SSP0_DATA4 = PINID(2, 4), - SSP0_DATA5 = PINID(2, 5), - SSP0_DATA6 = PINID(2, 6), - SSP0_DATA7 = PINID(2, 7), - SSP0_CMD = PINID(2, 8), - SSP0_DETECT = PINID(2, 9), - SSP0_SCK = PINID(2, 10), - SSP1_SCK = PINID(2, 12), - SSP1_CMD = PINID(2, 13), - SSP1_DATA0 = PINID(2, 14), - SSP1_DATA3 = PINID(2, 15), - SSP2_SCK = PINID(2, 16), - SSP2_MOSI = PINID(2, 17), - SSP2_MISO = PINID(2, 18), - SSP2_SS0 = PINID(2, 19), - SSP2_SS1 = PINID(2, 20), - SSP2_SS2 = PINID(2, 21), - SSP3_SCK = PINID(2, 24), - SSP3_MOSI = PINID(2, 25), - SSP3_MISO = PINID(2, 26), - SSP3_SS0 = PINID(2, 27), - AUART0_RX = PINID(3, 0), - AUART0_TX = PINID(3, 1), - AUART0_CTS = PINID(3, 2), - AUART0_RTS = PINID(3, 3), - AUART1_RX = PINID(3, 4), - AUART1_TX = PINID(3, 5), - AUART1_CTS = PINID(3, 6), - AUART1_RTS = PINID(3, 7), - AUART2_RX = PINID(3, 8), - AUART2_TX = PINID(3, 9), - AUART2_CTS = PINID(3, 10), - AUART2_RTS = PINID(3, 11), - AUART3_RX = PINID(3, 12), - AUART3_TX = PINID(3, 13), - AUART3_CTS = PINID(3, 14), - AUART3_RTS = PINID(3, 15), - PWM0 = PINID(3, 16), - PWM1 = PINID(3, 17), - PWM2 = PINID(3, 18), - SAIF0_MCLK = PINID(3, 20), - SAIF0_LRCLK = PINID(3, 21), - SAIF0_BITCLK = PINID(3, 22), - SAIF0_SDATA0 = PINID(3, 23), - I2C0_SCL = PINID(3, 24), - I2C0_SDA = PINID(3, 25), - SAIF1_SDATA0 = PINID(3, 26), - SPDIF = PINID(3, 27), - PWM3 = PINID(3, 28), - PWM4 = PINID(3, 29), - LCD_RESET = PINID(3, 30), - ENET0_MDC = PINID(4, 0), - ENET0_MDIO = PINID(4, 1), - ENET0_RX_EN = PINID(4, 2), - ENET0_RXD0 = PINID(4, 3), - ENET0_RXD1 = PINID(4, 4), - ENET0_TX_CLK = PINID(4, 5), - ENET0_TX_EN = PINID(4, 6), - ENET0_TXD0 = PINID(4, 7), - ENET0_TXD1 = PINID(4, 8), - ENET0_RXD2 = PINID(4, 9), - ENET0_RXD3 = PINID(4, 10), - ENET0_TXD2 = PINID(4, 11), - ENET0_TXD3 = PINID(4, 12), - ENET0_RX_CLK = PINID(4, 13), - ENET0_COL = PINID(4, 14), - ENET0_CRS = PINID(4, 15), - ENET_CLK = PINID(4, 16), - JTAG_RTCK = PINID(4, 20), - EMI_D00 = PINID(5, 0), - EMI_D01 = PINID(5, 1), - EMI_D02 = PINID(5, 2), - EMI_D03 = PINID(5, 3), - EMI_D04 = PINID(5, 4), - EMI_D05 = PINID(5, 5), - EMI_D06 = PINID(5, 6), - EMI_D07 = PINID(5, 7), - EMI_D08 = PINID(5, 8), - EMI_D09 = PINID(5, 9), - EMI_D10 = PINID(5, 10), - EMI_D11 = PINID(5, 11), - EMI_D12 = PINID(5, 12), - EMI_D13 = PINID(5, 13), - EMI_D14 = PINID(5, 14), - EMI_D15 = PINID(5, 15), - EMI_ODT0 = PINID(5, 16), - EMI_DQM0 = PINID(5, 17), - EMI_ODT1 = PINID(5, 18), - EMI_DQM1 = PINID(5, 19), - EMI_DDR_OPEN_FB = PINID(5, 20), - EMI_CLK = PINID(5, 21), - EMI_DQS0 = PINID(5, 22), - EMI_DQS1 = PINID(5, 23), - EMI_DDR_OPEN = PINID(5, 26), - EMI_A00 = PINID(6, 0), - EMI_A01 = PINID(6, 1), - EMI_A02 = PINID(6, 2), - EMI_A03 = PINID(6, 3), - EMI_A04 = PINID(6, 4), - EMI_A05 = PINID(6, 5), - EMI_A06 = PINID(6, 6), - EMI_A07 = PINID(6, 7), - EMI_A08 = PINID(6, 8), - EMI_A09 = PINID(6, 9), - EMI_A10 = PINID(6, 10), - EMI_A11 = PINID(6, 11), - EMI_A12 = PINID(6, 12), - EMI_A13 = PINID(6, 13), - EMI_A14 = PINID(6, 14), - EMI_BA0 = PINID(6, 16), - EMI_BA1 = PINID(6, 17), - EMI_BA2 = PINID(6, 18), - EMI_CASN = PINID(6, 19), - EMI_RASN = PINID(6, 20), - EMI_WEN = PINID(6, 21), - EMI_CE0N = PINID(6, 22), - EMI_CE1N = PINID(6, 23), - EMI_CKE = PINID(6, 24), -}; - -static const struct pinctrl_pin_desc imx28_pins[] = { - MXS_PINCTRL_PIN(GPMI_D00), - MXS_PINCTRL_PIN(GPMI_D01), - MXS_PINCTRL_PIN(GPMI_D02), - MXS_PINCTRL_PIN(GPMI_D03), - MXS_PINCTRL_PIN(GPMI_D04), - MXS_PINCTRL_PIN(GPMI_D05), - MXS_PINCTRL_PIN(GPMI_D06), - MXS_PINCTRL_PIN(GPMI_D07), - MXS_PINCTRL_PIN(GPMI_CE0N), - MXS_PINCTRL_PIN(GPMI_CE1N), - MXS_PINCTRL_PIN(GPMI_CE2N), - MXS_PINCTRL_PIN(GPMI_CE3N), - MXS_PINCTRL_PIN(GPMI_RDY0), - MXS_PINCTRL_PIN(GPMI_RDY1), - MXS_PINCTRL_PIN(GPMI_RDY2), - MXS_PINCTRL_PIN(GPMI_RDY3), - MXS_PINCTRL_PIN(GPMI_RDN), - MXS_PINCTRL_PIN(GPMI_WRN), - MXS_PINCTRL_PIN(GPMI_ALE), - MXS_PINCTRL_PIN(GPMI_CLE), - MXS_PINCTRL_PIN(GPMI_RESETN), - MXS_PINCTRL_PIN(LCD_D00), - MXS_PINCTRL_PIN(LCD_D01), - MXS_PINCTRL_PIN(LCD_D02), - MXS_PINCTRL_PIN(LCD_D03), - MXS_PINCTRL_PIN(LCD_D04), - MXS_PINCTRL_PIN(LCD_D05), - MXS_PINCTRL_PIN(LCD_D06), - MXS_PINCTRL_PIN(LCD_D07), - MXS_PINCTRL_PIN(LCD_D08), - MXS_PINCTRL_PIN(LCD_D09), - MXS_PINCTRL_PIN(LCD_D10), - MXS_PINCTRL_PIN(LCD_D11), - MXS_PINCTRL_PIN(LCD_D12), - MXS_PINCTRL_PIN(LCD_D13), - MXS_PINCTRL_PIN(LCD_D14), - MXS_PINCTRL_PIN(LCD_D15), - MXS_PINCTRL_PIN(LCD_D16), - MXS_PINCTRL_PIN(LCD_D17), - MXS_PINCTRL_PIN(LCD_D18), - MXS_PINCTRL_PIN(LCD_D19), - MXS_PINCTRL_PIN(LCD_D20), - MXS_PINCTRL_PIN(LCD_D21), - MXS_PINCTRL_PIN(LCD_D22), - MXS_PINCTRL_PIN(LCD_D23), - MXS_PINCTRL_PIN(LCD_RD_E), - MXS_PINCTRL_PIN(LCD_WR_RWN), - MXS_PINCTRL_PIN(LCD_RS), - MXS_PINCTRL_PIN(LCD_CS), - MXS_PINCTRL_PIN(LCD_VSYNC), - MXS_PINCTRL_PIN(LCD_HSYNC), - MXS_PINCTRL_PIN(LCD_DOTCLK), - MXS_PINCTRL_PIN(LCD_ENABLE), - MXS_PINCTRL_PIN(SSP0_DATA0), - MXS_PINCTRL_PIN(SSP0_DATA1), - MXS_PINCTRL_PIN(SSP0_DATA2), - MXS_PINCTRL_PIN(SSP0_DATA3), - MXS_PINCTRL_PIN(SSP0_DATA4), - MXS_PINCTRL_PIN(SSP0_DATA5), - MXS_PINCTRL_PIN(SSP0_DATA6), - MXS_PINCTRL_PIN(SSP0_DATA7), - MXS_PINCTRL_PIN(SSP0_CMD), - MXS_PINCTRL_PIN(SSP0_DETECT), - MXS_PINCTRL_PIN(SSP0_SCK), - MXS_PINCTRL_PIN(SSP1_SCK), - MXS_PINCTRL_PIN(SSP1_CMD), - MXS_PINCTRL_PIN(SSP1_DATA0), - MXS_PINCTRL_PIN(SSP1_DATA3), - MXS_PINCTRL_PIN(SSP2_SCK), - MXS_PINCTRL_PIN(SSP2_MOSI), - MXS_PINCTRL_PIN(SSP2_MISO), - MXS_PINCTRL_PIN(SSP2_SS0), - MXS_PINCTRL_PIN(SSP2_SS1), - MXS_PINCTRL_PIN(SSP2_SS2), - MXS_PINCTRL_PIN(SSP3_SCK), - MXS_PINCTRL_PIN(SSP3_MOSI), - MXS_PINCTRL_PIN(SSP3_MISO), - MXS_PINCTRL_PIN(SSP3_SS0), - MXS_PINCTRL_PIN(AUART0_RX), - MXS_PINCTRL_PIN(AUART0_TX), - MXS_PINCTRL_PIN(AUART0_CTS), - MXS_PINCTRL_PIN(AUART0_RTS), - MXS_PINCTRL_PIN(AUART1_RX), - MXS_PINCTRL_PIN(AUART1_TX), - MXS_PINCTRL_PIN(AUART1_CTS), - MXS_PINCTRL_PIN(AUART1_RTS), - MXS_PINCTRL_PIN(AUART2_RX), - MXS_PINCTRL_PIN(AUART2_TX), - MXS_PINCTRL_PIN(AUART2_CTS), - MXS_PINCTRL_PIN(AUART2_RTS), - MXS_PINCTRL_PIN(AUART3_RX), - MXS_PINCTRL_PIN(AUART3_TX), - MXS_PINCTRL_PIN(AUART3_CTS), - MXS_PINCTRL_PIN(AUART3_RTS), - MXS_PINCTRL_PIN(PWM0), - MXS_PINCTRL_PIN(PWM1), - MXS_PINCTRL_PIN(PWM2), - MXS_PINCTRL_PIN(SAIF0_MCLK), - MXS_PINCTRL_PIN(SAIF0_LRCLK), - MXS_PINCTRL_PIN(SAIF0_BITCLK), - MXS_PINCTRL_PIN(SAIF0_SDATA0), - MXS_PINCTRL_PIN(I2C0_SCL), - MXS_PINCTRL_PIN(I2C0_SDA), - MXS_PINCTRL_PIN(SAIF1_SDATA0), - MXS_PINCTRL_PIN(SPDIF), - MXS_PINCTRL_PIN(PWM3), - MXS_PINCTRL_PIN(PWM4), - MXS_PINCTRL_PIN(LCD_RESET), - MXS_PINCTRL_PIN(ENET0_MDC), - MXS_PINCTRL_PIN(ENET0_MDIO), - MXS_PINCTRL_PIN(ENET0_RX_EN), - MXS_PINCTRL_PIN(ENET0_RXD0), - MXS_PINCTRL_PIN(ENET0_RXD1), - MXS_PINCTRL_PIN(ENET0_TX_CLK), - MXS_PINCTRL_PIN(ENET0_TX_EN), - MXS_PINCTRL_PIN(ENET0_TXD0), - MXS_PINCTRL_PIN(ENET0_TXD1), - MXS_PINCTRL_PIN(ENET0_RXD2), - MXS_PINCTRL_PIN(ENET0_RXD3), - MXS_PINCTRL_PIN(ENET0_TXD2), - MXS_PINCTRL_PIN(ENET0_TXD3), - MXS_PINCTRL_PIN(ENET0_RX_CLK), - MXS_PINCTRL_PIN(ENET0_COL), - MXS_PINCTRL_PIN(ENET0_CRS), - MXS_PINCTRL_PIN(ENET_CLK), - MXS_PINCTRL_PIN(JTAG_RTCK), - MXS_PINCTRL_PIN(EMI_D00), - MXS_PINCTRL_PIN(EMI_D01), - MXS_PINCTRL_PIN(EMI_D02), - MXS_PINCTRL_PIN(EMI_D03), - MXS_PINCTRL_PIN(EMI_D04), - MXS_PINCTRL_PIN(EMI_D05), - MXS_PINCTRL_PIN(EMI_D06), - MXS_PINCTRL_PIN(EMI_D07), - MXS_PINCTRL_PIN(EMI_D08), - MXS_PINCTRL_PIN(EMI_D09), - MXS_PINCTRL_PIN(EMI_D10), - MXS_PINCTRL_PIN(EMI_D11), - MXS_PINCTRL_PIN(EMI_D12), - MXS_PINCTRL_PIN(EMI_D13), - MXS_PINCTRL_PIN(EMI_D14), - MXS_PINCTRL_PIN(EMI_D15), - MXS_PINCTRL_PIN(EMI_ODT0), - MXS_PINCTRL_PIN(EMI_DQM0), - MXS_PINCTRL_PIN(EMI_ODT1), - MXS_PINCTRL_PIN(EMI_DQM1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB), - MXS_PINCTRL_PIN(EMI_CLK), - MXS_PINCTRL_PIN(EMI_DQS0), - MXS_PINCTRL_PIN(EMI_DQS1), - MXS_PINCTRL_PIN(EMI_DDR_OPEN), - MXS_PINCTRL_PIN(EMI_A00), - MXS_PINCTRL_PIN(EMI_A01), - MXS_PINCTRL_PIN(EMI_A02), - MXS_PINCTRL_PIN(EMI_A03), - MXS_PINCTRL_PIN(EMI_A04), - MXS_PINCTRL_PIN(EMI_A05), - MXS_PINCTRL_PIN(EMI_A06), - MXS_PINCTRL_PIN(EMI_A07), - MXS_PINCTRL_PIN(EMI_A08), - MXS_PINCTRL_PIN(EMI_A09), - MXS_PINCTRL_PIN(EMI_A10), - MXS_PINCTRL_PIN(EMI_A11), - MXS_PINCTRL_PIN(EMI_A12), - MXS_PINCTRL_PIN(EMI_A13), - MXS_PINCTRL_PIN(EMI_A14), - MXS_PINCTRL_PIN(EMI_BA0), - MXS_PINCTRL_PIN(EMI_BA1), - MXS_PINCTRL_PIN(EMI_BA2), - MXS_PINCTRL_PIN(EMI_CASN), - MXS_PINCTRL_PIN(EMI_RASN), - MXS_PINCTRL_PIN(EMI_WEN), - MXS_PINCTRL_PIN(EMI_CE0N), - MXS_PINCTRL_PIN(EMI_CE1N), - MXS_PINCTRL_PIN(EMI_CKE), -}; - -static struct mxs_regs imx28_regs = { - .muxsel = 0x100, - .drive = 0x300, - .pull = 0x600, -}; - -static struct mxs_pinctrl_soc_data imx28_pinctrl_data = { - .regs = &imx28_regs, - .pins = imx28_pins, - .npins = ARRAY_SIZE(imx28_pins), -}; - -static int __devinit imx28_pinctrl_probe(struct platform_device *pdev) -{ - return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); -} - -static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx28-pinctrl", }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match); - -static struct platform_driver imx28_pinctrl_driver = { - .driver = { - .name = "imx28-pinctrl", - .owner = THIS_MODULE, - .of_match_table = imx28_pinctrl_of_match, - }, - .probe = imx28_pinctrl_probe, - .remove = __devexit_p(mxs_pinctrl_remove), -}; - -static int __init imx28_pinctrl_init(void) -{ - return platform_driver_register(&imx28_pinctrl_driver); -} -arch_initcall(imx28_pinctrl_init); - -static void __exit imx28_pinctrl_exit(void) -{ - platform_driver_unregister(&imx28_pinctrl_driver); -} -module_exit(imx28_pinctrl_exit); - -MODULE_AUTHOR("Shawn Guo "); -MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-imx6q.c b/trunk/drivers/pinctrl/pinctrl-imx6q.c deleted file mode 100644 index 7737d4d71a3c..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-imx6q.c +++ /dev/null @@ -1,2331 +0,0 @@ -/* - * imx6q pinctrl driver based on imx pinmux core - * - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * Copyright (C) 2012 Linaro, Inc. - * - * Author: Dong Aisheng - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-imx.h" - -enum imx6q_pads { - MX6Q_PAD_SD2_DAT1 = 0, - MX6Q_PAD_SD2_DAT2 = 1, - MX6Q_PAD_SD2_DAT0 = 2, - MX6Q_PAD_RGMII_TXC = 3, - MX6Q_PAD_RGMII_TD0 = 4, - MX6Q_PAD_RGMII_TD1 = 5, - MX6Q_PAD_RGMII_TD2 = 6, - MX6Q_PAD_RGMII_TD3 = 7, - MX6Q_PAD_RGMII_RX_CTL = 8, - MX6Q_PAD_RGMII_RD0 = 9, - MX6Q_PAD_RGMII_TX_CTL = 10, - MX6Q_PAD_RGMII_RD1 = 11, - MX6Q_PAD_RGMII_RD2 = 12, - MX6Q_PAD_RGMII_RD3 = 13, - MX6Q_PAD_RGMII_RXC = 14, - MX6Q_PAD_EIM_A25 = 15, - MX6Q_PAD_EIM_EB2 = 16, - MX6Q_PAD_EIM_D16 = 17, - MX6Q_PAD_EIM_D17 = 18, - MX6Q_PAD_EIM_D18 = 19, - MX6Q_PAD_EIM_D19 = 20, - MX6Q_PAD_EIM_D20 = 21, - MX6Q_PAD_EIM_D21 = 22, - MX6Q_PAD_EIM_D22 = 23, - MX6Q_PAD_EIM_D23 = 24, - MX6Q_PAD_EIM_EB3 = 25, - MX6Q_PAD_EIM_D24 = 26, - MX6Q_PAD_EIM_D25 = 27, - MX6Q_PAD_EIM_D26 = 28, - MX6Q_PAD_EIM_D27 = 29, - MX6Q_PAD_EIM_D28 = 30, - MX6Q_PAD_EIM_D29 = 31, - MX6Q_PAD_EIM_D30 = 32, - MX6Q_PAD_EIM_D31 = 33, - MX6Q_PAD_EIM_A24 = 34, - MX6Q_PAD_EIM_A23 = 35, - MX6Q_PAD_EIM_A22 = 36, - MX6Q_PAD_EIM_A21 = 37, - MX6Q_PAD_EIM_A20 = 38, - MX6Q_PAD_EIM_A19 = 39, - MX6Q_PAD_EIM_A18 = 40, - MX6Q_PAD_EIM_A17 = 41, - MX6Q_PAD_EIM_A16 = 42, - MX6Q_PAD_EIM_CS0 = 43, - MX6Q_PAD_EIM_CS1 = 44, - MX6Q_PAD_EIM_OE = 45, - MX6Q_PAD_EIM_RW = 46, - MX6Q_PAD_EIM_LBA = 47, - MX6Q_PAD_EIM_EB0 = 48, - MX6Q_PAD_EIM_EB1 = 49, - MX6Q_PAD_EIM_DA0 = 50, - MX6Q_PAD_EIM_DA1 = 51, - MX6Q_PAD_EIM_DA2 = 52, - MX6Q_PAD_EIM_DA3 = 53, - MX6Q_PAD_EIM_DA4 = 54, - MX6Q_PAD_EIM_DA5 = 55, - MX6Q_PAD_EIM_DA6 = 56, - MX6Q_PAD_EIM_DA7 = 57, - MX6Q_PAD_EIM_DA8 = 58, - MX6Q_PAD_EIM_DA9 = 59, - MX6Q_PAD_EIM_DA10 = 60, - MX6Q_PAD_EIM_DA11 = 61, - MX6Q_PAD_EIM_DA12 = 62, - MX6Q_PAD_EIM_DA13 = 63, - MX6Q_PAD_EIM_DA14 = 64, - MX6Q_PAD_EIM_DA15 = 65, - MX6Q_PAD_EIM_WAIT = 66, - MX6Q_PAD_EIM_BCLK = 67, - MX6Q_PAD_DI0_DISP_CLK = 68, - MX6Q_PAD_DI0_PIN15 = 69, - MX6Q_PAD_DI0_PIN2 = 70, - MX6Q_PAD_DI0_PIN3 = 71, - MX6Q_PAD_DI0_PIN4 = 72, - MX6Q_PAD_DISP0_DAT0 = 73, - MX6Q_PAD_DISP0_DAT1 = 74, - MX6Q_PAD_DISP0_DAT2 = 75, - MX6Q_PAD_DISP0_DAT3 = 76, - MX6Q_PAD_DISP0_DAT4 = 77, - MX6Q_PAD_DISP0_DAT5 = 78, - MX6Q_PAD_DISP0_DAT6 = 79, - MX6Q_PAD_DISP0_DAT7 = 80, - MX6Q_PAD_DISP0_DAT8 = 81, - MX6Q_PAD_DISP0_DAT9 = 82, - MX6Q_PAD_DISP0_DAT10 = 83, - MX6Q_PAD_DISP0_DAT11 = 84, - MX6Q_PAD_DISP0_DAT12 = 85, - MX6Q_PAD_DISP0_DAT13 = 86, - MX6Q_PAD_DISP0_DAT14 = 87, - MX6Q_PAD_DISP0_DAT15 = 88, - MX6Q_PAD_DISP0_DAT16 = 89, - MX6Q_PAD_DISP0_DAT17 = 90, - MX6Q_PAD_DISP0_DAT18 = 91, - MX6Q_PAD_DISP0_DAT19 = 92, - MX6Q_PAD_DISP0_DAT20 = 93, - MX6Q_PAD_DISP0_DAT21 = 94, - MX6Q_PAD_DISP0_DAT22 = 95, - MX6Q_PAD_DISP0_DAT23 = 96, - MX6Q_PAD_ENET_MDIO = 97, - MX6Q_PAD_ENET_REF_CLK = 98, - MX6Q_PAD_ENET_RX_ER = 99, - MX6Q_PAD_ENET_CRS_DV = 100, - MX6Q_PAD_ENET_RXD1 = 101, - MX6Q_PAD_ENET_RXD0 = 102, - MX6Q_PAD_ENET_TX_EN = 103, - MX6Q_PAD_ENET_TXD1 = 104, - MX6Q_PAD_ENET_TXD0 = 105, - MX6Q_PAD_ENET_MDC = 106, - MX6Q_PAD_DRAM_D40 = 107, - MX6Q_PAD_DRAM_D41 = 108, - MX6Q_PAD_DRAM_D42 = 109, - MX6Q_PAD_DRAM_D43 = 110, - MX6Q_PAD_DRAM_D44 = 111, - MX6Q_PAD_DRAM_D45 = 112, - MX6Q_PAD_DRAM_D46 = 113, - MX6Q_PAD_DRAM_D47 = 114, - MX6Q_PAD_DRAM_SDQS5 = 115, - MX6Q_PAD_DRAM_DQM5 = 116, - MX6Q_PAD_DRAM_D32 = 117, - MX6Q_PAD_DRAM_D33 = 118, - MX6Q_PAD_DRAM_D34 = 119, - MX6Q_PAD_DRAM_D35 = 120, - MX6Q_PAD_DRAM_D36 = 121, - MX6Q_PAD_DRAM_D37 = 122, - MX6Q_PAD_DRAM_D38 = 123, - MX6Q_PAD_DRAM_D39 = 124, - MX6Q_PAD_DRAM_DQM4 = 125, - MX6Q_PAD_DRAM_SDQS4 = 126, - MX6Q_PAD_DRAM_D24 = 127, - MX6Q_PAD_DRAM_D25 = 128, - MX6Q_PAD_DRAM_D26 = 129, - MX6Q_PAD_DRAM_D27 = 130, - MX6Q_PAD_DRAM_D28 = 131, - MX6Q_PAD_DRAM_D29 = 132, - MX6Q_PAD_DRAM_SDQS3 = 133, - MX6Q_PAD_DRAM_D30 = 134, - MX6Q_PAD_DRAM_D31 = 135, - MX6Q_PAD_DRAM_DQM3 = 136, - MX6Q_PAD_DRAM_D16 = 137, - MX6Q_PAD_DRAM_D17 = 138, - MX6Q_PAD_DRAM_D18 = 139, - MX6Q_PAD_DRAM_D19 = 140, - MX6Q_PAD_DRAM_D20 = 141, - MX6Q_PAD_DRAM_D21 = 142, - MX6Q_PAD_DRAM_D22 = 143, - MX6Q_PAD_DRAM_SDQS2 = 144, - MX6Q_PAD_DRAM_D23 = 145, - MX6Q_PAD_DRAM_DQM2 = 146, - MX6Q_PAD_DRAM_A0 = 147, - MX6Q_PAD_DRAM_A1 = 148, - MX6Q_PAD_DRAM_A2 = 149, - MX6Q_PAD_DRAM_A3 = 150, - MX6Q_PAD_DRAM_A4 = 151, - MX6Q_PAD_DRAM_A5 = 152, - MX6Q_PAD_DRAM_A6 = 153, - MX6Q_PAD_DRAM_A7 = 154, - MX6Q_PAD_DRAM_A8 = 155, - MX6Q_PAD_DRAM_A9 = 156, - MX6Q_PAD_DRAM_A10 = 157, - MX6Q_PAD_DRAM_A11 = 158, - MX6Q_PAD_DRAM_A12 = 159, - MX6Q_PAD_DRAM_A13 = 160, - MX6Q_PAD_DRAM_A14 = 161, - MX6Q_PAD_DRAM_A15 = 162, - MX6Q_PAD_DRAM_CAS = 163, - MX6Q_PAD_DRAM_CS0 = 164, - MX6Q_PAD_DRAM_CS1 = 165, - MX6Q_PAD_DRAM_RAS = 166, - MX6Q_PAD_DRAM_RESET = 167, - MX6Q_PAD_DRAM_SDBA0 = 168, - MX6Q_PAD_DRAM_SDBA1 = 169, - MX6Q_PAD_DRAM_SDCLK_0 = 170, - MX6Q_PAD_DRAM_SDBA2 = 171, - MX6Q_PAD_DRAM_SDCKE0 = 172, - MX6Q_PAD_DRAM_SDCLK_1 = 173, - MX6Q_PAD_DRAM_SDCKE1 = 174, - MX6Q_PAD_DRAM_SDODT0 = 175, - MX6Q_PAD_DRAM_SDODT1 = 176, - MX6Q_PAD_DRAM_SDWE = 177, - MX6Q_PAD_DRAM_D0 = 178, - MX6Q_PAD_DRAM_D1 = 179, - MX6Q_PAD_DRAM_D2 = 180, - MX6Q_PAD_DRAM_D3 = 181, - MX6Q_PAD_DRAM_D4 = 182, - MX6Q_PAD_DRAM_D5 = 183, - MX6Q_PAD_DRAM_SDQS0 = 184, - MX6Q_PAD_DRAM_D6 = 185, - MX6Q_PAD_DRAM_D7 = 186, - MX6Q_PAD_DRAM_DQM0 = 187, - MX6Q_PAD_DRAM_D8 = 188, - MX6Q_PAD_DRAM_D9 = 189, - MX6Q_PAD_DRAM_D10 = 190, - MX6Q_PAD_DRAM_D11 = 191, - MX6Q_PAD_DRAM_D12 = 192, - MX6Q_PAD_DRAM_D13 = 193, - MX6Q_PAD_DRAM_D14 = 194, - MX6Q_PAD_DRAM_SDQS1 = 195, - MX6Q_PAD_DRAM_D15 = 196, - MX6Q_PAD_DRAM_DQM1 = 197, - MX6Q_PAD_DRAM_D48 = 198, - MX6Q_PAD_DRAM_D49 = 199, - MX6Q_PAD_DRAM_D50 = 200, - MX6Q_PAD_DRAM_D51 = 201, - MX6Q_PAD_DRAM_D52 = 202, - MX6Q_PAD_DRAM_D53 = 203, - MX6Q_PAD_DRAM_D54 = 204, - MX6Q_PAD_DRAM_D55 = 205, - MX6Q_PAD_DRAM_SDQS6 = 206, - MX6Q_PAD_DRAM_DQM6 = 207, - MX6Q_PAD_DRAM_D56 = 208, - MX6Q_PAD_DRAM_SDQS7 = 209, - MX6Q_PAD_DRAM_D57 = 210, - MX6Q_PAD_DRAM_D58 = 211, - MX6Q_PAD_DRAM_D59 = 212, - MX6Q_PAD_DRAM_D60 = 213, - MX6Q_PAD_DRAM_DQM7 = 214, - MX6Q_PAD_DRAM_D61 = 215, - MX6Q_PAD_DRAM_D62 = 216, - MX6Q_PAD_DRAM_D63 = 217, - MX6Q_PAD_KEY_COL0 = 218, - MX6Q_PAD_KEY_ROW0 = 219, - MX6Q_PAD_KEY_COL1 = 220, - MX6Q_PAD_KEY_ROW1 = 221, - MX6Q_PAD_KEY_COL2 = 222, - MX6Q_PAD_KEY_ROW2 = 223, - MX6Q_PAD_KEY_COL3 = 224, - MX6Q_PAD_KEY_ROW3 = 225, - MX6Q_PAD_KEY_COL4 = 226, - MX6Q_PAD_KEY_ROW4 = 227, - MX6Q_PAD_GPIO_0 = 228, - MX6Q_PAD_GPIO_1 = 229, - MX6Q_PAD_GPIO_9 = 230, - MX6Q_PAD_GPIO_3 = 231, - MX6Q_PAD_GPIO_6 = 232, - MX6Q_PAD_GPIO_2 = 233, - MX6Q_PAD_GPIO_4 = 234, - MX6Q_PAD_GPIO_5 = 235, - MX6Q_PAD_GPIO_7 = 236, - MX6Q_PAD_GPIO_8 = 237, - MX6Q_PAD_GPIO_16 = 238, - MX6Q_PAD_GPIO_17 = 239, - MX6Q_PAD_GPIO_18 = 240, - MX6Q_PAD_GPIO_19 = 241, - MX6Q_PAD_CSI0_PIXCLK = 242, - MX6Q_PAD_CSI0_MCLK = 243, - MX6Q_PAD_CSI0_DATA_EN = 244, - MX6Q_PAD_CSI0_VSYNC = 245, - MX6Q_PAD_CSI0_DAT4 = 246, - MX6Q_PAD_CSI0_DAT5 = 247, - MX6Q_PAD_CSI0_DAT6 = 248, - MX6Q_PAD_CSI0_DAT7 = 249, - MX6Q_PAD_CSI0_DAT8 = 250, - MX6Q_PAD_CSI0_DAT9 = 251, - MX6Q_PAD_CSI0_DAT10 = 252, - MX6Q_PAD_CSI0_DAT11 = 253, - MX6Q_PAD_CSI0_DAT12 = 254, - MX6Q_PAD_CSI0_DAT13 = 255, - MX6Q_PAD_CSI0_DAT14 = 256, - MX6Q_PAD_CSI0_DAT15 = 257, - MX6Q_PAD_CSI0_DAT16 = 258, - MX6Q_PAD_CSI0_DAT17 = 259, - MX6Q_PAD_CSI0_DAT18 = 260, - MX6Q_PAD_CSI0_DAT19 = 261, - MX6Q_PAD_JTAG_TMS = 262, - MX6Q_PAD_JTAG_MOD = 263, - MX6Q_PAD_JTAG_TRSTB = 264, - MX6Q_PAD_JTAG_TDI = 265, - MX6Q_PAD_JTAG_TCK = 266, - MX6Q_PAD_JTAG_TDO = 267, - MX6Q_PAD_LVDS1_TX3_P = 268, - MX6Q_PAD_LVDS1_TX2_P = 269, - MX6Q_PAD_LVDS1_CLK_P = 270, - MX6Q_PAD_LVDS1_TX1_P = 271, - MX6Q_PAD_LVDS1_TX0_P = 272, - MX6Q_PAD_LVDS0_TX3_P = 273, - MX6Q_PAD_LVDS0_CLK_P = 274, - MX6Q_PAD_LVDS0_TX2_P = 275, - MX6Q_PAD_LVDS0_TX1_P = 276, - MX6Q_PAD_LVDS0_TX0_P = 277, - MX6Q_PAD_TAMPER = 278, - MX6Q_PAD_PMIC_ON_REQ = 279, - MX6Q_PAD_PMIC_STBY_REQ = 280, - MX6Q_PAD_POR_B = 281, - MX6Q_PAD_BOOT_MODE1 = 282, - MX6Q_PAD_RESET_IN_B = 283, - MX6Q_PAD_BOOT_MODE0 = 284, - MX6Q_PAD_TEST_MODE = 285, - MX6Q_PAD_SD3_DAT7 = 286, - MX6Q_PAD_SD3_DAT6 = 287, - MX6Q_PAD_SD3_DAT5 = 288, - MX6Q_PAD_SD3_DAT4 = 289, - MX6Q_PAD_SD3_CMD = 290, - MX6Q_PAD_SD3_CLK = 291, - MX6Q_PAD_SD3_DAT0 = 292, - MX6Q_PAD_SD3_DAT1 = 293, - MX6Q_PAD_SD3_DAT2 = 294, - MX6Q_PAD_SD3_DAT3 = 295, - MX6Q_PAD_SD3_RST = 296, - MX6Q_PAD_NANDF_CLE = 297, - MX6Q_PAD_NANDF_ALE = 298, - MX6Q_PAD_NANDF_WP_B = 299, - MX6Q_PAD_NANDF_RB0 = 300, - MX6Q_PAD_NANDF_CS0 = 301, - MX6Q_PAD_NANDF_CS1 = 302, - MX6Q_PAD_NANDF_CS2 = 303, - MX6Q_PAD_NANDF_CS3 = 304, - MX6Q_PAD_SD4_CMD = 305, - MX6Q_PAD_SD4_CLK = 306, - MX6Q_PAD_NANDF_D0 = 307, - MX6Q_PAD_NANDF_D1 = 308, - MX6Q_PAD_NANDF_D2 = 309, - MX6Q_PAD_NANDF_D3 = 310, - MX6Q_PAD_NANDF_D4 = 311, - MX6Q_PAD_NANDF_D5 = 312, - MX6Q_PAD_NANDF_D6 = 313, - MX6Q_PAD_NANDF_D7 = 314, - MX6Q_PAD_SD4_DAT0 = 315, - MX6Q_PAD_SD4_DAT1 = 316, - MX6Q_PAD_SD4_DAT2 = 317, - MX6Q_PAD_SD4_DAT3 = 318, - MX6Q_PAD_SD4_DAT4 = 319, - MX6Q_PAD_SD4_DAT5 = 320, - MX6Q_PAD_SD4_DAT6 = 321, - MX6Q_PAD_SD4_DAT7 = 322, - MX6Q_PAD_SD1_DAT1 = 323, - MX6Q_PAD_SD1_DAT0 = 324, - MX6Q_PAD_SD1_DAT3 = 325, - MX6Q_PAD_SD1_CMD = 326, - MX6Q_PAD_SD1_DAT2 = 327, - MX6Q_PAD_SD1_CLK = 328, - MX6Q_PAD_SD2_CLK = 329, - MX6Q_PAD_SD2_CMD = 330, - MX6Q_PAD_SD2_DAT3 = 331, -}; - -/* imx6q register maps */ -static struct imx_pin_reg imx6q_pin_regs[] = { - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */ - IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */ - IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */ - IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */ - IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */ - IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */ - IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */ - IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */ - IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */ - IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */ - IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */ - IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */ - IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */ - IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */ - IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */ - IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */ - IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */ - IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */ - IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */ - IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */ - IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */ - IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */ - IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */ - IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */ - IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */ - IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */ - IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */ - IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */ - IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */ - IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */ - IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */ - IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */ - IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */ - IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */ - IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */ - IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */ - IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */ -}; - -/* Pad names for the pinmux subsystem */ -static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = { - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3), - IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT), - IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3), - IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22), - IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0), - IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62), - IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4), - IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18), - IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18), - IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK), - IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P), - IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P), - IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ), - IMX_PINCTRL_PIN(MX6Q_PAD_POR_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1), - IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B), - IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0), - IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6), - IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6), - IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2), - IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD), - IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3), -}; - -static struct imx_pinctrl_soc_info imx6q_pinctrl_info = { - .pins = imx6q_pinctrl_pads, - .npins = ARRAY_SIZE(imx6q_pinctrl_pads), - .pin_regs = imx6q_pin_regs, - .npin_regs = ARRAY_SIZE(imx6q_pin_regs), -}; - -static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = { - { .compatible = "fsl,imx6q-iomuxc", }, - { /* sentinel */ } -}; - -static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev) -{ - return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info); -} - -static struct platform_driver imx6q_pinctrl_driver = { - .driver = { - .name = "imx6q-pinctrl", - .owner = THIS_MODULE, - .of_match_table = of_match_ptr(imx6q_pinctrl_of_match), - }, - .probe = imx6q_pinctrl_probe, - .remove = __devexit_p(imx_pinctrl_remove), -}; - -static int __init imx6q_pinctrl_init(void) -{ - return platform_driver_register(&imx6q_pinctrl_driver); -} -arch_initcall(imx6q_pinctrl_init); - -static void __exit imx6q_pinctrl_exit(void) -{ - platform_driver_unregister(&imx6q_pinctrl_driver); -} -module_exit(imx6q_pinctrl_exit); -MODULE_AUTHOR("Dong Aisheng "); -MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/trunk/drivers/pinctrl/pinctrl-mxs.c b/trunk/drivers/pinctrl/pinctrl-mxs.c deleted file mode 100644 index 93cd959971c5..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-mxs.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "core.h" -#include "pinctrl-mxs.h" - -#define SUFFIX_LEN 4 - -struct mxs_pinctrl_data { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - struct mxs_pinctrl_soc_data *soc; -}; - -static int mxs_get_groups_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->ngroups; -} - -static const char *mxs_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->groups[group].name; -} - -static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, - const unsigned **pins, unsigned *num_pins) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *pins = d->soc->groups[group].pins; - *num_pins = d->soc->groups[group].npins; - - return 0; -} - -static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, - unsigned offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} - -static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct pinctrl_map *new_map; - char *group; - unsigned new_num; - unsigned long config = 0; - unsigned long *pconfig; - int length = strlen(np->name) + SUFFIX_LEN; - u32 val; - int ret; - - ret = of_property_read_u32(np, "fsl,drive-strength", &val); - if (!ret) - config = val | MA_PRESENT; - ret = of_property_read_u32(np, "fsl,voltage", &val); - if (!ret) - config |= val << VOL_SHIFT | VOL_PRESENT; - ret = of_property_read_u32(np, "fsl,pull-up", &val); - if (!ret) - config |= val << PULL_SHIFT | PULL_PRESENT; - - new_num = config ? 2 : 1; - new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; - new_map[0].data.mux.function = np->name; - - /* Compose group name */ - group = kzalloc(length, GFP_KERNEL); - if (!group) - return -ENOMEM; - of_property_read_u32(np, "reg", &val); - snprintf(group, length, "%s.%d", np->name, val); - new_map[0].data.mux.group = group; - - if (config) { - pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL); - if (!pconfig) { - ret = -ENOMEM; - goto free; - } - - new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP; - new_map[1].data.configs.group_or_pin = group; - new_map[1].data.configs.configs = pconfig; - new_map[1].data.configs.num_configs = 1; - } - - *map = new_map; - *num_maps = new_num; - - return 0; - -free: - kfree(new_map); - return ret; -} - -static void mxs_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) { - if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) - kfree(map[i].data.mux.group); - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - } - - kfree(map); -} - -static struct pinctrl_ops mxs_pinctrl_ops = { - .get_groups_count = mxs_get_groups_count, - .get_group_name = mxs_get_group_name, - .get_group_pins = mxs_get_group_pins, - .pin_dbg_show = mxs_pin_dbg_show, - .dt_node_to_map = mxs_dt_node_to_map, - .dt_free_map = mxs_dt_free_map, -}; - -static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->nfunctions; -} - -static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - return d->soc->functions[function].name; -} - -static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned group, - const char * const **groups, - unsigned * const num_groups) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *groups = d->soc->functions[group].groups; - *num_groups = d->soc->functions[group].ngroups; - - return 0; -} - -static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 bank, shift; - u16 pin; - int i; - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - reg = d->base + d->soc->regs->muxsel; - reg += bank * 0x20 + pin / 16 * 0x10; - shift = pin % 16 * 2; - - writel(0x3 << shift, reg + CLR); - writel(g->muxsel[i] << shift, reg + SET); - } - - return 0; -} - -static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - /* Nothing to do here */ -} - -static struct pinmux_ops mxs_pinmux_ops = { - .get_functions_count = mxs_pinctrl_get_funcs_count, - .get_function_name = mxs_pinctrl_get_func_name, - .get_function_groups = mxs_pinctrl_get_func_groups, - .enable = mxs_pinctrl_enable, - .disable = mxs_pinctrl_disable, -}; - -static int mxs_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long *config) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin, unsigned long config) -{ - return -ENOTSUPP; -} - -static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned group, unsigned long *config) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - - *config = d->soc->groups[group].config; - - return 0; -} - -static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, unsigned long config) -{ - struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); - struct mxs_group *g = &d->soc->groups[group]; - void __iomem *reg; - u8 ma, vol, pull, bank, shift; - u16 pin; - int i; - - ma = CONFIG_TO_MA(config); - vol = CONFIG_TO_VOL(config); - pull = CONFIG_TO_PULL(config); - - for (i = 0; i < g->npins; i++) { - bank = PINID_TO_BANK(g->pins[i]); - pin = PINID_TO_PIN(g->pins[i]); - - /* drive */ - reg = d->base + d->soc->regs->drive; - reg += bank * 0x40 + pin / 8 * 0x10; - - /* mA */ - if (config & MA_PRESENT) { - shift = pin % 8 * 4; - writel(0x3 << shift, reg + CLR); - writel(ma << shift, reg + SET); - } - - /* vol */ - if (config & VOL_PRESENT) { - shift = pin % 8 * 4 + 2; - if (vol) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - - /* pull */ - if (config & PULL_PRESENT) { - reg = d->base + d->soc->regs->pull; - reg += bank * 0x10; - shift = pin; - if (pull) - writel(1 << shift, reg + SET); - else - writel(1 << shift, reg + CLR); - } - } - - /* cache the config value for mxs_pinconf_group_get() */ - g->config = config; - - return 0; -} - -static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned pin) -{ - /* Not support */ -} - -static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned group) -{ - unsigned long config; - - if (!mxs_pinconf_group_get(pctldev, group, &config)) - seq_printf(s, "0x%lx", config); -} - -struct pinconf_ops mxs_pinconf_ops = { - .pin_config_get = mxs_pinconf_get, - .pin_config_set = mxs_pinconf_set, - .pin_config_group_get = mxs_pinconf_group_get, - .pin_config_group_set = mxs_pinconf_group_set, - .pin_config_dbg_show = mxs_pinconf_dbg_show, - .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show, -}; - -static struct pinctrl_desc mxs_pinctrl_desc = { - .pctlops = &mxs_pinctrl_ops, - .pmxops = &mxs_pinmux_ops, - .confops = &mxs_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev, - struct device_node *np, int idx, - const char **out_name) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - struct mxs_group *g = &d->soc->groups[idx]; - struct property *prop; - const char *propname = "fsl,pinmux-ids"; - char *group; - int length = strlen(np->name) + SUFFIX_LEN; - int i; - u32 val; - - group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); - if (!group) - return -ENOMEM; - of_property_read_u32(np, "reg", &val); - snprintf(group, length, "%s.%d", np->name, val); - g->name = group; - - prop = of_find_property(np, propname, &length); - if (!prop) - return -EINVAL; - g->npins = length / sizeof(u32); - - g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins), - GFP_KERNEL); - if (!g->pins) - return -ENOMEM; - - g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel), - GFP_KERNEL); - if (!g->muxsel) - return -ENOMEM; - - of_property_read_u32_array(np, propname, g->pins, g->npins); - for (i = 0; i < g->npins; i++) { - g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]); - g->pins[i] = MUXID_TO_PINID(g->pins[i]); - } - - *out_name = g->name; - - return 0; -} - -static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev, - struct mxs_pinctrl_data *d) -{ - struct mxs_pinctrl_soc_data *soc = d->soc; - struct device_node *np = pdev->dev.of_node; - struct device_node *child; - struct mxs_function *f; - const char *fn, *fnull = ""; - int i = 0, idxf = 0, idxg = 0; - int ret; - u32 val; - - child = of_get_next_child(np, NULL); - if (!child) { - dev_err(&pdev->dev, "no group is defined\n"); - return -ENOENT; - } - - /* Count total functions and groups */ - fn = fnull; - for_each_child_of_node(np, child) { - /* Skip pure pinconf node */ - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - fn = child->name; - soc->nfunctions++; - } - soc->ngroups++; - } - - soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions * - sizeof(*soc->functions), GFP_KERNEL); - if (!soc->functions) - return -ENOMEM; - - soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups * - sizeof(*soc->groups), GFP_KERNEL); - if (!soc->groups) - return -ENOMEM; - - /* Count groups for each function */ - fn = fnull; - f = &soc->functions[idxf]; - for_each_child_of_node(np, child) { - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->name = fn = child->name; - } - f->ngroups++; - }; - - /* Get groups for each function */ - idxf = 0; - fn = fnull; - for_each_child_of_node(np, child) { - if (of_property_read_u32(child, "reg", &val)) - continue; - if (strcmp(fn, child->name)) { - f = &soc->functions[idxf++]; - f->groups = devm_kzalloc(&pdev->dev, f->ngroups * - sizeof(*f->groups), - GFP_KERNEL); - if (!f->groups) - return -ENOMEM; - fn = child->name; - i = 0; - } - ret = mxs_pinctrl_parse_group(pdev, child, idxg++, - &f->groups[i++]); - if (ret) - return ret; - } - - return 0; -} - -int __devinit mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc) -{ - struct device_node *np = pdev->dev.of_node; - struct mxs_pinctrl_data *d; - int ret; - - d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL); - if (!d) - return -ENOMEM; - - d->dev = &pdev->dev; - d->soc = soc; - - d->base = of_iomap(np, 0); - if (!d->base) - return -EADDRNOTAVAIL; - - mxs_pinctrl_desc.pins = d->soc->pins; - mxs_pinctrl_desc.npins = d->soc->npins; - mxs_pinctrl_desc.name = dev_name(&pdev->dev); - - platform_set_drvdata(pdev, d); - - ret = mxs_pinctrl_probe_dt(pdev, d); - if (ret) { - dev_err(&pdev->dev, "dt probe failed: %d\n", ret); - goto err; - } - - d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d); - if (!d->pctl) { - dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n"); - ret = -EINVAL; - goto err; - } - - return 0; - -err: - iounmap(d->base); - return ret; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_probe); - -int __devexit mxs_pinctrl_remove(struct platform_device *pdev) -{ - struct mxs_pinctrl_data *d = platform_get_drvdata(pdev); - - pinctrl_unregister(d->pctl); - iounmap(d->base); - - return 0; -} -EXPORT_SYMBOL_GPL(mxs_pinctrl_remove); diff --git a/trunk/drivers/pinctrl/pinctrl-mxs.h b/trunk/drivers/pinctrl/pinctrl-mxs.h deleted file mode 100644 index fdd88d0bae22..000000000000 --- a/trunk/drivers/pinctrl/pinctrl-mxs.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#ifndef __PINCTRL_MXS_H -#define __PINCTRL_MXS_H - -#include -#include - -#define SET 0x4 -#define CLR 0x8 -#define TOG 0xc - -#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) -#define PINID(bank, pin) ((bank) * 32 + (pin)) - -/* - * pinmux-id bit field definitions - * - * bank: 15..12 (4) - * pin: 11..4 (8) - * muxsel: 3..0 (4) - */ -#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff) -#define MUXID_TO_MUXSEL(m) ((m) & 0xf) - -#define PINID_TO_BANK(p) ((p) >> 5) -#define PINID_TO_PIN(p) ((p) % 32) - -/* - * pin config bit field definitions - * - * pull-up: 6..5 (2) - * voltage: 4..3 (2) - * mA: 2..0 (3) - * - * MSB of each field is presence bit for the config. - */ -#define PULL_PRESENT (1 << 6) -#define PULL_SHIFT 5 -#define VOL_PRESENT (1 << 4) -#define VOL_SHIFT 3 -#define MA_PRESENT (1 << 2) -#define MA_SHIFT 0 -#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) -#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) -#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) - -struct mxs_function { - const char *name; - const char **groups; - unsigned ngroups; -}; - -struct mxs_group { - const char *name; - unsigned int *pins; - unsigned npins; - u8 *muxsel; - u8 config; -}; - -struct mxs_regs { - u16 muxsel; - u16 drive; - u16 pull; -}; - -struct mxs_pinctrl_soc_data { - const struct mxs_regs *regs; - const struct pinctrl_pin_desc *pins; - unsigned npins; - struct mxs_function *functions; - unsigned nfunctions; - struct mxs_group *groups; - unsigned ngroups; -}; - -int mxs_pinctrl_probe(struct platform_device *pdev, - struct mxs_pinctrl_soc_data *soc); -int mxs_pinctrl_remove(struct platform_device *pdev); - -#endif /* __PINCTRL_MXS_H */ diff --git a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c index 7644e42ac211..079dce0e93e9 100644 --- a/trunk/drivers/pinctrl/pinctrl-pxa3xx.c +++ b/trunk/drivers/pinctrl/pinctrl-pxa3xx.c @@ -25,18 +25,20 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = { .pin_base = 0, }; -static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev) +static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - return info->num_grps; + if (selector >= info->num_grps) + return -EINVAL; + return 0; } static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev, unsigned selector) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - + if (selector >= info->num_grps) + return NULL; return info->grps[selector].name; } @@ -46,23 +48,25 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev, unsigned *num_pins) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - + if (selector >= info->num_grps) + return -EINVAL; *pins = info->grps[selector].pins; *num_pins = info->grps[selector].npins; return 0; } static struct pinctrl_ops pxa3xx_pctrl_ops = { - .get_groups_count = pxa3xx_get_groups_count, + .list_groups = pxa3xx_list_groups, .get_group_name = pxa3xx_get_group_name, .get_group_pins = pxa3xx_get_group_pins, }; -static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev) +static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func) { struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); - - return info->num_funcs; + if (func >= info->num_funcs) + return -EINVAL; + return 0; } static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev, @@ -166,7 +170,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev, } static struct pinmux_ops pxa3xx_pmx_ops = { - .get_functions_count = pxa3xx_pmx_get_funcs_count, + .list_functions = pxa3xx_pmx_list_func, .get_function_name = pxa3xx_pmx_get_func_name, .get_function_groups = pxa3xx_pmx_get_groups, .enable = pxa3xx_pmx_enable, diff --git a/trunk/drivers/pinctrl/pinctrl-sirf.c b/trunk/drivers/pinctrl/pinctrl-sirf.c index ba15b1a29e52..6b3534cc051a 100644 --- a/trunk/drivers/pinctrl/pinctrl-sirf.c +++ b/trunk/drivers/pinctrl/pinctrl-sirf.c @@ -853,14 +853,18 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), }; -static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev) +static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(sirfsoc_pin_groups); + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return -EINVAL; + return 0; } static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return NULL; return sirfsoc_pin_groups[selector].name; } @@ -868,6 +872,8 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector const unsigned **pins, unsigned *num_pins) { + if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) + return -EINVAL; *pins = sirfsoc_pin_groups[selector].pins; *num_pins = sirfsoc_pin_groups[selector].num_pins; return 0; @@ -880,7 +886,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s } static struct pinctrl_ops sirfsoc_pctrl_ops = { - .get_groups_count = sirfsoc_get_groups_count, + .list_groups = sirfsoc_list_groups, .get_group_name = sirfsoc_get_group_name, .get_group_pins = sirfsoc_get_group_pins, .pin_dbg_show = sirfsoc_pin_dbg_show, @@ -1027,9 +1033,11 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector sirfsoc_pinmux_endisable(spmx, selector, false); } -static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev) +static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) { - return ARRAY_SIZE(sirfsoc_pmx_functions); + if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) + return -EINVAL; + return 0; } static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, @@ -1066,9 +1074,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev, } static struct pinmux_ops sirfsoc_pinmux_ops = { + .list_functions = sirfsoc_pinmux_list_funcs, .enable = sirfsoc_pinmux_enable, .disable = sirfsoc_pinmux_disable, - .get_functions_count = sirfsoc_pinmux_get_funcs_count, .get_function_name = sirfsoc_pinmux_get_func_name, .get_function_groups = sirfsoc_pinmux_get_groups, .gpio_request_enable = sirfsoc_pinmux_request_gpio, diff --git a/trunk/drivers/pinctrl/pinctrl-tegra.c b/trunk/drivers/pinctrl/pinctrl-tegra.c index 2c98fba01ca5..9b329688120c 100644 --- a/trunk/drivers/pinctrl/pinctrl-tegra.c +++ b/trunk/drivers/pinctrl/pinctrl-tegra.c @@ -23,11 +23,9 @@ #include #include #include -#include #include #include #include -#include #include @@ -55,11 +53,15 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) writel(val, pmx->regs[bank] + reg); } -static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev, + unsigned group) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->soc->ngroups; + if (group >= pmx->soc->ngroups) + return -EINVAL; + + return 0; } static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, @@ -67,6 +69,9 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (group >= pmx->soc->ngroups) + return NULL; + return pmx->soc->groups[group].name; } @@ -77,6 +82,9 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (group >= pmx->soc->ngroups) + return -EINVAL; + *pins = pmx->soc->groups[group].pins; *num_pins = pmx->soc->groups[group].npins; @@ -90,221 +98,22 @@ static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, " " DRIVER_NAME); } -static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, unsigned reserve) -{ - unsigned old_num = *reserved_maps; - unsigned new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) - return -ENOMEM; - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - const char *function) -{ - if (*num_maps == *reserved_maps) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps, - unsigned *num_maps, const char *group, - unsigned long *configs, unsigned num_configs) -{ - unsigned long *dup_configs; - - if (*num_maps == *reserved_maps) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static int add_config(unsigned long **configs, unsigned *num_configs, - unsigned long config) -{ - unsigned old_num = *num_configs; - unsigned new_num = old_num + 1; - unsigned long *new_configs; - - new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, - GFP_KERNEL); - if (!new_configs) - return -ENOMEM; - - new_configs[old_num] = config; - - *configs = new_configs; - *num_configs = new_num; - - return 0; -} - -void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static const struct cfg_param { - const char *property; - enum tegra_pinconf_param param; -} cfg_params[] = { - {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL}, - {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE}, - {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT}, - {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN}, - {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, - {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, - {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, - {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, - {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, - {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH}, - {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH}, - {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING}, - {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, -}; - -int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, - struct pinctrl_map **map, - unsigned *reserved_maps, - unsigned *num_maps) -{ - int ret, i; - const char *function; - u32 val; - unsigned long config; - unsigned long *configs = NULL; - unsigned num_configs = 0; - unsigned reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "nvidia,function", &function); - if (ret < 0) - function = NULL; - - for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { - ret = of_property_read_u32(np, cfg_params[i].property, &val); - if (!ret) { - config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); - ret = add_config(&configs, &num_configs, config); - if (ret < 0) - goto exit; - } - } - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "nvidia,pins"); - if (ret < 0) - goto exit; - reserve *= ret; - - ret = reserve_map(map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "nvidia,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(map, reserved_maps, num_maps, - group, configs, num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - unsigned reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps, - num_maps); - if (ret < 0) { - tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - static struct pinctrl_ops tegra_pinctrl_ops = { - .get_groups_count = tegra_pinctrl_get_groups_count, + .list_groups = tegra_pinctrl_list_groups, .get_group_name = tegra_pinctrl_get_group_name, .get_group_pins = tegra_pinctrl_get_group_pins, .pin_dbg_show = tegra_pinctrl_pin_dbg_show, - .dt_node_to_map = tegra_pinctrl_dt_node_to_map, - .dt_free_map = tegra_pinctrl_dt_free_map, }; -static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) +static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev, + unsigned function) { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - return pmx->soc->nfunctions; + if (function >= pmx->soc->nfunctions) + return -EINVAL; + + return 0; } static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, @@ -312,6 +121,9 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (function >= pmx->soc->nfunctions) + return NULL; + return pmx->soc->functions[function].name; } @@ -322,6 +134,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, { struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + if (function >= pmx->soc->nfunctions) + return -EINVAL; + *groups = pmx->soc->functions[function].groups; *num_groups = pmx->soc->functions[function].ngroups; @@ -336,6 +151,8 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, int i; u32 val; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; if (g->mux_reg < 0) @@ -363,6 +180,8 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, const struct tegra_pingroup *g; u32 val; + if (group >= pmx->soc->ngroups) + return; g = &pmx->soc->groups[group]; if (g->mux_reg < 0) @@ -375,7 +194,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, } static struct pinmux_ops tegra_pinmux_ops = { - .get_functions_count = tegra_pinctrl_get_funcs_count, + .list_functions = tegra_pinctrl_list_funcs, .get_function_name = tegra_pinctrl_get_func_name, .get_function_groups = tegra_pinctrl_get_func_groups, .enable = tegra_pinctrl_enable, @@ -505,6 +324,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, s16 reg; u32 val, mask; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); @@ -532,6 +353,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, s16 reg; u32 val, mask; + if (group >= pmx->soc->ngroups) + return -EINVAL; g = &pmx->soc->groups[group]; ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); diff --git a/trunk/drivers/pinctrl/pinctrl-u300.c b/trunk/drivers/pinctrl/pinctrl-u300.c index 05d029911be6..26eb8ccd72d5 100644 --- a/trunk/drivers/pinctrl/pinctrl-u300.c +++ b/trunk/drivers/pinctrl/pinctrl-u300.c @@ -836,14 +836,18 @@ static const struct u300_pin_group u300_pin_groups[] = { }, }; -static int u300_get_groups_count(struct pinctrl_dev *pctldev) +static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(u300_pin_groups); + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return -EINVAL; + return 0; } static const char *u300_get_group_name(struct pinctrl_dev *pctldev, unsigned selector) { + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return NULL; return u300_pin_groups[selector].name; } @@ -851,6 +855,8 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, const unsigned **pins, unsigned *num_pins) { + if (selector >= ARRAY_SIZE(u300_pin_groups)) + return -EINVAL; *pins = u300_pin_groups[selector].pins; *num_pins = u300_pin_groups[selector].num_pins; return 0; @@ -863,7 +869,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, } static struct pinctrl_ops u300_pctrl_ops = { - .get_groups_count = u300_get_groups_count, + .list_groups = u300_list_groups, .get_group_name = u300_get_group_name, .get_group_pins = u300_get_group_pins, .pin_dbg_show = u300_pin_dbg_show, @@ -985,9 +991,11 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector, u300_pmx_endisable(upmx, selector, false); } -static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) { - return ARRAY_SIZE(u300_pmx_functions); + if (selector >= ARRAY_SIZE(u300_pmx_functions)) + return -EINVAL; + return 0; } static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, @@ -1006,7 +1014,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector, } static struct pinmux_ops u300_pmx_ops = { - .get_functions_count = u300_pmx_get_funcs_count, + .list_functions = u300_pmx_list_funcs, .get_function_name = u300_pmx_get_func_name, .get_function_groups = u300_pmx_get_groups, .enable = u300_pmx_enable, diff --git a/trunk/drivers/pinctrl/pinmux.c b/trunk/drivers/pinctrl/pinmux.c index 220fa492c9f0..4e62783a573a 100644 --- a/trunk/drivers/pinctrl/pinmux.c +++ b/trunk/drivers/pinctrl/pinmux.c @@ -33,26 +33,22 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev) { const struct pinmux_ops *ops = pctldev->desc->pmxops; - unsigned nfuncs; unsigned selector = 0; /* Check that we implement required operations */ - if (!ops || - !ops->get_functions_count || + if (!ops->list_functions || !ops->get_function_name || !ops->get_function_groups || !ops->enable || - !ops->disable) { - dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); + !ops->disable) return -EINVAL; - } + /* Check that all functions registered have names */ - nfuncs = ops->get_functions_count(pctldev); - while (selector < nfuncs) { + while (ops->list_functions(pctldev, selector) >= 0) { const char *fname = ops->get_function_name(pctldev, selector); if (!fname) { - dev_err(pctldev->dev, "pinmux ops has no name for function%u\n", + pr_err("pinmux ops has no name for function%u\n", selector); return -EINVAL; } @@ -89,23 +85,20 @@ static int pin_request(struct pinctrl_dev *pctldev, const struct pinmux_ops *ops = pctldev->desc->pmxops; int status = -EINVAL; + dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner); + desc = pin_desc_get(pctldev, pin); if (desc == NULL) { dev_err(pctldev->dev, - "pin %d is not registered so it cannot be requested\n", - pin); + "pin is not registered so it cannot be requested\n"); goto out; } - dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", - pin, desc->name, owner); - if (gpio_range) { /* There's no need to support multiple GPIO requests */ if (desc->gpio_owner) { dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->gpio_owner, owner); + "pin already requested\n"); goto out; } @@ -113,8 +106,7 @@ static int pin_request(struct pinctrl_dev *pctldev, } else { if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { dev_err(pctldev->dev, - "pin %s already requested by %s; cannot claim for %s\n", - desc->name, desc->mux_owner, owner); + "pin already requested\n"); goto out; } @@ -147,7 +139,8 @@ static int pin_request(struct pinctrl_dev *pctldev, status = 0; if (status) { - dev_err(pctldev->dev, "request() failed for pin %d\n", pin); + dev_err(pctldev->dev, "->request on device %s failed for pin %d\n", + pctldev->desc->name, pin); module_put(pctldev->owner); } @@ -164,7 +157,7 @@ static int pin_request(struct pinctrl_dev *pctldev, out: if (status) dev_err(pctldev->dev, "pin-%d (%s) status %d\n", - pin, owner, status); + pin, owner, status); return status; } @@ -294,11 +287,10 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, const char *function) { const struct pinmux_ops *ops = pctldev->desc->pmxops; - unsigned nfuncs = ops->get_functions_count(pctldev); unsigned selector = 0; /* See if this pctldev has this function */ - while (selector < nfuncs) { + while (ops->list_functions(pctldev, selector) >= 0) { const char *fname = ops->get_function_name(pctldev, selector); @@ -327,32 +319,18 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, const unsigned *pins; unsigned num_pins; - if (!pmxops) { - dev_err(pctldev->dev, "does not support mux function\n"); - return -EINVAL; - } - - ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function); - if (ret < 0) { - dev_err(pctldev->dev, "invalid function %s in map table\n", - map->data.mux.function); - return ret; - } - setting->data.mux.func = ret; + setting->data.mux.func = + pinmux_func_name_to_selector(pctldev, map->data.mux.function); + if (setting->data.mux.func < 0) + return setting->data.mux.func; ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, &groups, &num_groups); - if (ret < 0) { - dev_err(pctldev->dev, "can't query groups for function %s\n", - map->data.mux.function); + if (ret < 0) return ret; - } - if (!num_groups) { - dev_err(pctldev->dev, - "function %s can't be selected on any group\n", - map->data.mux.function); + if (!num_groups) return -EINVAL; - } + if (map->data.mux.group) { bool found = false; group = map->data.mux.group; @@ -362,23 +340,15 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, break; } } - if (!found) { - dev_err(pctldev->dev, - "invalid group \"%s\" for function \"%s\"\n", - group, map->data.mux.function); + if (!found) return -EINVAL; - } } else { group = groups[0]; } - ret = pinctrl_get_group_selector(pctldev, group); - if (ret < 0) { - dev_err(pctldev->dev, "invalid group %s in map table\n", - map->data.mux.group); - return ret; - } - setting->data.mux.group = ret; + setting->data.mux.group = pinctrl_get_group_selector(pctldev, group); + if (setting->data.mux.group < 0) + return setting->data.mux.group; ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins, &num_pins); @@ -394,7 +364,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map, ret = pin_request(pctldev, pins[i], map->dev_name, NULL); if (ret) { dev_err(pctldev->dev, - "could not request pin %d on device %s\n", + "could not get request pin %d on device %s\n", pins[i], pinctrl_dev_get_name(pctldev)); /* On error release all taken pins */ i--; /* this pin just failed */ @@ -507,15 +477,11 @@ static int pinmux_functions_show(struct seq_file *s, void *what) { struct pinctrl_dev *pctldev = s->private; const struct pinmux_ops *pmxops = pctldev->desc->pmxops; - unsigned nfuncs; unsigned func_selector = 0; - if (!pmxops) - return 0; - mutex_lock(&pinctrl_mutex); - nfuncs = pmxops->get_functions_count(pctldev); - while (func_selector < nfuncs) { + + while (pmxops->list_functions(pctldev, func_selector) >= 0) { const char *func = pmxops->get_function_name(pctldev, func_selector); const char * const *groups; @@ -549,9 +515,6 @@ static int pinmux_pins_show(struct seq_file *s, void *what) const struct pinmux_ops *pmxops = pctldev->desc->pmxops; unsigned i, pin; - if (!pmxops) - return 0; - seq_puts(s, "Pinmux settings per pin\n"); seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); diff --git a/trunk/drivers/pinctrl/pinmux.h b/trunk/drivers/pinctrl/pinmux.h index d1a98b1c9fce..6fc47003e95d 100644 --- a/trunk/drivers/pinctrl/pinmux.h +++ b/trunk/drivers/pinctrl/pinmux.h @@ -31,6 +31,12 @@ void pinmux_free_setting(struct pinctrl_setting const *setting); int pinmux_enable_setting(struct pinctrl_setting const *setting); void pinmux_disable_setting(struct pinctrl_setting const *setting); +void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map); +void pinmux_show_setting(struct seq_file *s, + struct pinctrl_setting const *setting); +void pinmux_init_device_debugfs(struct dentry *devroot, + struct pinctrl_dev *pctldev); + #else static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) @@ -83,18 +89,6 @@ static inline void pinmux_disable_setting( { } -#endif - -#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS) - -void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map); -void pinmux_show_setting(struct seq_file *s, - struct pinctrl_setting const *setting); -void pinmux_init_device_debugfs(struct dentry *devroot, - struct pinctrl_dev *pctldev); - -#else - static inline void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) { diff --git a/trunk/drivers/pinctrl/spear/Kconfig b/trunk/drivers/pinctrl/spear/Kconfig deleted file mode 100644 index 6a2596b4f359..000000000000 --- a/trunk/drivers/pinctrl/spear/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -# -# ST Microelectronics SPEAr PINCTRL drivers -# - -if PLAT_SPEAR - -config PINCTRL_SPEAR - bool - depends on OF - select PINMUX - help - This enables pin control drivers for SPEAr Platform - -config PINCTRL_SPEAR3XX - bool - depends on ARCH_SPEAR3XX - select PINCTRL_SPEAR - -config PINCTRL_SPEAR300 - bool "ST Microelectronics SPEAr300 SoC pin controller driver" - depends on MACH_SPEAR300 - select PINCTRL_SPEAR3XX - -config PINCTRL_SPEAR310 - bool "ST Microelectronics SPEAr310 SoC pin controller driver" - depends on MACH_SPEAR310 - select PINCTRL_SPEAR3XX - -config PINCTRL_SPEAR320 - bool "ST Microelectronics SPEAr320 SoC pin controller driver" - depends on MACH_SPEAR320 - select PINCTRL_SPEAR3XX - -endif diff --git a/trunk/drivers/pinctrl/spear/Makefile b/trunk/drivers/pinctrl/spear/Makefile deleted file mode 100644 index 15dcb85da22d..000000000000 --- a/trunk/drivers/pinctrl/spear/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPEAr pinmux support - -obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o -obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o -obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o -obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o -obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear.c b/trunk/drivers/pinctrl/spear/pinctrl-spear.c deleted file mode 100644 index 5ae50aadf885..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * Inspired from: - * - U300 Pinctl drivers - * - Tegra Pinctl drivers - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pinctrl-spear.h" - -#define DRIVER_NAME "spear-pinmux" - -static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) -{ - return readl_relaxed(pmx->vbase + reg); -} - -static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) -{ - writel_relaxed(val, pmx->vbase + reg); -} - -static int set_mode(struct spear_pmx *pmx, int mode) -{ - struct spear_pmx_mode *pmx_mode = NULL; - int i; - u32 val; - - if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) - return -EINVAL; - - for (i = 0; i < pmx->machdata->npmx_modes; i++) { - if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { - pmx_mode = pmx->machdata->pmx_modes[i]; - break; - } - } - - if (!pmx_mode) - return -EINVAL; - - val = pmx_readl(pmx, pmx_mode->reg); - val &= ~pmx_mode->mask; - val |= pmx_mode->val; - pmx_writel(pmx, val, pmx_mode->reg); - - pmx->machdata->mode = pmx_mode->mode; - dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", - pmx_mode->name ? pmx_mode->name : "no_name", - pmx_mode->reg); - - return 0; -} - -void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) -{ - struct spear_pingroup *pgroup; - struct spear_modemux *modemux; - int i, j, group; - - for (group = 0; group < machdata->ngroups; group++) { - pgroup = machdata->groups[group]; - - for (i = 0; i < pgroup->nmodemuxs; i++) { - modemux = &pgroup->modemuxs[i]; - - for (j = 0; j < modemux->nmuxregs; j++) - if (modemux->muxregs[j].reg == 0xFFFF) - modemux->muxregs[j].reg = reg; - } - } -} - -static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->ngroups; -} - -static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned group) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->groups[group]->name; -} - -static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned group, const unsigned **pins, unsigned *num_pins) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *pins = pmx->machdata->groups[group]->pins; - *num_pins = pmx->machdata->groups[group]->npins; - - return 0; -} - -static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, unsigned offset) -{ - seq_printf(s, " " DRIVER_NAME); -} - -int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct device_node *np; - struct property *prop; - const char *function, *group; - int ret, index = 0, count = 0; - - /* calculate number of maps required */ - for_each_child_of_node(np_config, np) { - ret = of_property_read_string(np, "st,function", &function); - if (ret < 0) - return ret; - - ret = of_property_count_strings(np, "st,pins"); - if (ret < 0) - return ret; - - count += ret; - } - - if (!count) { - dev_err(pmx->dev, "No child nodes passed via DT\n"); - return -ENODEV; - } - - *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); - if (!*map) - return -ENOMEM; - - for_each_child_of_node(np_config, np) { - of_property_read_string(np, "st,function", &function); - of_property_for_each_string(np, "st,pins", prop, group) { - (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[index].data.mux.group = group; - (*map)[index].data.mux.function = function; - index++; - } - } - - *num_maps = count; - - return 0; -} - -void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps) -{ - kfree(map); -} - -static struct pinctrl_ops spear_pinctrl_ops = { - .get_groups_count = spear_pinctrl_get_groups_cnt, - .get_group_name = spear_pinctrl_get_group_name, - .get_group_pins = spear_pinctrl_get_group_pins, - .pin_dbg_show = spear_pinctrl_pin_dbg_show, - .dt_node_to_map = spear_pinctrl_dt_node_to_map, - .dt_free_map = spear_pinctrl_dt_free_map, -}; - -static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->nfunctions; -} - -static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned function) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - return pmx->machdata->functions[function]->name; -} - -static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned function, const char *const **groups, - unsigned * const ngroups) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - - *groups = pmx->machdata->functions[function]->groups; - *ngroups = pmx->machdata->functions[function]->ngroups; - - return 0; -} - -static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group, bool enable) -{ - struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct spear_pingroup *pgroup; - const struct spear_modemux *modemux; - struct spear_muxreg *muxreg; - u32 val, temp; - int i, j; - bool found = false; - - pgroup = pmx->machdata->groups[group]; - - for (i = 0; i < pgroup->nmodemuxs; i++) { - modemux = &pgroup->modemuxs[i]; - - /* SoC have any modes */ - if (pmx->machdata->modes_supported) { - if (!(pmx->machdata->mode & modemux->modes)) - continue; - } - - found = true; - for (j = 0; j < modemux->nmuxregs; j++) { - muxreg = &modemux->muxregs[j]; - - val = pmx_readl(pmx, muxreg->reg); - val &= ~muxreg->mask; - - if (enable) - temp = muxreg->val; - else - temp = ~muxreg->val; - - val |= temp; - pmx_writel(pmx, val, muxreg->reg); - } - } - - if (!found) { - dev_err(pmx->dev, "pinmux group: %s not supported\n", - pgroup->name); - return -ENODEV; - } - - return 0; -} - -static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, - unsigned group) -{ - return spear_pinctrl_endisable(pctldev, function, group, true); -} - -static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, - unsigned function, unsigned group) -{ - spear_pinctrl_endisable(pctldev, function, group, false); -} - -static struct pinmux_ops spear_pinmux_ops = { - .get_functions_count = spear_pinctrl_get_funcs_count, - .get_function_name = spear_pinctrl_get_func_name, - .get_function_groups = spear_pinctrl_get_func_groups, - .enable = spear_pinctrl_enable, - .disable = spear_pinctrl_disable, -}; - -static struct pinctrl_desc spear_pinctrl_desc = { - .name = DRIVER_NAME, - .pctlops = &spear_pinctrl_ops, - .pmxops = &spear_pinmux_ops, - .owner = THIS_MODULE, -}; - -int __devinit spear_pinctrl_probe(struct platform_device *pdev, - struct spear_pinctrl_machdata *machdata) -{ - struct device_node *np = pdev->dev.of_node; - struct resource *res; - struct spear_pmx *pmx; - - if (!machdata) - return -ENODEV; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) { - dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); - return -ENOMEM; - } - - pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); - if (!pmx->vbase) { - dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); - return -ENODEV; - } - - pmx->dev = &pdev->dev; - pmx->machdata = machdata; - - /* configure mode, if supported by SoC */ - if (machdata->modes_supported) { - int mode = 0; - - if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { - dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); - return -EINVAL; - } - - if (set_mode(pmx, mode)) { - dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", - mode); - return -EINVAL; - } - } - - platform_set_drvdata(pdev, pmx); - - spear_pinctrl_desc.pins = machdata->pins; - spear_pinctrl_desc.npins = machdata->npins; - - pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - return 0; -} - -int __devexit spear_pinctrl_remove(struct platform_device *pdev) -{ - struct spear_pmx *pmx = platform_get_drvdata(pdev); - - pinctrl_unregister(pmx->pctl); - - return 0; -} diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear.h b/trunk/drivers/pinctrl/spear/pinctrl-spear.h deleted file mode 100644 index 47a6b5b72f90..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Driver header file for the ST Microelectronics SPEAr pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PINMUX_SPEAR_H__ -#define __PINMUX_SPEAR_H__ - -#include -#include - -struct platform_device; -struct device; - -/** - * struct spear_pmx_mode - SPEAr pmx mode - * @name: name of pmx mode - * @mode: mode id - * @reg: register for configuring this mode - * @mask: mask of this mode in reg - * @val: val to be configured at reg after doing (val & mask) - */ -struct spear_pmx_mode { - const char *const name; - u16 mode; - u16 reg; - u16 mask; - u32 val; -}; - -/** - * struct spear_muxreg - SPEAr mux reg configuration - * @reg: register offset - * @mask: mask bits - * @val: val to be written on mask bits - */ -struct spear_muxreg { - u16 reg; - u32 mask; - u32 val; -}; - -/** - * struct spear_modemux - SPEAr mode mux configuration - * @modes: mode ids supported by this group of muxregs - * @nmuxregs: number of muxreg configurations to be done for modes - * @muxregs: array of muxreg configurations to be done for modes - */ -struct spear_modemux { - u16 modes; - u8 nmuxregs; - struct spear_muxreg *muxregs; -}; - -/** - * struct spear_pingroup - SPEAr pin group configurations - * @name: name of pin group - * @pins: array containing pin numbers - * @npins: size of pins array - * @modemuxs: array of modemux configurations for this pin group - * @nmodemuxs: size of array modemuxs - * - * A representation of a group of pins in the SPEAr pin controller. Each group - * allows some parameter or parameters to be configured. - */ -struct spear_pingroup { - const char *name; - const unsigned *pins; - unsigned npins; - struct spear_modemux *modemuxs; - unsigned nmodemuxs; -}; - -/** - * struct spear_function - SPEAr pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct spear_function { - const char *name; - const char *const *groups; - unsigned ngroups; -}; - -/** - * struct spear_pinctrl_machdata - SPEAr pin controller machine driver - * configuration - * @pins: An array describing all pins the pin controller affects. - * All pins which are also GPIOs must be listed first within the *array, - * and be numbered identically to the GPIO controller's *numbering. - * @npins: The numbmer of entries in @pins. - * @functions: An array describing all mux functions the SoC supports. - * @nfunctions: The numbmer of entries in @functions. - * @groups: An array describing all pin groups the pin SoC supports. - * @ngroups: The numbmer of entries in @groups. - * - * @modes_supported: Does SoC support modes - * @mode: mode configured from probe - * @pmx_modes: array of modes supported by SoC - * @npmx_modes: number of entries in pmx_modes. - */ -struct spear_pinctrl_machdata { - const struct pinctrl_pin_desc *pins; - unsigned npins; - struct spear_function **functions; - unsigned nfunctions; - struct spear_pingroup **groups; - unsigned ngroups; - - bool modes_supported; - u16 mode; - struct spear_pmx_mode **pmx_modes; - unsigned npmx_modes; -}; - -/** - * struct spear_pmx - SPEAr pinctrl mux - * @dev: pointer to struct dev of platform_device registered - * @pctl: pointer to struct pinctrl_dev - * @machdata: pointer to SoC or machine specific structure - * @vbase: virtual base address of pinmux controller - */ -struct spear_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - struct spear_pinctrl_machdata *machdata; - void __iomem *vbase; -}; - -/* exported routines */ -void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); -int __devinit spear_pinctrl_probe(struct platform_device *pdev, - struct spear_pinctrl_machdata *machdata); -int __devexit spear_pinctrl_remove(struct platform_device *pdev); -#endif /* __PINMUX_SPEAR_H__ */ diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear300.c b/trunk/drivers/pinctrl/spear/pinctrl-spear300.c deleted file mode 100644 index 9c82a35e4e78..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear300.c +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr300 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear300-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x00 -#define MODE_CONFIG_REG 0x04 - -/* modes */ -#define NAND_MODE (1 << 0) -#define NOR_MODE (1 << 1) -#define PHOTO_FRAME_MODE (1 << 2) -#define LEND_IP_PHONE_MODE (1 << 3) -#define HEND_IP_PHONE_MODE (1 << 4) -#define LEND_WIFI_PHONE_MODE (1 << 5) -#define HEND_WIFI_PHONE_MODE (1 << 6) -#define ATA_PABX_WI2S_MODE (1 << 7) -#define ATA_PABX_I2S_MODE (1 << 8) -#define CAML_LCDW_MODE (1 << 9) -#define CAMU_LCD_MODE (1 << 10) -#define CAMU_WLCD_MODE (1 << 11) -#define CAML_LCD_MODE (1 << 12) - -static struct spear_pmx_mode pmx_mode_nand = { - .name = "nand", - .mode = NAND_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x00, -}; - -static struct spear_pmx_mode pmx_mode_nor = { - .name = "nor", - .mode = NOR_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x01, -}; - -static struct spear_pmx_mode pmx_mode_photo_frame = { - .name = "photo frame mode", - .mode = PHOTO_FRAME_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x02, -}; - -static struct spear_pmx_mode pmx_mode_lend_ip_phone = { - .name = "lend ip phone mode", - .mode = LEND_IP_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x03, -}; - -static struct spear_pmx_mode pmx_mode_hend_ip_phone = { - .name = "hend ip phone mode", - .mode = HEND_IP_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x04, -}; - -static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { - .name = "lend wifi phone mode", - .mode = LEND_WIFI_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x05, -}; - -static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { - .name = "hend wifi phone mode", - .mode = HEND_WIFI_PHONE_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x06, -}; - -static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { - .name = "ata pabx wi2s mode", - .mode = ATA_PABX_WI2S_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x07, -}; - -static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { - .name = "ata pabx i2s mode", - .mode = ATA_PABX_I2S_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x08, -}; - -static struct spear_pmx_mode pmx_mode_caml_lcdw = { - .name = "caml lcdw mode", - .mode = CAML_LCDW_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0C, -}; - -static struct spear_pmx_mode pmx_mode_camu_lcd = { - .name = "camu lcd mode", - .mode = CAMU_LCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0D, -}; - -static struct spear_pmx_mode pmx_mode_camu_wlcd = { - .name = "camu wlcd mode", - .mode = CAMU_WLCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0xE, -}; - -static struct spear_pmx_mode pmx_mode_caml_lcd = { - .name = "caml lcd mode", - .mode = CAML_LCD_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x0000000F, - .val = 0x0F, -}; - -static struct spear_pmx_mode *spear300_pmx_modes[] = { - &pmx_mode_nand, - &pmx_mode_nor, - &pmx_mode_photo_frame, - &pmx_mode_lend_ip_phone, - &pmx_mode_hend_ip_phone, - &pmx_mode_lend_wifi_phone, - &pmx_mode_hend_wifi_phone, - &pmx_mode_ata_pabx_wi2s, - &pmx_mode_ata_pabx_i2s, - &pmx_mode_caml_lcdw, - &pmx_mode_camu_lcd, - &pmx_mode_camu_wlcd, - &pmx_mode_caml_lcd, -}; - -/* fsmc_2chips_pins */ -static const unsigned fsmc_2chips_pins[] = { 1, 97 }; -static struct spear_muxreg fsmc_2chips_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_2chips_modemux[] = { - { - .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .muxregs = fsmc_2chips_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), - }, -}; - -static struct spear_pingroup fsmc_2chips_pingroup = { - .name = "fsmc_2chips_grp", - .pins = fsmc_2chips_pins, - .npins = ARRAY_SIZE(fsmc_2chips_pins), - .modemuxs = fsmc_2chips_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), -}; - -/* fsmc_4chips_pins */ -static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; -static struct spear_muxreg fsmc_4chips_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_4chips_modemux[] = { - { - .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, - .muxregs = fsmc_4chips_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), - }, -}; - -static struct spear_pingroup fsmc_4chips_pingroup = { - .name = "fsmc_4chips_grp", - .pins = fsmc_4chips_pins, - .npins = ARRAY_SIZE(fsmc_4chips_pins), - .modemuxs = fsmc_4chips_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" -}; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* clcd_lcdmode_pins */ -static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; -static struct spear_muxreg clcd_lcdmode_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux clcd_lcdmode_modemux[] = { - { - .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | - CAMU_LCD_MODE | CAML_LCD_MODE, - .muxregs = clcd_lcdmode_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), - }, -}; - -static struct spear_pingroup clcd_lcdmode_pingroup = { - .name = "clcd_lcdmode_grp", - .pins = clcd_lcdmode_pins, - .npins = ARRAY_SIZE(clcd_lcdmode_pins), - .modemuxs = clcd_lcdmode_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), -}; - -/* clcd_pfmode_pins */ -static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; -static struct spear_muxreg clcd_pfmode_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux clcd_pfmode_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = clcd_pfmode_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), - }, -}; - -static struct spear_pingroup clcd_pfmode_pingroup = { - .name = "clcd_pfmode_grp", - .pins = clcd_pfmode_pins, - .npins = ARRAY_SIZE(clcd_pfmode_pins), - .modemuxs = clcd_pfmode_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), -}; - -static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" -}; -static struct spear_function clcd_function = { - .name = "clcd", - .groups = clcd_grps, - .ngroups = ARRAY_SIZE(clcd_grps), -}; - -/* tdm_pins */ -static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; -static struct spear_muxreg tdm_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_modemux tdm_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE - | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE - | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = tdm_muxreg, - .nmuxregs = ARRAY_SIZE(tdm_muxreg), - }, -}; - -static struct spear_pingroup tdm_pingroup = { - .name = "tdm_grp", - .pins = tdm_pins, - .npins = ARRAY_SIZE(tdm_pins), - .modemuxs = tdm_modemux, - .nmodemuxs = ARRAY_SIZE(tdm_modemux), -}; - -static const char *const tdm_grps[] = { "tdm_grp" }; -static struct spear_function tdm_function = { - .name = "tdm", - .groups = tdm_grps, - .ngroups = ARRAY_SIZE(tdm_grps), -}; - -/* i2c_clk_pins */ -static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; -static struct spear_muxreg i2c_clk_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux i2c_clk_modemux[] = { - { - .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | - LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE - | CAML_LCD_MODE, - .muxregs = i2c_clk_muxreg, - .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), - }, -}; - -static struct spear_pingroup i2c_clk_pingroup = { - .name = "i2c_clk_grp_grp", - .pins = i2c_clk_pins, - .npins = ARRAY_SIZE(i2c_clk_pins), - .modemuxs = i2c_clk_modemux, - .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), -}; - -static const char *const i2c_grps[] = { "i2c_clk_grp" }; -static struct spear_function i2c_function = { - .name = "i2c1", - .groups = i2c_grps, - .ngroups = ARRAY_SIZE(i2c_grps), -}; - -/* caml_pins */ -static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; -static struct spear_muxreg caml_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux caml_modemux[] = { - { - .modes = CAML_LCDW_MODE | CAML_LCD_MODE, - .muxregs = caml_muxreg, - .nmuxregs = ARRAY_SIZE(caml_muxreg), - }, -}; - -static struct spear_pingroup caml_pingroup = { - .name = "caml_grp", - .pins = caml_pins, - .npins = ARRAY_SIZE(caml_pins), - .modemuxs = caml_modemux, - .nmodemuxs = ARRAY_SIZE(caml_modemux), -}; - -/* camu_pins */ -static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; -static struct spear_muxreg camu_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux camu_modemux[] = { - { - .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, - .muxregs = camu_muxreg, - .nmuxregs = ARRAY_SIZE(camu_muxreg), - }, -}; - -static struct spear_pingroup camu_pingroup = { - .name = "camu_grp", - .pins = camu_pins, - .npins = ARRAY_SIZE(camu_pins), - .modemuxs = camu_modemux, - .nmodemuxs = ARRAY_SIZE(camu_modemux), -}; - -static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; -static struct spear_function cam_function = { - .name = "cam", - .groups = cam_grps, - .ngroups = ARRAY_SIZE(cam_grps), -}; - -/* dac_pins */ -static const unsigned dac_pins[] = { 43, 44 }; -static struct spear_muxreg dac_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK, - .val = 0, - }, -}; - -static struct spear_modemux dac_modemux[] = { - { - .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = dac_muxreg, - .nmuxregs = ARRAY_SIZE(dac_muxreg), - }, -}; - -static struct spear_pingroup dac_pingroup = { - .name = "dac_grp", - .pins = dac_pins, - .npins = ARRAY_SIZE(dac_pins), - .modemuxs = dac_modemux, - .nmodemuxs = ARRAY_SIZE(dac_modemux), -}; - -static const char *const dac_grps[] = { "dac_grp" }; -static struct spear_function dac_function = { - .name = "dac", - .groups = dac_grps, - .ngroups = ARRAY_SIZE(dac_grps), -}; - -/* i2s_pins */ -static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; -static struct spear_muxreg i2s_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux i2s_modemux[] = { - { - .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE - | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | - ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE - | CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = i2s_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_muxreg), - }, -}; - -static struct spear_pingroup i2s_pingroup = { - .name = "i2s_grp", - .pins = i2s_pins, - .npins = ARRAY_SIZE(i2s_pins), - .modemuxs = i2s_modemux, - .nmodemuxs = ARRAY_SIZE(i2s_modemux), -}; - -static const char *const i2s_grps[] = { "i2s_grp" }; -static struct spear_function i2s_function = { - .name = "i2s", - .groups = i2s_grps, - .ngroups = ARRAY_SIZE(i2s_grps), -}; - -/* sdhci_4bit_pins */ -static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; -static struct spear_muxreg sdhci_4bit_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - .val = 0, - }, -}; - -static struct spear_modemux sdhci_4bit_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, - .muxregs = sdhci_4bit_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), - }, -}; - -static struct spear_pingroup sdhci_4bit_pingroup = { - .name = "sdhci_4bit_grp", - .pins = sdhci_4bit_pins, - .npins = ARRAY_SIZE(sdhci_4bit_pins), - .modemuxs = sdhci_4bit_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), -}; - -/* sdhci_8bit_pins */ -static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, - 33 }; -static struct spear_muxreg sdhci_8bit_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | - PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | - PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux sdhci_8bit_modemux[] = { - { - .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | - HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | - HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | - CAMU_WLCD_MODE | CAML_LCD_MODE, - .muxregs = sdhci_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), - }, -}; - -static struct spear_pingroup sdhci_8bit_pingroup = { - .name = "sdhci_8bit_grp", - .pins = sdhci_8bit_pins, - .npins = ARRAY_SIZE(sdhci_8bit_pins), - .modemuxs = sdhci_8bit_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), -}; - -static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; -static struct spear_function sdhci_function = { - .name = "sdhci", - .groups = sdhci_grps, - .ngroups = ARRAY_SIZE(sdhci_grps), -}; - -/* gpio1_0_to_3_pins */ -static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; -static struct spear_muxreg gpio1_0_to_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux gpio1_0_to_3_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = gpio1_0_to_3_muxreg, - .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), - }, -}; - -static struct spear_pingroup gpio1_0_to_3_pingroup = { - .name = "gpio1_0_to_3_grp", - .pins = gpio1_0_to_3_pins, - .npins = ARRAY_SIZE(gpio1_0_to_3_pins), - .modemuxs = gpio1_0_to_3_modemux, - .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), -}; - -/* gpio1_4_to_7_pins */ -static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; - -static struct spear_muxreg gpio1_4_to_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux gpio1_4_to_7_modemux[] = { - { - .modes = PHOTO_FRAME_MODE, - .muxregs = gpio1_4_to_7_muxreg, - .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), - }, -}; - -static struct spear_pingroup gpio1_4_to_7_pingroup = { - .name = "gpio1_4_to_7_grp", - .pins = gpio1_4_to_7_pins, - .npins = ARRAY_SIZE(gpio1_4_to_7_pins), - .modemuxs = gpio1_4_to_7_modemux, - .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), -}; - -static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" -}; -static struct spear_function gpio1_function = { - .name = "gpio1", - .groups = gpio1_grps, - .ngroups = ARRAY_SIZE(gpio1_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear300_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &fsmc_2chips_pingroup, - &fsmc_4chips_pingroup, - &clcd_lcdmode_pingroup, - &clcd_pfmode_pingroup, - &tdm_pingroup, - &i2c_clk_pingroup, - &caml_pingroup, - &camu_pingroup, - &dac_pingroup, - &i2s_pingroup, - &sdhci_4bit_pingroup, - &sdhci_8bit_pingroup, - &gpio1_0_to_3_pingroup, - &gpio1_4_to_7_pingroup, -}; - -/* functions */ -static struct spear_function *spear300_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &fsmc_function, - &clcd_function, - &tdm_function, - &i2c_function, - &cam_function, - &dac_function, - &i2s_function, - &sdhci_function, - &gpio1_function, -}; - -static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear300-pinmux", - }, - {}, -}; - -static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear300_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); - spear3xx_machdata.functions = spear300_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); - - spear3xx_machdata.modes_supported = true; - spear3xx_machdata.pmx_modes = spear300_pmx_modes; - spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear300_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear300_pinctrl_of_match, - }, - .probe = spear300_pinctrl_probe, - .remove = __devexit_p(spear300_pinctrl_remove), -}; - -static int __init spear300_pinctrl_init(void) -{ - return platform_driver_register(&spear300_pinctrl_driver); -} -arch_initcall(spear300_pinctrl_init); - -static void __exit spear300_pinctrl_exit(void) -{ - platform_driver_unregister(&spear300_pinctrl_driver); -} -module_exit(spear300_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear310.c b/trunk/drivers/pinctrl/spear/pinctrl-spear310.c deleted file mode 100644 index 1a9707605125..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear310.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr310 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear310-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x08 - -/* emi_cs_0_to_5_pins */ -static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; -static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_modemux emi_cs_0_to_5_modemux[] = { - { - .muxregs = emi_cs_0_to_5_muxreg, - .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), - }, -}; - -static struct spear_pingroup emi_cs_0_to_5_pingroup = { - .name = "emi_cs_0_to_5_grp", - .pins = emi_cs_0_to_5_pins, - .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), - .modemuxs = emi_cs_0_to_5_modemux, - .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), -}; - -static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; -static struct spear_function emi_cs_0_to_5_function = { - .name = "emi", - .groups = emi_cs_0_to_5_grps, - .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), -}; - -/* uart1_pins */ -static const unsigned uart1_pins[] = { 0, 1 }; -static struct spear_muxreg uart1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart1_modemux[] = { - { - .muxregs = uart1_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_muxreg), - }, -}; - -static struct spear_pingroup uart1_pingroup = { - .name = "uart1_grp", - .pins = uart1_pins, - .npins = ARRAY_SIZE(uart1_pins), - .modemuxs = uart1_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modemux), -}; - -static const char *const uart1_grps[] = { "uart1_grp" }; -static struct spear_function uart1_function = { - .name = "uart1", - .groups = uart1_grps, - .ngroups = ARRAY_SIZE(uart1_grps), -}; - -/* uart2_pins */ -static const unsigned uart2_pins[] = { 43, 44 }; -static struct spear_muxreg uart2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart2_modemux[] = { - { - .muxregs = uart2_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_muxreg), - }, -}; - -static struct spear_pingroup uart2_pingroup = { - .name = "uart2_grp", - .pins = uart2_pins, - .npins = ARRAY_SIZE(uart2_pins), - .modemuxs = uart2_modemux, - .nmodemuxs = ARRAY_SIZE(uart2_modemux), -}; - -static const char *const uart2_grps[] = { "uart2_grp" }; -static struct spear_function uart2_function = { - .name = "uart2", - .groups = uart2_grps, - .ngroups = ARRAY_SIZE(uart2_grps), -}; - -/* uart3_pins */ -static const unsigned uart3_pins[] = { 37, 38 }; -static struct spear_muxreg uart3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart3_modemux[] = { - { - .muxregs = uart3_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_muxreg), - }, -}; - -static struct spear_pingroup uart3_pingroup = { - .name = "uart3_grp", - .pins = uart3_pins, - .npins = ARRAY_SIZE(uart3_pins), - .modemuxs = uart3_modemux, - .nmodemuxs = ARRAY_SIZE(uart3_modemux), -}; - -static const char *const uart3_grps[] = { "uart3_grp" }; -static struct spear_function uart3_function = { - .name = "uart3", - .groups = uart3_grps, - .ngroups = ARRAY_SIZE(uart3_grps), -}; - -/* uart4_pins */ -static const unsigned uart4_pins[] = { 39, 40 }; -static struct spear_muxreg uart4_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart4_modemux[] = { - { - .muxregs = uart4_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_muxreg), - }, -}; - -static struct spear_pingroup uart4_pingroup = { - .name = "uart4_grp", - .pins = uart4_pins, - .npins = ARRAY_SIZE(uart4_pins), - .modemuxs = uart4_modemux, - .nmodemuxs = ARRAY_SIZE(uart4_modemux), -}; - -static const char *const uart4_grps[] = { "uart4_grp" }; -static struct spear_function uart4_function = { - .name = "uart4", - .groups = uart4_grps, - .ngroups = ARRAY_SIZE(uart4_grps), -}; - -/* uart5_pins */ -static const unsigned uart5_pins[] = { 41, 42 }; -static struct spear_muxreg uart5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_modemux uart5_modemux[] = { - { - .muxregs = uart5_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_muxreg), - }, -}; - -static struct spear_pingroup uart5_pingroup = { - .name = "uart5_grp", - .pins = uart5_pins, - .npins = ARRAY_SIZE(uart5_pins), - .modemuxs = uart5_modemux, - .nmodemuxs = ARRAY_SIZE(uart5_modemux), -}; - -static const char *const uart5_grps[] = { "uart5_grp" }; -static struct spear_function uart5_function = { - .name = "uart5", - .groups = uart5_grps, - .ngroups = ARRAY_SIZE(uart5_grps), -}; - -/* fsmc_pins */ -static const unsigned fsmc_pins[] = { 34, 35, 36 }; -static struct spear_muxreg fsmc_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_modemux fsmc_modemux[] = { - { - .muxregs = fsmc_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_muxreg), - }, -}; - -static struct spear_pingroup fsmc_pingroup = { - .name = "fsmc_grp", - .pins = fsmc_pins, - .npins = ARRAY_SIZE(fsmc_pins), - .modemuxs = fsmc_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_grp" }; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* rs485_0_pins */ -static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; -static struct spear_muxreg rs485_0_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux rs485_0_modemux[] = { - { - .muxregs = rs485_0_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), - }, -}; - -static struct spear_pingroup rs485_0_pingroup = { - .name = "rs485_0_grp", - .pins = rs485_0_pins, - .npins = ARRAY_SIZE(rs485_0_pins), - .modemuxs = rs485_0_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), -}; - -static const char *const rs485_0_grps[] = { "rs485_0" }; -static struct spear_function rs485_0_function = { - .name = "rs485_0", - .groups = rs485_0_grps, - .ngroups = ARRAY_SIZE(rs485_0_grps), -}; - -/* rs485_1_pins */ -static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; -static struct spear_muxreg rs485_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux rs485_1_modemux[] = { - { - .muxregs = rs485_1_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), - }, -}; - -static struct spear_pingroup rs485_1_pingroup = { - .name = "rs485_1_grp", - .pins = rs485_1_pins, - .npins = ARRAY_SIZE(rs485_1_pins), - .modemuxs = rs485_1_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), -}; - -static const char *const rs485_1_grps[] = { "rs485_1" }; -static struct spear_function rs485_1_function = { - .name = "rs485_1", - .groups = rs485_1_grps, - .ngroups = ARRAY_SIZE(rs485_1_grps), -}; - -/* tdm_pins */ -static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; -static struct spear_muxreg tdm_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_modemux tdm_modemux[] = { - { - .muxregs = tdm_muxreg, - .nmuxregs = ARRAY_SIZE(tdm_muxreg), - }, -}; - -static struct spear_pingroup tdm_pingroup = { - .name = "tdm_grp", - .pins = tdm_pins, - .npins = ARRAY_SIZE(tdm_pins), - .modemuxs = tdm_modemux, - .nmodemuxs = ARRAY_SIZE(tdm_modemux), -}; - -static const char *const tdm_grps[] = { "tdm_grp" }; -static struct spear_function tdm_function = { - .name = "tdm", - .groups = tdm_grps, - .ngroups = ARRAY_SIZE(tdm_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear310_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &emi_cs_0_to_5_pingroup, - &uart1_pingroup, - &uart2_pingroup, - &uart3_pingroup, - &uart4_pingroup, - &uart5_pingroup, - &fsmc_pingroup, - &rs485_0_pingroup, - &rs485_1_pingroup, - &tdm_pingroup, -}; - -/* functions */ -static struct spear_function *spear310_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &emi_cs_0_to_5_function, - &uart1_function, - &uart2_function, - &uart3_function, - &uart4_function, - &uart5_function, - &fsmc_function, - &rs485_0_function, - &rs485_1_function, - &tdm_function, -}; - -static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear310-pinmux", - }, - {}, -}; - -static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear310_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); - spear3xx_machdata.functions = spear310_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - spear3xx_machdata.modes_supported = false; - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear310_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear310_pinctrl_of_match, - }, - .probe = spear310_pinctrl_probe, - .remove = __devexit_p(spear310_pinctrl_remove), -}; - -static int __init spear310_pinctrl_init(void) -{ - return platform_driver_register(&spear310_pinctrl_driver); -} -arch_initcall(spear310_pinctrl_init); - -static void __exit spear310_pinctrl_exit(void) -{ - platform_driver_unregister(&spear310_pinctrl_driver); -} -module_exit(spear310_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear320.c b/trunk/drivers/pinctrl/spear/pinctrl-spear320.c deleted file mode 100644 index de726e6c283a..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear320.c +++ /dev/null @@ -1,3468 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr320 pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include "pinctrl-spear3xx.h" - -#define DRIVER_NAME "spear320-pinmux" - -/* addresses */ -#define PMX_CONFIG_REG 0x0C -#define MODE_CONFIG_REG 0x10 -#define MODE_EXT_CONFIG_REG 0x18 - -/* modes */ -#define AUTO_NET_SMII_MODE (1 << 0) -#define AUTO_NET_MII_MODE (1 << 1) -#define AUTO_EXP_MODE (1 << 2) -#define SMALL_PRINTERS_MODE (1 << 3) -#define EXTENDED_MODE (1 << 4) - -static struct spear_pmx_mode pmx_mode_auto_net_smii = { - .name = "Automation Networking SMII mode", - .mode = AUTO_NET_SMII_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x0, -}; - -static struct spear_pmx_mode pmx_mode_auto_net_mii = { - .name = "Automation Networking MII mode", - .mode = AUTO_NET_MII_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x1, -}; - -static struct spear_pmx_mode pmx_mode_auto_exp = { - .name = "Automation Expanded mode", - .mode = AUTO_EXP_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x2, -}; - -static struct spear_pmx_mode pmx_mode_small_printers = { - .name = "Small Printers mode", - .mode = SMALL_PRINTERS_MODE, - .reg = MODE_CONFIG_REG, - .mask = 0x00000007, - .val = 0x3, -}; - -static struct spear_pmx_mode pmx_mode_extended = { - .name = "extended mode", - .mode = EXTENDED_MODE, - .reg = MODE_EXT_CONFIG_REG, - .mask = 0x00000001, - .val = 0x1, -}; - -static struct spear_pmx_mode *spear320_pmx_modes[] = { - &pmx_mode_auto_net_smii, - &pmx_mode_auto_net_mii, - &pmx_mode_auto_exp, - &pmx_mode_small_printers, - &pmx_mode_extended, -}; - -/* Extended mode registers and their offsets */ -#define EXT_CTRL_REG 0x0018 - #define MII_MDIO_MASK (1 << 4) - #define MII_MDIO_10_11_VAL 0 - #define MII_MDIO_81_VAL (1 << 4) - #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) - #define MAC_MODE_MII 0 - #define MAC_MODE_RMII 1 - #define MAC_MODE_SMII 2 - #define MAC_MODE_SS_SMII 3 - #define MAC_MODE_MASK 0x3 - #define MAC1_MODE_SHIFT 16 - #define MAC2_MODE_SHIFT 18 - -#define IP_SEL_PAD_0_9_REG 0x00A4 - #define PMX_PL_0_1_MASK (0x3F << 0) - #define PMX_UART2_PL_0_1_VAL 0x0 - #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) - - #define PMX_PL_2_3_MASK (0x3F << 6) - #define PMX_I2C2_PL_2_3_VAL 0x0 - #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) - #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_4_5_MASK (0x3F << 12) - #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) - #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) - #define PMX_PL_5_MASK (0x7 << 15) - #define PMX_TOUCH_Y_PL_5_VAL 0x0 - - #define PMX_PL_6_7_MASK (0x3F << 18) - #define PMX_PL_6_MASK (0x7 << 18) - #define PMX_PL_7_MASK (0x7 << 21) - #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_PWM_3_PL_6_VAL (0x2 << 18) - #define PMX_PWM_2_PL_7_VAL (0x2 << 21) - #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_8_9_MASK (0x3F << 24) - #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) - #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_10_19_REG 0x00A8 - #define PMX_PL_10_11_MASK (0x3F << 0) - #define PMX_SMII_PL_10_11_VAL 0 - #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_PL_12_MASK (0x7 << 6) - #define PMX_PWM3_PL_12_VAL 0 - #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) - - #define PMX_PL_13_14_MASK (0x3F << 9) - #define PMX_PL_13_MASK (0x7 << 9) - #define PMX_PL_14_MASK (0x7 << 12) - #define PMX_SSP2_PL_13_14_15_16_VAL 0 - #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) - #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) - #define PMX_PWM2_PL_13_VAL (0x2 << 9) - #define PMX_PWM1_PL_14_VAL (0x2 << 12) - - #define PMX_PL_15_MASK (0x7 << 15) - #define PMX_PWM0_PL_15_VAL (0x2 << 15) - #define PMX_PL_15_16_MASK (0x3F << 15) - #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) - #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) - - #define PMX_PL_17_18_MASK (0x3F << 21) - #define PMX_SSP1_PL_17_18_19_20_VAL 0 - #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_19_MASK (0x7 << 27) - #define PMX_I2C2_PL_19_VAL (0x1 << 27) - #define PMX_RMII_PL_19_VAL (0x4 << 27) - -#define IP_SEL_PAD_20_29_REG 0x00AC - #define PMX_PL_20_MASK (0x7 << 0) - #define PMX_I2C2_PL_20_VAL (0x1 << 0) - #define PMX_RMII_PL_20_VAL (0x4 << 0) - - #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) - #define PMX_SMII_PL_21_TO_27_VAL 0 - #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_28_29_MASK (0x3F << 24) - #define PMX_PL_28_MASK (0x7 << 24) - #define PMX_PL_29_MASK (0x7 << 27) - #define PMX_UART1_PL_28_29_VAL 0 - #define PMX_PWM_3_PL_28_VAL (0x4 << 24) - #define PMX_PWM_2_PL_29_VAL (0x4 << 27) - -#define IP_SEL_PAD_30_39_REG 0x00B0 - #define PMX_PL_30_31_MASK (0x3F << 0) - #define PMX_CAN1_PL_30_31_VAL (0) - #define PMX_PL_30_MASK (0x7 << 0) - #define PMX_PL_31_MASK (0x7 << 3) - #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) - #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) - #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) - - #define PMX_PL_32_33_MASK (0x3F << 6) - #define PMX_CAN0_PL_32_33_VAL 0 - #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) - #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_34_MASK (0x7 << 12) - #define PMX_PWM2_PL_34_VAL 0 - #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) - #define PMX_SSP2_PL_34_VAL (0x4 << 12) - - #define PMX_PL_35_MASK (0x7 << 15) - #define PMX_I2S_REF_CLK_PL_35_VAL 0 - #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) - #define PMX_SSP2_PL_35_VAL (0x4 << 15) - - #define PMX_PL_36_MASK (0x7 << 18) - #define PMX_TOUCH_X_PL_36_VAL 0 - #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) - #define PMX_SSP1_PL_36_VAL (0x4 << 18) - - #define PMX_PL_37_38_MASK (0x3F << 21) - #define PMX_PWM0_1_PL_37_38_VAL 0 - #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) - #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_39_MASK (0x7 << 27) - #define PMX_I2S_PL_39_VAL 0 - #define PMX_UART4_PL_39_VAL (0x2 << 27) - #define PMX_SSP1_PL_39_VAL (0x4 << 27) - -#define IP_SEL_PAD_40_49_REG 0x00B4 - #define PMX_PL_40_MASK (0x7 << 0) - #define PMX_I2S_PL_40_VAL 0 - #define PMX_UART4_PL_40_VAL (0x2 << 0) - #define PMX_PWM3_PL_40_VAL (0x4 << 0) - - #define PMX_PL_41_42_MASK (0x3F << 3) - #define PMX_PL_41_MASK (0x7 << 3) - #define PMX_PL_42_MASK (0x7 << 6) - #define PMX_I2S_PL_41_42_VAL 0 - #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) - #define PMX_PWM2_PL_41_VAL (0x4 << 3) - #define PMX_PWM1_PL_42_VAL (0x4 << 6) - - #define PMX_PL_43_MASK (0x7 << 9) - #define PMX_SDHCI_PL_43_VAL 0 - #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) - #define PMX_PWM0_PL_43_VAL (0x4 << 9) - - #define PMX_PL_44_45_MASK (0x3F << 12) - #define PMX_SDHCI_PL_44_45_VAL 0 - #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) - #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_46_47_MASK (0x3F << 18) - #define PMX_SDHCI_PL_46_47_VAL 0 - #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_48_49_MASK (0x3F << 24) - #define PMX_SDHCI_PL_48_49_VAL 0 - #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_50_59_REG 0x00B8 - #define PMX_PL_50_51_MASK (0x3F << 0) - #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) - #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) - #define PMX_PL_50_MASK (0x7 << 0) - #define PMX_PL_51_MASK (0x7 << 3) - #define PMX_SDHCI_PL_50_VAL 0 - #define PMX_SDHCI_CD_PL_51_VAL 0 - - #define PMX_PL_52_53_MASK (0x3F << 6) - #define PMX_FSMC_PL_52_53_VAL 0 - #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) - #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_54_55_56_MASK (0x1FF << 12) - #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) - - #define PMX_PL_57_MASK (0x7 << 21) - #define PMX_FSMC_PL_57_VAL 0 - #define PMX_PWM3_PL_57_VAL (0x4 << 21) - - #define PMX_PL_58_59_MASK (0x3F << 24) - #define PMX_PL_58_MASK (0x7 << 24) - #define PMX_PL_59_MASK (0x7 << 27) - #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_PWM2_PL_58_VAL (0x4 << 24) - #define PMX_PWM1_PL_59_VAL (0x4 << 27) - -#define IP_SEL_PAD_60_69_REG 0x00BC - #define PMX_PL_60_MASK (0x7 << 0) - #define PMX_FSMC_PL_60_VAL 0 - #define PMX_PWM0_PL_60_VAL (0x4 << 0) - - #define PMX_PL_61_TO_64_MASK (0xFFF << 3) - #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) - #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) - - #define PMX_PL_65_TO_68_MASK (0xFFF << 15) - #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) - #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) - - #define PMX_PL_69_MASK (0x7 << 27) - #define PMX_CLCD_PL_69_VAL (0) - #define PMX_EMI_PL_69_VAL (0x2 << 27) - #define PMX_SPP_PL_69_VAL (0x3 << 27) - #define PMX_UART5_PL_69_VAL (0x4 << 27) - -#define IP_SEL_PAD_70_79_REG 0x00C0 - #define PMX_PL_70_MASK (0x7 << 0) - #define PMX_CLCD_PL_70_VAL (0) - #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) - #define PMX_SPP_PL_70_VAL (0x3 << 0) - #define PMX_UART5_PL_70_VAL (0x4 << 0) - - #define PMX_PL_71_72_MASK (0x3F << 3) - #define PMX_CLCD_PL_71_72_VAL (0) - #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) - #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) - #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) - - #define PMX_PL_73_MASK (0x7 << 9) - #define PMX_CLCD_PL_73_VAL (0) - #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) - #define PMX_SPP_PL_73_VAL (0x3 << 9) - #define PMX_UART3_PL_73_VAL (0x4 << 9) - - #define PMX_PL_74_MASK (0x7 << 12) - #define PMX_CLCD_PL_74_VAL (0) - #define PMX_EMI_PL_74_VAL (0x2 << 12) - #define PMX_SPP_PL_74_VAL (0x3 << 12) - #define PMX_UART3_PL_74_VAL (0x4 << 12) - - #define PMX_PL_75_76_MASK (0x3F << 15) - #define PMX_CLCD_PL_75_76_VAL (0) - #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) - #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) - #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) - - #define PMX_PL_77_78_79_MASK (0x1FF << 21) - #define PMX_CLCD_PL_77_78_79_VAL (0) - #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) - #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) - #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_80_89_REG 0x00C4 - #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) - #define PMX_CLCD_PL_80_TO_85_VAL 0 - #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) - #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) - #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) - #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_86_87_MASK (0x3F << 18) - #define PMX_PL_86_MASK (0x7 << 18) - #define PMX_PL_87_MASK (0x7 << 21) - #define PMX_CLCD_PL_86_87_VAL 0 - #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_PWM3_PL_86_VAL (0x4 << 18) - #define PMX_PWM2_PL_87_VAL (0x4 << 21) - - #define PMX_PL_88_89_MASK (0x3F << 24) - #define PMX_CLCD_PL_88_89_VAL 0 - #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) - #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) - #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) - #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) - -#define IP_SEL_PAD_90_99_REG 0x00C8 - #define PMX_PL_90_91_MASK (0x3F << 0) - #define PMX_CLCD_PL_90_91_VAL 0 - #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) - #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) - #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) - #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_PL_92_93_MASK (0x3F << 6) - #define PMX_CLCD_PL_92_93_VAL 0 - #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) - #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) - #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) - #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) - - #define PMX_PL_94_95_MASK (0x3F << 12) - #define PMX_CLCD_PL_94_95_VAL 0 - #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) - #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) - #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) - #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) - - #define PMX_PL_96_97_MASK (0x3F << 18) - #define PMX_CLCD_PL_96_97_VAL 0 - #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) - #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) - #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) - #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) - - #define PMX_PL_98_MASK (0x7 << 24) - #define PMX_CLCD_PL_98_VAL 0 - #define PMX_I2C1_PL_98_VAL (0x2 << 24) - #define PMX_UART3_PL_98_VAL (0x4 << 24) - - #define PMX_PL_99_MASK (0x7 << 27) - #define PMX_SDHCI_PL_99_VAL 0 - #define PMX_I2C1_PL_99_VAL (0x2 << 27) - #define PMX_UART3_PL_99_VAL (0x4 << 27) - -#define IP_SEL_MIX_PAD_REG 0x00CC - #define PMX_PL_100_101_MASK (0x3F << 0) - #define PMX_SDHCI_PL_100_101_VAL 0 - #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) - - #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) - #define PMX_SSP1_PORT_94_TO_97_VAL 0 - #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) - #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) - #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) - #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) - - #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) - #define PMX_SSP2_PORT_90_TO_93_VAL 0 - #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) - #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) - #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) - #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) - - #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) - #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 - #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) - #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) - #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) - - #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) - #define PMX_UART3_PORT_94_VAL 0 - #define PMX_UART3_PORT_73_VAL (0x1 << 16) - #define PMX_UART3_PORT_52_VAL (0x2 << 16) - #define PMX_UART3_PORT_41_VAL (0x3 << 16) - #define PMX_UART3_PORT_15_VAL (0x4 << 16) - #define PMX_UART3_PORT_8_VAL (0x5 << 16) - #define PMX_UART3_PORT_99_VAL (0x6 << 16) - - #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) - #define PMX_UART4_PORT_92_VAL 0 - #define PMX_UART4_PORT_71_VAL (0x1 << 19) - #define PMX_UART4_PORT_39_VAL (0x2 << 19) - #define PMX_UART4_PORT_13_VAL (0x3 << 19) - #define PMX_UART4_PORT_6_VAL (0x4 << 19) - #define PMX_UART4_PORT_101_VAL (0x5 << 19) - - #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) - #define PMX_UART5_PORT_90_VAL 0 - #define PMX_UART5_PORT_69_VAL (0x1 << 22) - #define PMX_UART5_PORT_37_VAL (0x2 << 22) - #define PMX_UART5_PORT_4_VAL (0x3 << 22) - - #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) - #define PMX_UART6_PORT_88_VAL 0 - #define PMX_UART6_PORT_2_VAL (0x1 << 24) - - #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) - #define PMX_I2C1_PORT_8_9_VAL 0 - #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) - - #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) - #define PMX_I2C2_PORT_96_97_VAL 0 - #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) - #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) - #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) - #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) - - #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) - #define PMX_SDHCI_CD_PORT_12_VAL 0 - #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) - -/* Pad multiplexing for CLCD device */ -static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, - 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, - 97 }; -static struct spear_muxreg clcd_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_CLCD_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | - PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | - PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | - PMX_CLCD_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, - .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | - PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | - PMX_CLCD_PL_98_VAL, - }, -}; - -static struct spear_modemux clcd_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = clcd_muxreg, - .nmuxregs = ARRAY_SIZE(clcd_muxreg), - }, -}; - -static struct spear_pingroup clcd_pingroup = { - .name = "clcd_grp", - .pins = clcd_pins, - .npins = ARRAY_SIZE(clcd_pins), - .modemuxs = clcd_modemux, - .nmodemuxs = ARRAY_SIZE(clcd_modemux), -}; - -static const char *const clcd_grps[] = { "clcd_grp" }; -static struct spear_function clcd_function = { - .name = "clcd", - .groups = clcd_grps, - .ngroups = ARRAY_SIZE(clcd_grps), -}; - -/* Pad multiplexing for EMI (Parallel NOR flash) device */ -static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, - 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, - 93, 94, 95, 96, 97 }; -static struct spear_muxreg emi_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg emi_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, - .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | - PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, - .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | - PMX_FSMC_EMI_PL_54_55_56_VAL | - PMX_FSMC_EMI_PL_58_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_EMI_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | - PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | - PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | - PMX_EMI_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | - PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = EMI_FSMC_DYNAMIC_MUX_MASK, - .val = EMI_FSMC_DYNAMIC_MUX_MASK, - }, -}; - -static struct spear_modemux emi_modemux[] = { - { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = emi_muxreg, - .nmuxregs = ARRAY_SIZE(emi_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = emi_ext_muxreg, - .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), - }, -}; - -static struct spear_pingroup emi_pingroup = { - .name = "emi_grp", - .pins = emi_pins, - .npins = ARRAY_SIZE(emi_pins), - .modemuxs = emi_modemux, - .nmodemuxs = ARRAY_SIZE(emi_modemux), -}; - -static const char *const emi_grps[] = { "emi_grp" }; -static struct spear_function emi_function = { - .name = "emi", - .groups = emi_grps, - .ngroups = ARRAY_SIZE(emi_grps), -}; - -/* Pad multiplexing for FSMC (NAND flash) device */ -static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, - 61, 62, 63, 64, 65, 66, 67, 68 }; -static struct spear_muxreg fsmc_8bit_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | - PMX_PL_57_MASK | PMX_PL_58_59_MASK, - .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | - PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | - PMX_PL_65_TO_68_MASK, - .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | - PMX_FSMC_PL_65_TO_68_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = EMI_FSMC_DYNAMIC_MUX_MASK, - .val = EMI_FSMC_DYNAMIC_MUX_MASK, - }, -}; - -static struct spear_modemux fsmc_8bit_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = fsmc_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), - }, -}; - -static struct spear_pingroup fsmc_8bit_pingroup = { - .name = "fsmc_8bit_grp", - .pins = fsmc_8bit_pins, - .npins = ARRAY_SIZE(fsmc_8bit_pins), - .modemuxs = fsmc_8bit_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), -}; - -static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; -static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg fsmc_16bit_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, - .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, - .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | - PMX_FSMC_EMI_PL_73_VAL, - } -}; - -static struct spear_modemux fsmc_16bit_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = fsmc_8bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), - }, { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = fsmc_16bit_autoexp_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = fsmc_16bit_muxreg, - .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), - }, -}; - -static struct spear_pingroup fsmc_16bit_pingroup = { - .name = "fsmc_16bit_grp", - .pins = fsmc_16bit_pins, - .npins = ARRAY_SIZE(fsmc_16bit_pins), - .modemuxs = fsmc_16bit_modemux, - .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), -}; - -static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; -static struct spear_function fsmc_function = { - .name = "fsmc", - .groups = fsmc_grps, - .ngroups = ARRAY_SIZE(fsmc_grps), -}; - -/* Pad multiplexing for SPP device */ -static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85 }; -static struct spear_muxreg spp_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_SPP_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | - PMX_PL_74_MASK | PMX_PL_75_76_MASK | - PMX_PL_77_78_79_MASK, - .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | - PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | - PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, - }, { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK, - .val = PMX_SPP_PL_80_TO_85_VAL, - }, -}; - -static struct spear_modemux spp_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = spp_muxreg, - .nmuxregs = ARRAY_SIZE(spp_muxreg), - }, -}; - -static struct spear_pingroup spp_pingroup = { - .name = "spp_grp", - .pins = spp_pins, - .npins = ARRAY_SIZE(spp_pins), - .modemuxs = spp_modemux, - .nmodemuxs = ARRAY_SIZE(spp_modemux), -}; - -static const char *const spp_grps[] = { "spp_grp" }; -static struct spear_function spp_function = { - .name = "spp", - .groups = spp_grps, - .ngroups = ARRAY_SIZE(spp_grps), -}; - -/* Pad multiplexing for SDHCI device */ -static const unsigned sdhci_led_pins[] = { 34 }; -static struct spear_muxreg sdhci_led_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg sdhci_led_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK, - .val = PMX_PWM2_PL_34_VAL, - }, -}; - -static struct spear_modemux sdhci_led_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = sdhci_led_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = sdhci_led_ext_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), - }, -}; - -static struct spear_pingroup sdhci_led_pingroup = { - .name = "sdhci_led_grp", - .pins = sdhci_led_pins, - .npins = ARRAY_SIZE(sdhci_led_pins), - .modemuxs = sdhci_led_modemux, - .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), -}; - -static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, - 50}; -static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 -}; -static struct spear_muxreg sdhci_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg sdhci_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | - PMX_PL_48_49_MASK, - .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | - PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_MASK, - .val = PMX_SDHCI_PL_50_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_99_MASK, - .val = PMX_SDHCI_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_PL_100_101_MASK, - .val = PMX_SDHCI_PL_100_101_VAL, - }, -}; - -static struct spear_muxreg sdhci_cd_12_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_12_MASK, - .val = PMX_SDHCI_CD_PL_12_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SDHCI_CD_PORT_SEL_MASK, - .val = PMX_SDHCI_CD_PORT_12_VAL, - }, -}; - -static struct spear_muxreg sdhci_cd_51_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_51_MASK, - .val = PMX_SDHCI_CD_PL_51_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SDHCI_CD_PORT_SEL_MASK, - .val = PMX_SDHCI_CD_PORT_51_VAL, - }, -}; - -#define pmx_sdhci_common_modemux \ - { \ - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ - SMALL_PRINTERS_MODE | EXTENDED_MODE, \ - .muxregs = sdhci_muxreg, \ - .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ - }, { \ - .modes = EXTENDED_MODE, \ - .muxregs = sdhci_ext_muxreg, \ - .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ - } - -static struct spear_modemux sdhci_modemux[][3] = { - { - /* select pin 12 for cd */ - pmx_sdhci_common_modemux, - { - .modes = EXTENDED_MODE, - .muxregs = sdhci_cd_12_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), - }, - }, { - /* select pin 51 for cd */ - pmx_sdhci_common_modemux, - { - .modes = EXTENDED_MODE, - .muxregs = sdhci_cd_51_muxreg, - .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), - }, - } -}; - -static struct spear_pingroup sdhci_pingroup[] = { - { - .name = "sdhci_cd_12_grp", - .pins = sdhci_cd_12_pins, - .npins = ARRAY_SIZE(sdhci_cd_12_pins), - .modemuxs = sdhci_modemux[0], - .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), - }, { - .name = "sdhci_cd_51_grp", - .pins = sdhci_cd_51_pins, - .npins = ARRAY_SIZE(sdhci_cd_51_pins), - .modemuxs = sdhci_modemux[1], - .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), - }, -}; - -static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", - "sdhci_led_grp" }; - -static struct spear_function sdhci_function = { - .name = "sdhci", - .groups = sdhci_grps, - .ngroups = ARRAY_SIZE(sdhci_grps), -}; - -/* Pad multiplexing for I2S device */ -static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; -static struct spear_muxreg i2s_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg i2s_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, - .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, - .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, - }, -}; - -static struct spear_modemux i2s_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = i2s_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = i2s_ext_muxreg, - .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), - }, -}; - -static struct spear_pingroup i2s_pingroup = { - .name = "i2s_grp", - .pins = i2s_pins, - .npins = ARRAY_SIZE(i2s_pins), - .modemuxs = i2s_modemux, - .nmodemuxs = ARRAY_SIZE(i2s_modemux), -}; - -static const char *const i2s_grps[] = { "i2s_grp" }; -static struct spear_function i2s_function = { - .name = "i2s", - .groups = i2s_grps, - .ngroups = ARRAY_SIZE(i2s_grps), -}; - -/* Pad multiplexing for UART1 device */ -static const unsigned uart1_pins[] = { 28, 29 }; -static struct spear_muxreg uart1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_28_29_MASK, - .val = PMX_UART1_PL_28_29_VAL, - }, -}; - -static struct spear_modemux uart1_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart1_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), - }, -}; - -static struct spear_pingroup uart1_pingroup = { - .name = "uart1_grp", - .pins = uart1_pins, - .npins = ARRAY_SIZE(uart1_pins), - .modemuxs = uart1_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modemux), -}; - -static const char *const uart1_grps[] = { "uart1_grp" }; -static struct spear_function uart1_function = { - .name = "uart1", - .groups = uart1_grps, - .ngroups = ARRAY_SIZE(uart1_grps), -}; - -/* Pad multiplexing for UART1 Modem device */ -static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; -static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; -static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; -static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; - -static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, - .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | - PMX_UART1_ENH_PL_6_7_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | - PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | - PMX_PL_35_MASK | PMX_PL_36_MASK, - .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | - PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | - PMX_UART1_ENH_PL_36_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | - PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, - .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | - PMX_UART1_ENH_PL_36_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, - .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, - }, -}; - -static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK, - .val = PMX_UART1_ENH_PL_80_TO_85_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, - .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART1_ENH_PORT_SEL_MASK, - .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, - }, -}; - -static struct spear_modemux uart1_modem_2_to_7_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_2_to_7_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_31_to_36_modemux[] = { - { - .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart1_modem_31_to_36_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_31_to_36_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_34_to_45_modemux[] = { - { - .modes = AUTO_EXP_MODE | EXTENDED_MODE, - .muxregs = uart1_modem_34_to_45_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_34_to_45_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), - }, -}; - -static struct spear_modemux uart1_modem_80_to_85_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = uart1_modem_ext_80_to_85_muxreg, - .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), - }, -}; - -static struct spear_pingroup uart1_modem_pingroup[] = { - { - .name = "uart1_modem_2_to_7_grp", - .pins = uart1_modem_2_to_7_pins, - .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), - .modemuxs = uart1_modem_2_to_7_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), - }, { - .name = "uart1_modem_31_to_36_grp", - .pins = uart1_modem_31_to_36_pins, - .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), - .modemuxs = uart1_modem_31_to_36_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), - }, { - .name = "uart1_modem_34_to_45_grp", - .pins = uart1_modem_34_to_45_pins, - .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), - .modemuxs = uart1_modem_34_to_45_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), - }, { - .name = "uart1_modem_80_to_85_grp", - .pins = uart1_modem_80_to_85_pins, - .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), - .modemuxs = uart1_modem_80_to_85_modemux, - .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), - }, -}; - -static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", - "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", - "uart1_modem_80_to_85_grp" }; -static struct spear_function uart1_modem_function = { - .name = "uart1_modem", - .groups = uart1_modem_grps, - .ngroups = ARRAY_SIZE(uart1_modem_grps), -}; - -/* Pad multiplexing for UART2 device */ -static const unsigned uart2_pins[] = { 0, 1 }; -static struct spear_muxreg uart2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg uart2_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_0_1_MASK, - .val = PMX_UART2_PL_0_1_VAL, - }, -}; - -static struct spear_modemux uart2_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = uart2_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = uart2_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), - }, -}; - -static struct spear_pingroup uart2_pingroup = { - .name = "uart2_grp", - .pins = uart2_pins, - .npins = ARRAY_SIZE(uart2_pins), - .modemuxs = uart2_modemux, - .nmodemuxs = ARRAY_SIZE(uart2_modemux), -}; - -static const char *const uart2_grps[] = { "uart2_grp" }; -static struct spear_function uart2_function = { - .name = "uart2", - .groups = uart2_grps, - .ngroups = ARRAY_SIZE(uart2_grps), -}; - -/* Pad multiplexing for uart3 device */ -static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, - { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; - -static struct spear_muxreg uart3_ext_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_UART3_PL_8_9_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_8_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_15_16_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_15_16_MASK, - .val = PMX_UART3_PL_15_16_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_15_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_41_42_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_41_42_MASK, - .val = PMX_UART3_PL_41_42_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_41_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_52_53_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_52_53_MASK, - .val = PMX_UART3_PL_52_53_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_52_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_73_74_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, - .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_73_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_94_95_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_94_95_MASK, - .val = PMX_UART3_PL_94_95_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_94_VAL, - }, -}; - -static struct spear_muxreg uart3_ext_98_99_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, - .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART3_PORT_SEL_MASK, - .val = PMX_UART3_PORT_99_VAL, - }, -}; - -static struct spear_modemux uart3_modemux[][1] = { - { - /* Select signals on pins 8_9 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), - }, - }, { - /* Select signals on pins 15_16 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_15_16_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), - }, - }, { - /* Select signals on pins 41_42 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_41_42_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), - }, - }, { - /* Select signals on pins 52_53 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_52_53_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), - }, - }, { - /* Select signals on pins 73_74 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_73_74_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), - }, - }, { - /* Select signals on pins 94_95 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_94_95_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), - }, - }, { - /* Select signals on pins 98_99 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart3_ext_98_99_muxreg, - .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), - }, - }, -}; - -static struct spear_pingroup uart3_pingroup[] = { - { - .name = "uart3_8_9_grp", - .pins = uart3_pins[0], - .npins = ARRAY_SIZE(uart3_pins[0]), - .modemuxs = uart3_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), - }, { - .name = "uart3_15_16_grp", - .pins = uart3_pins[1], - .npins = ARRAY_SIZE(uart3_pins[1]), - .modemuxs = uart3_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), - }, { - .name = "uart3_41_42_grp", - .pins = uart3_pins[2], - .npins = ARRAY_SIZE(uart3_pins[2]), - .modemuxs = uart3_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), - }, { - .name = "uart3_52_53_grp", - .pins = uart3_pins[3], - .npins = ARRAY_SIZE(uart3_pins[3]), - .modemuxs = uart3_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), - }, { - .name = "uart3_73_74_grp", - .pins = uart3_pins[4], - .npins = ARRAY_SIZE(uart3_pins[4]), - .modemuxs = uart3_modemux[4], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), - }, { - .name = "uart3_94_95_grp", - .pins = uart3_pins[5], - .npins = ARRAY_SIZE(uart3_pins[5]), - .modemuxs = uart3_modemux[5], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), - }, { - .name = "uart3_98_99_grp", - .pins = uart3_pins[6], - .npins = ARRAY_SIZE(uart3_pins[6]), - .modemuxs = uart3_modemux[6], - .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), - }, -}; - -static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", - "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", - "uart3_94_95_grp", "uart3_98_99_grp" }; - -static struct spear_function uart3_function = { - .name = "uart3", - .groups = uart3_grps, - .ngroups = ARRAY_SIZE(uart3_grps), -}; - -/* Pad multiplexing for uart4 device */ -static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, - { 71, 72 }, { 92, 93 }, { 100, 101 } }; - -static struct spear_muxreg uart4_ext_6_7_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_6_7_MASK, - .val = PMX_UART4_PL_6_7_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_6_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_13_14_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_14_MASK, - .val = PMX_UART4_PL_13_14_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_13_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_39_40_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_39_MASK, - .val = PMX_UART4_PL_39_VAL, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK, - .val = PMX_UART4_PL_40_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_39_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_71_72_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_71_72_MASK, - .val = PMX_UART4_PL_71_72_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_71_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_92_93_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_92_93_MASK, - .val = PMX_UART4_PL_92_93_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PORT_92_VAL, - }, -}; - -static struct spear_muxreg uart4_ext_100_101_muxreg[] = { - { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_PL_100_101_MASK | - PMX_UART4_PORT_SEL_MASK, - .val = PMX_UART4_PL_100_101_VAL | - PMX_UART4_PORT_101_VAL, - }, -}; - -static struct spear_modemux uart4_modemux[][1] = { - { - /* Select signals on pins 6_7 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_6_7_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), - }, - }, { - /* Select signals on pins 13_14 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_13_14_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), - }, - }, { - /* Select signals on pins 39_40 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_39_40_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), - }, - }, { - /* Select signals on pins 71_72 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_71_72_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), - }, - }, { - /* Select signals on pins 92_93 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_92_93_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), - }, - }, { - /* Select signals on pins 100_101_ */ - { - .modes = EXTENDED_MODE, - .muxregs = uart4_ext_100_101_muxreg, - .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), - }, - }, -}; - -static struct spear_pingroup uart4_pingroup[] = { - { - .name = "uart4_6_7_grp", - .pins = uart4_pins[0], - .npins = ARRAY_SIZE(uart4_pins[0]), - .modemuxs = uart4_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), - }, { - .name = "uart4_13_14_grp", - .pins = uart4_pins[1], - .npins = ARRAY_SIZE(uart4_pins[1]), - .modemuxs = uart4_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), - }, { - .name = "uart4_39_40_grp", - .pins = uart4_pins[2], - .npins = ARRAY_SIZE(uart4_pins[2]), - .modemuxs = uart4_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), - }, { - .name = "uart4_71_72_grp", - .pins = uart4_pins[3], - .npins = ARRAY_SIZE(uart4_pins[3]), - .modemuxs = uart4_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), - }, { - .name = "uart4_92_93_grp", - .pins = uart4_pins[4], - .npins = ARRAY_SIZE(uart4_pins[4]), - .modemuxs = uart4_modemux[4], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), - }, { - .name = "uart4_100_101_grp", - .pins = uart4_pins[5], - .npins = ARRAY_SIZE(uart4_pins[5]), - .modemuxs = uart4_modemux[5], - .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), - }, -}; - -static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", - "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", - "uart4_100_101_grp" }; - -static struct spear_function uart4_function = { - .name = "uart4", - .groups = uart4_grps, - .ngroups = ARRAY_SIZE(uart4_grps), -}; - -/* Pad multiplexing for uart5 device */ -static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, - { 90, 91 } }; - -static struct spear_muxreg uart5_ext_4_5_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_I2C_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_4_5_MASK, - .val = PMX_UART5_PL_4_5_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_4_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_37_38_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_37_38_MASK, - .val = PMX_UART5_PL_37_38_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_37_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_69_70_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_69_MASK, - .val = PMX_UART5_PL_69_VAL, - }, { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_70_MASK, - .val = PMX_UART5_PL_70_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_69_VAL, - }, -}; - -static struct spear_muxreg uart5_ext_90_91_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK, - .val = PMX_UART5_PL_90_91_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART5_PORT_SEL_MASK, - .val = PMX_UART5_PORT_90_VAL, - }, -}; - -static struct spear_modemux uart5_modemux[][1] = { - { - /* Select signals on pins 4_5 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_4_5_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), - }, - }, { - /* Select signals on pins 37_38 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_37_38_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), - }, - }, { - /* Select signals on pins 69_70 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_69_70_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), - }, - }, { - /* Select signals on pins 90_91 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart5_ext_90_91_muxreg, - .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), - }, - }, -}; - -static struct spear_pingroup uart5_pingroup[] = { - { - .name = "uart5_4_5_grp", - .pins = uart5_pins[0], - .npins = ARRAY_SIZE(uart5_pins[0]), - .modemuxs = uart5_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), - }, { - .name = "uart5_37_38_grp", - .pins = uart5_pins[1], - .npins = ARRAY_SIZE(uart5_pins[1]), - .modemuxs = uart5_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), - }, { - .name = "uart5_69_70_grp", - .pins = uart5_pins[2], - .npins = ARRAY_SIZE(uart5_pins[2]), - .modemuxs = uart5_modemux[2], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), - }, { - .name = "uart5_90_91_grp", - .pins = uart5_pins[3], - .npins = ARRAY_SIZE(uart5_pins[3]), - .modemuxs = uart5_modemux[3], - .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), - }, -}; - -static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", - "uart5_69_70_grp", "uart5_90_91_grp" }; -static struct spear_function uart5_function = { - .name = "uart5", - .groups = uart5_grps, - .ngroups = ARRAY_SIZE(uart5_grps), -}; - -/* Pad multiplexing for uart6 device */ -static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; -static struct spear_muxreg uart6_ext_2_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK, - .val = PMX_UART6_PL_2_3_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART6_PORT_SEL_MASK, - .val = PMX_UART6_PORT_2_VAL, - }, -}; - -static struct spear_muxreg uart6_ext_88_89_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_88_89_MASK, - .val = PMX_UART6_PL_88_89_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_UART6_PORT_SEL_MASK, - .val = PMX_UART6_PORT_88_VAL, - }, -}; - -static struct spear_modemux uart6_modemux[][1] = { - { - /* Select signals on pins 2_3 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart6_ext_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), - }, - }, { - /* Select signals on pins 88_89 */ - { - .modes = EXTENDED_MODE, - .muxregs = uart6_ext_88_89_muxreg, - .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), - }, - }, -}; - -static struct spear_pingroup uart6_pingroup[] = { - { - .name = "uart6_2_3_grp", - .pins = uart6_pins[0], - .npins = ARRAY_SIZE(uart6_pins[0]), - .modemuxs = uart6_modemux[0], - .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), - }, { - .name = "uart6_88_89_grp", - .pins = uart6_pins[1], - .npins = ARRAY_SIZE(uart6_pins[1]), - .modemuxs = uart6_modemux[1], - .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), - }, -}; - -static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; -static struct spear_function uart6_function = { - .name = "uart6", - .groups = uart6_grps, - .ngroups = ARRAY_SIZE(uart6_grps), -}; - -/* UART - RS485 pmx */ -static const unsigned rs485_pins[] = { 77, 78, 79 }; -static struct spear_muxreg rs485_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_77_78_79_MASK, - .val = PMX_RS485_PL_77_78_79_VAL, - }, -}; - -static struct spear_modemux rs485_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = rs485_muxreg, - .nmuxregs = ARRAY_SIZE(rs485_muxreg), - }, -}; - -static struct spear_pingroup rs485_pingroup = { - .name = "rs485_grp", - .pins = rs485_pins, - .npins = ARRAY_SIZE(rs485_pins), - .modemuxs = rs485_modemux, - .nmodemuxs = ARRAY_SIZE(rs485_modemux), -}; - -static const char *const rs485_grps[] = { "rs485_grp" }; -static struct spear_function rs485_function = { - .name = "rs485", - .groups = rs485_grps, - .ngroups = ARRAY_SIZE(rs485_grps), -}; - -/* Pad multiplexing for Touchscreen device */ -static const unsigned touchscreen_pins[] = { 5, 36 }; -static struct spear_muxreg touchscreen_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg touchscreen_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_5_MASK, - .val = PMX_TOUCH_Y_PL_5_VAL, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_36_MASK, - .val = PMX_TOUCH_X_PL_36_VAL, - }, -}; - -static struct spear_modemux touchscreen_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = touchscreen_muxreg, - .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = touchscreen_ext_muxreg, - .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), - }, -}; - -static struct spear_pingroup touchscreen_pingroup = { - .name = "touchscreen_grp", - .pins = touchscreen_pins, - .npins = ARRAY_SIZE(touchscreen_pins), - .modemuxs = touchscreen_modemux, - .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), -}; - -static const char *const touchscreen_grps[] = { "touchscreen_grp" }; -static struct spear_function touchscreen_function = { - .name = "touchscreen", - .groups = touchscreen_grps, - .ngroups = ARRAY_SIZE(touchscreen_grps), -}; - -/* Pad multiplexing for CAN device */ -static const unsigned can0_pins[] = { 32, 33 }; -static struct spear_muxreg can0_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg can0_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_32_33_MASK, - .val = PMX_CAN0_PL_32_33_VAL, - }, -}; - -static struct spear_modemux can0_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | EXTENDED_MODE, - .muxregs = can0_muxreg, - .nmuxregs = ARRAY_SIZE(can0_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = can0_ext_muxreg, - .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), - }, -}; - -static struct spear_pingroup can0_pingroup = { - .name = "can0_grp", - .pins = can0_pins, - .npins = ARRAY_SIZE(can0_pins), - .modemuxs = can0_modemux, - .nmodemuxs = ARRAY_SIZE(can0_modemux), -}; - -static const char *const can0_grps[] = { "can0_grp" }; -static struct spear_function can0_function = { - .name = "can0", - .groups = can0_grps, - .ngroups = ARRAY_SIZE(can0_grps), -}; - -static const unsigned can1_pins[] = { 30, 31 }; -static struct spear_muxreg can1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg can1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_30_31_MASK, - .val = PMX_CAN1_PL_30_31_VAL, - }, -}; - -static struct spear_modemux can1_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE - | EXTENDED_MODE, - .muxregs = can1_muxreg, - .nmuxregs = ARRAY_SIZE(can1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = can1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), - }, -}; - -static struct spear_pingroup can1_pingroup = { - .name = "can1_grp", - .pins = can1_pins, - .npins = ARRAY_SIZE(can1_pins), - .modemuxs = can1_modemux, - .nmodemuxs = ARRAY_SIZE(can1_modemux), -}; - -static const char *const can1_grps[] = { "can1_grp" }; -static struct spear_function can1_function = { - .name = "can1", - .groups = can1_grps, - .ngroups = ARRAY_SIZE(can1_grps), -}; - -/* Pad multiplexing for PWM0_1 device */ -static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, - { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; - -static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_PWM_0_1_PL_8_9_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, - .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, - .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_net_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { - { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_37_38_MASK, - .val = PMX_PWM0_1_PL_37_38_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, - .val = PMX_PWM1_PL_42_VAL | - PMX_PWM0_PL_43_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_59_MASK, - .val = PMX_PWM1_PL_59_VAL, - }, { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_60_MASK, - .val = PMX_PWM0_PL_60_VAL, - }, -}; - -static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_88_89_MASK, - .val = PMX_PWM0_1_PL_88_89_VAL, - }, -}; - -static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = pwm0_1_autoexpsmallpri_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_14_15_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_30_31_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = pwm0_1_net_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_37_38_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_42_43_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_59_60_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), - }, -}; - -static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm0_1_pin_88_89_muxreg, - .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), - }, -}; - -static struct spear_pingroup pwm0_1_pingroup[] = { - { - .name = "pwm0_1_pin_8_9_grp", - .pins = pwm0_1_pins[0], - .npins = ARRAY_SIZE(pwm0_1_pins[0]), - .modemuxs = pwm0_1_pin_8_9_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), - }, { - .name = "pwm0_1_pin_14_15_grp", - .pins = pwm0_1_pins[1], - .npins = ARRAY_SIZE(pwm0_1_pins[1]), - .modemuxs = pwm0_1_pin_14_15_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), - }, { - .name = "pwm0_1_pin_30_31_grp", - .pins = pwm0_1_pins[2], - .npins = ARRAY_SIZE(pwm0_1_pins[2]), - .modemuxs = pwm0_1_pin_30_31_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), - }, { - .name = "pwm0_1_pin_37_38_grp", - .pins = pwm0_1_pins[3], - .npins = ARRAY_SIZE(pwm0_1_pins[3]), - .modemuxs = pwm0_1_pin_37_38_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), - }, { - .name = "pwm0_1_pin_42_43_grp", - .pins = pwm0_1_pins[4], - .npins = ARRAY_SIZE(pwm0_1_pins[4]), - .modemuxs = pwm0_1_pin_42_43_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), - }, { - .name = "pwm0_1_pin_59_60_grp", - .pins = pwm0_1_pins[5], - .npins = ARRAY_SIZE(pwm0_1_pins[5]), - .modemuxs = pwm0_1_pin_59_60_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), - }, { - .name = "pwm0_1_pin_88_89_grp", - .pins = pwm0_1_pins[6], - .npins = ARRAY_SIZE(pwm0_1_pins[6]), - .modemuxs = pwm0_1_pin_88_89_modemux, - .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), - }, -}; - -static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", - "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", - "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" -}; - -static struct spear_function pwm0_1_function = { - .name = "pwm0_1", - .groups = pwm0_1_grps, - .ngroups = ARRAY_SIZE(pwm0_1_grps), -}; - -/* Pad multiplexing for PWM2 device */ -static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, - { 58 }, { 87 } }; -static struct spear_muxreg pwm2_net_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm2_pin_7_muxreg[] = { - { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_7_MASK, - .val = PMX_PWM_2_PL_7_VAL, - }, -}; - -static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm2_pin_13_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_MASK, - .val = PMX_PWM2_PL_13_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_29_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN1_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_29_MASK, - .val = PMX_PWM_2_PL_29_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_34_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_34_MASK, - .val = PMX_PWM2_PL_34_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_41_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_41_MASK, - .val = PMX_PWM2_PL_41_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_58_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_58_MASK, - .val = PMX_PWM2_PL_58_VAL, - }, -}; - -static struct spear_muxreg pwm2_pin_87_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_87_MASK, - .val = PMX_PWM2_PL_87_VAL, - }, -}; - -static struct spear_modemux pwm2_pin_7_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, - .muxregs = pwm2_net_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_7_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_13_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = pwm2_autoexpsmallpri_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_13_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_29_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_29_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), - }, -}; -static struct spear_modemux pwm2_pin_34_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_34_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_41_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_41_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_58_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_58_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), - }, -}; - -static struct spear_modemux pwm2_pin_87_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm2_pin_87_muxreg, - .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), - }, -}; - -static struct spear_pingroup pwm2_pingroup[] = { - { - .name = "pwm2_pin_7_grp", - .pins = pwm2_pins[0], - .npins = ARRAY_SIZE(pwm2_pins[0]), - .modemuxs = pwm2_pin_7_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), - }, { - .name = "pwm2_pin_13_grp", - .pins = pwm2_pins[1], - .npins = ARRAY_SIZE(pwm2_pins[1]), - .modemuxs = pwm2_pin_13_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), - }, { - .name = "pwm2_pin_29_grp", - .pins = pwm2_pins[2], - .npins = ARRAY_SIZE(pwm2_pins[2]), - .modemuxs = pwm2_pin_29_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), - }, { - .name = "pwm2_pin_34_grp", - .pins = pwm2_pins[3], - .npins = ARRAY_SIZE(pwm2_pins[3]), - .modemuxs = pwm2_pin_34_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), - }, { - .name = "pwm2_pin_41_grp", - .pins = pwm2_pins[4], - .npins = ARRAY_SIZE(pwm2_pins[4]), - .modemuxs = pwm2_pin_41_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), - }, { - .name = "pwm2_pin_58_grp", - .pins = pwm2_pins[5], - .npins = ARRAY_SIZE(pwm2_pins[5]), - .modemuxs = pwm2_pin_58_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), - }, { - .name = "pwm2_pin_87_grp", - .pins = pwm2_pins[6], - .npins = ARRAY_SIZE(pwm2_pins[6]), - .modemuxs = pwm2_pin_87_modemux, - .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), - }, -}; - -static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", - "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", - "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; -static struct spear_function pwm2_function = { - .name = "pwm2", - .groups = pwm2_grps, - .ngroups = ARRAY_SIZE(pwm2_grps), -}; - -/* Pad multiplexing for PWM3 device */ -static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, - { 86 } }; -static struct spear_muxreg pwm3_pin_6_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_6_MASK, - .val = PMX_PWM_3_PL_6_VAL, - }, -}; - -static struct spear_muxreg pwm3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg pwm3_pin_12_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_12_MASK, - .val = PMX_PWM3_PL_12_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_28_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_GPIO_PIN0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_28_MASK, - .val = PMX_PWM_3_PL_28_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_40_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_40_MASK, - .val = PMX_PWM3_PL_40_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_57_muxreg[] = { - { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_57_MASK, - .val = PMX_PWM3_PL_57_VAL, - }, -}; - -static struct spear_muxreg pwm3_pin_86_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_86_MASK, - .val = PMX_PWM3_PL_86_VAL, - }, -}; - -static struct spear_modemux pwm3_pin_6_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_6_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_12_modemux[] = { - { - .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | - AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = pwm3_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_12_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_28_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_28_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_40_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_40_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_57_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_57_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), - }, -}; - -static struct spear_modemux pwm3_pin_86_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = pwm3_pin_86_muxreg, - .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), - }, -}; - -static struct spear_pingroup pwm3_pingroup[] = { - { - .name = "pwm3_pin_6_grp", - .pins = pwm3_pins[0], - .npins = ARRAY_SIZE(pwm3_pins[0]), - .modemuxs = pwm3_pin_6_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), - }, { - .name = "pwm3_pin_12_grp", - .pins = pwm3_pins[1], - .npins = ARRAY_SIZE(pwm3_pins[1]), - .modemuxs = pwm3_pin_12_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), - }, { - .name = "pwm3_pin_28_grp", - .pins = pwm3_pins[2], - .npins = ARRAY_SIZE(pwm3_pins[2]), - .modemuxs = pwm3_pin_28_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), - }, { - .name = "pwm3_pin_40_grp", - .pins = pwm3_pins[3], - .npins = ARRAY_SIZE(pwm3_pins[3]), - .modemuxs = pwm3_pin_40_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), - }, { - .name = "pwm3_pin_57_grp", - .pins = pwm3_pins[4], - .npins = ARRAY_SIZE(pwm3_pins[4]), - .modemuxs = pwm3_pin_57_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), - }, { - .name = "pwm3_pin_86_grp", - .pins = pwm3_pins[5], - .npins = ARRAY_SIZE(pwm3_pins[5]), - .modemuxs = pwm3_pin_86_modemux, - .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), - }, -}; - -static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", - "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", - "pwm3_pin_86_grp" }; -static struct spear_function pwm3_function = { - .name = "pwm3", - .groups = pwm3_grps, - .ngroups = ARRAY_SIZE(pwm3_grps), -}; - -/* Pad multiplexing for SSP1 device */ -static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, - { 65, 68 }, { 94, 97 } }; -static struct spear_muxreg ssp1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, - .val = PMX_SSP1_PL_17_18_19_20_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK, - .val = PMX_SSP1_PL_17_18_19_20_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_17_TO_20_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, - .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | - PMX_SSP1_PL_39_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_36_TO_39_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_48_49_MASK, - .val = PMX_SSP1_PL_48_49_VAL, - }, { - .reg = IP_SEL_PAD_50_59_REG, - .mask = PMX_PL_50_51_MASK, - .val = PMX_SSP1_PL_50_51_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_48_TO_51_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_65_TO_68_MASK, - .val = PMX_SSP1_PL_65_TO_68_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_65_TO_68_VAL, - }, -}; - -static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP1_PORT_SEL_MASK, - .val = PMX_SSP1_PORT_94_TO_97_VAL, - }, -}; - -static struct spear_modemux ssp1_17_20_modemux[] = { - { - .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | - EXTENDED_MODE, - .muxregs = ssp1_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_17_20_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), - }, -}; - -static struct spear_modemux ssp1_36_39_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_36_39_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), - }, -}; - -static struct spear_modemux ssp1_48_51_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_48_51_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), - }, -}; -static struct spear_modemux ssp1_65_68_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_65_68_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), - }, -}; - -static struct spear_modemux ssp1_94_97_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp1_ext_94_97_muxreg, - .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), - }, -}; - -static struct spear_pingroup ssp1_pingroup[] = { - { - .name = "ssp1_17_20_grp", - .pins = ssp1_pins[0], - .npins = ARRAY_SIZE(ssp1_pins[0]), - .modemuxs = ssp1_17_20_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), - }, { - .name = "ssp1_36_39_grp", - .pins = ssp1_pins[1], - .npins = ARRAY_SIZE(ssp1_pins[1]), - .modemuxs = ssp1_36_39_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), - }, { - .name = "ssp1_48_51_grp", - .pins = ssp1_pins[2], - .npins = ARRAY_SIZE(ssp1_pins[2]), - .modemuxs = ssp1_48_51_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), - }, { - .name = "ssp1_65_68_grp", - .pins = ssp1_pins[3], - .npins = ARRAY_SIZE(ssp1_pins[3]), - .modemuxs = ssp1_65_68_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), - }, { - .name = "ssp1_94_97_grp", - .pins = ssp1_pins[4], - .npins = ARRAY_SIZE(ssp1_pins[4]), - .modemuxs = ssp1_94_97_modemux, - .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), - }, -}; - -static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", - "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" -}; -static struct spear_function ssp1_function = { - .name = "ssp1", - .groups = ssp1_grps, - .ngroups = ARRAY_SIZE(ssp1_grps), -}; - -/* Pad multiplexing for SSP2 device */ -static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, - { 61, 64 }, { 90, 93 } }; -static struct spear_muxreg ssp2_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, - .val = PMX_SSP2_PL_13_14_15_16_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_13_TO_16_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | - PMX_GPIO_PIN5_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_30_39_REG, - .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, - .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | - PMX_SSP2_PL_35_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_32_TO_35_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_40_49_REG, - .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, - .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_44_TO_47_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { - { - .reg = IP_SEL_PAD_60_69_REG, - .mask = PMX_PL_61_TO_64_MASK, - .val = PMX_SSP2_PL_61_TO_64_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_61_TO_64_VAL, - }, -}; - -static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, - .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_SSP2_PORT_SEL_MASK, - .val = PMX_SSP2_PORT_90_TO_93_VAL, - }, -}; - -static struct spear_modemux ssp2_13_16_modemux[] = { - { - .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, - .muxregs = ssp2_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_13_16_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), - }, -}; - -static struct spear_modemux ssp2_32_35_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_32_35_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), - }, -}; - -static struct spear_modemux ssp2_44_47_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_44_47_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), - }, -}; - -static struct spear_modemux ssp2_61_64_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_61_64_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), - }, -}; - -static struct spear_modemux ssp2_90_93_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = ssp2_ext_90_93_muxreg, - .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), - }, -}; - -static struct spear_pingroup ssp2_pingroup[] = { - { - .name = "ssp2_13_16_grp", - .pins = ssp2_pins[0], - .npins = ARRAY_SIZE(ssp2_pins[0]), - .modemuxs = ssp2_13_16_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), - }, { - .name = "ssp2_32_35_grp", - .pins = ssp2_pins[1], - .npins = ARRAY_SIZE(ssp2_pins[1]), - .modemuxs = ssp2_32_35_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), - }, { - .name = "ssp2_44_47_grp", - .pins = ssp2_pins[2], - .npins = ARRAY_SIZE(ssp2_pins[2]), - .modemuxs = ssp2_44_47_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), - }, { - .name = "ssp2_61_64_grp", - .pins = ssp2_pins[3], - .npins = ARRAY_SIZE(ssp2_pins[3]), - .modemuxs = ssp2_61_64_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), - }, { - .name = "ssp2_90_93_grp", - .pins = ssp2_pins[4], - .npins = ARRAY_SIZE(ssp2_pins[4]), - .modemuxs = ssp2_90_93_modemux, - .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), - }, -}; - -static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", - "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; -static struct spear_function ssp2_function = { - .name = "ssp2", - .groups = ssp2_grps, - .ngroups = ARRAY_SIZE(ssp2_grps), -}; - -/* Pad multiplexing for cadence mii2 as mii device */ -static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, - 90, 91, 92, 93, 94, 95, 96, 97 }; -static struct spear_muxreg mii2_muxreg[] = { - { - .reg = IP_SEL_PAD_80_89_REG, - .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | - PMX_PL_88_89_MASK, - .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | - PMX_MII2_PL_88_89_VAL, - }, { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | - PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, - .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | - PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | - (MAC_MODE_MII << MAC1_MODE_SHIFT) | - MII_MDIO_81_VAL, - }, -}; - -static struct spear_modemux mii2_modemux[] = { - { - .modes = EXTENDED_MODE, - .muxregs = mii2_muxreg, - .nmuxregs = ARRAY_SIZE(mii2_muxreg), - }, -}; - -static struct spear_pingroup mii2_pingroup = { - .name = "mii2_grp", - .pins = mii2_pins, - .npins = ARRAY_SIZE(mii2_pins), - .modemuxs = mii2_modemux, - .nmodemuxs = ARRAY_SIZE(mii2_modemux), -}; - -static const char *const mii2_grps[] = { "mii2_grp" }; -static struct spear_function mii2_function = { - .name = "mii2", - .groups = mii2_grps, - .ngroups = ARRAY_SIZE(mii2_grps), -}; - -/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ -static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27 }; -static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; -static struct spear_muxreg mii0_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, -}; - -static struct spear_muxreg smii0_1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_10_11_MASK, - .val = PMX_SMII_PL_10_11_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_21_TO_27_MASK, - .val = PMX_SMII_PL_21_TO_27_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) - | (MAC_MODE_SMII << MAC1_MODE_SHIFT) - | MII_MDIO_10_11_VAL, - }, -}; - -static struct spear_muxreg rmii0_1_ext_muxreg[] = { - { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | - PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, - .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | - PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | - PMX_RMII_PL_19_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, - .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, - }, { - .reg = EXT_CTRL_REG, - .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | - (MAC_MODE_MASK << MAC1_MODE_SHIFT) | - MII_MDIO_MASK, - .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) - | (MAC_MODE_RMII << MAC1_MODE_SHIFT) - | MII_MDIO_10_11_VAL, - }, -}; - -static struct spear_modemux mii0_1_modemux[][2] = { - { - /* configure as smii */ - { - .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | - SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = mii0_1_muxreg, - .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = smii0_1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), - }, - }, { - /* configure as rmii */ - { - .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | - SMALL_PRINTERS_MODE | EXTENDED_MODE, - .muxregs = mii0_1_muxreg, - .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), - }, { - .modes = EXTENDED_MODE, - .muxregs = rmii0_1_ext_muxreg, - .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), - }, - }, -}; - -static struct spear_pingroup mii0_1_pingroup[] = { - { - .name = "smii0_1_grp", - .pins = smii0_1_pins, - .npins = ARRAY_SIZE(smii0_1_pins), - .modemuxs = mii0_1_modemux[0], - .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), - }, { - .name = "rmii0_1_grp", - .pins = rmii0_1_pins, - .npins = ARRAY_SIZE(rmii0_1_pins), - .modemuxs = mii0_1_modemux[1], - .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), - }, -}; - -static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; -static struct spear_function mii0_1_function = { - .name = "mii0_1", - .groups = mii0_1_grps, - .ngroups = ARRAY_SIZE(mii0_1_grps), -}; - -/* Pad multiplexing for i2c1 device */ -static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; -static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_SSP_CS_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_8_9_MASK, - .val = PMX_I2C1_PL_8_9_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C1_PORT_SEL_MASK, - .val = PMX_I2C1_PORT_8_9_VAL, - }, -}; - -static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, - .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C1_PORT_SEL_MASK, - .val = PMX_I2C1_PORT_98_99_VAL, - }, -}; - -static struct spear_modemux i2c1_modemux[][1] = { - { - /* Select signals on pins 8-9 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c1_ext_8_9_muxreg, - .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), - }, - }, { - /* Select signals on pins 98-99 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c1_ext_98_99_muxreg, - .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), - }, - }, -}; - -static struct spear_pingroup i2c1_pingroup[] = { - { - .name = "i2c1_8_9_grp", - .pins = i2c1_pins[0], - .npins = ARRAY_SIZE(i2c1_pins[0]), - .modemuxs = i2c1_modemux[0], - .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), - }, { - .name = "i2c1_98_99_grp", - .pins = i2c1_pins[1], - .npins = ARRAY_SIZE(i2c1_pins[1]), - .modemuxs = i2c1_modemux[1], - .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), - }, -}; - -static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; -static struct spear_function i2c1_function = { - .name = "i2c1", - .groups = i2c1_grps, - .ngroups = ARRAY_SIZE(i2c1_grps), -}; - -/* Pad multiplexing for i2c2 device */ -static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, - { 75, 76 }, { 96, 97 } }; -static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_FIRDA_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_0_1_MASK, - .val = PMX_I2C2_PL_0_1_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_0_1_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_UART0_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_0_9_REG, - .mask = PMX_PL_2_3_MASK, - .val = PMX_I2C2_PL_2_3_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_2_3_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { - { - .reg = PMX_CONFIG_REG, - .mask = PMX_MII_MASK, - .val = 0, - }, { - .reg = IP_SEL_PAD_10_19_REG, - .mask = PMX_PL_19_MASK, - .val = PMX_I2C2_PL_19_VAL, - }, { - .reg = IP_SEL_PAD_20_29_REG, - .mask = PMX_PL_20_MASK, - .val = PMX_I2C2_PL_20_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_19_20_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { - { - .reg = IP_SEL_PAD_70_79_REG, - .mask = PMX_PL_75_76_MASK, - .val = PMX_I2C2_PL_75_76_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_75_76_VAL, - }, -}; - -static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { - { - .reg = IP_SEL_PAD_90_99_REG, - .mask = PMX_PL_96_97_MASK, - .val = PMX_I2C2_PL_96_97_VAL, - }, { - .reg = IP_SEL_MIX_PAD_REG, - .mask = PMX_I2C2_PORT_SEL_MASK, - .val = PMX_I2C2_PORT_96_97_VAL, - }, -}; - -static struct spear_modemux i2c2_modemux[][1] = { - { - /* Select signals on pins 0_1 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_0_1_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), - }, - }, { - /* Select signals on pins 2_3 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), - }, - }, { - /* Select signals on pins 19_20 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_19_20_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), - }, - }, { - /* Select signals on pins 75_76 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_75_76_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), - }, - }, { - /* Select signals on pins 96_97 */ - { - .modes = EXTENDED_MODE, - .muxregs = i2c2_ext_96_97_muxreg, - .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), - }, - }, -}; - -static struct spear_pingroup i2c2_pingroup[] = { - { - .name = "i2c2_0_1_grp", - .pins = i2c2_pins[0], - .npins = ARRAY_SIZE(i2c2_pins[0]), - .modemuxs = i2c2_modemux[0], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), - }, { - .name = "i2c2_2_3_grp", - .pins = i2c2_pins[1], - .npins = ARRAY_SIZE(i2c2_pins[1]), - .modemuxs = i2c2_modemux[1], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), - }, { - .name = "i2c2_19_20_grp", - .pins = i2c2_pins[2], - .npins = ARRAY_SIZE(i2c2_pins[2]), - .modemuxs = i2c2_modemux[2], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), - }, { - .name = "i2c2_75_76_grp", - .pins = i2c2_pins[3], - .npins = ARRAY_SIZE(i2c2_pins[3]), - .modemuxs = i2c2_modemux[3], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), - }, { - .name = "i2c2_96_97_grp", - .pins = i2c2_pins[4], - .npins = ARRAY_SIZE(i2c2_pins[4]), - .modemuxs = i2c2_modemux[4], - .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), - }, -}; - -static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", - "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; -static struct spear_function i2c2_function = { - .name = "i2c2", - .groups = i2c2_grps, - .ngroups = ARRAY_SIZE(i2c2_grps), -}; - -/* pingroups */ -static struct spear_pingroup *spear320_pingroups[] = { - SPEAR3XX_COMMON_PINGROUPS, - &clcd_pingroup, - &emi_pingroup, - &fsmc_8bit_pingroup, - &fsmc_16bit_pingroup, - &spp_pingroup, - &sdhci_led_pingroup, - &sdhci_pingroup[0], - &sdhci_pingroup[1], - &i2s_pingroup, - &uart1_pingroup, - &uart1_modem_pingroup[0], - &uart1_modem_pingroup[1], - &uart1_modem_pingroup[2], - &uart1_modem_pingroup[3], - &uart2_pingroup, - &uart3_pingroup[0], - &uart3_pingroup[1], - &uart3_pingroup[2], - &uart3_pingroup[3], - &uart3_pingroup[4], - &uart3_pingroup[5], - &uart3_pingroup[6], - &uart4_pingroup[0], - &uart4_pingroup[1], - &uart4_pingroup[2], - &uart4_pingroup[3], - &uart4_pingroup[4], - &uart4_pingroup[5], - &uart5_pingroup[0], - &uart5_pingroup[1], - &uart5_pingroup[2], - &uart5_pingroup[3], - &uart6_pingroup[0], - &uart6_pingroup[1], - &rs485_pingroup, - &touchscreen_pingroup, - &can0_pingroup, - &can1_pingroup, - &pwm0_1_pingroup[0], - &pwm0_1_pingroup[1], - &pwm0_1_pingroup[2], - &pwm0_1_pingroup[3], - &pwm0_1_pingroup[4], - &pwm0_1_pingroup[5], - &pwm0_1_pingroup[6], - &pwm2_pingroup[0], - &pwm2_pingroup[1], - &pwm2_pingroup[2], - &pwm2_pingroup[3], - &pwm2_pingroup[4], - &pwm2_pingroup[5], - &pwm2_pingroup[6], - &pwm3_pingroup[0], - &pwm3_pingroup[1], - &pwm3_pingroup[2], - &pwm3_pingroup[3], - &pwm3_pingroup[4], - &pwm3_pingroup[5], - &ssp1_pingroup[0], - &ssp1_pingroup[1], - &ssp1_pingroup[2], - &ssp1_pingroup[3], - &ssp1_pingroup[4], - &ssp2_pingroup[0], - &ssp2_pingroup[1], - &ssp2_pingroup[2], - &ssp2_pingroup[3], - &ssp2_pingroup[4], - &mii2_pingroup, - &mii0_1_pingroup[0], - &mii0_1_pingroup[1], - &i2c1_pingroup[0], - &i2c1_pingroup[1], - &i2c2_pingroup[0], - &i2c2_pingroup[1], - &i2c2_pingroup[2], - &i2c2_pingroup[3], - &i2c2_pingroup[4], -}; - -/* functions */ -static struct spear_function *spear320_functions[] = { - SPEAR3XX_COMMON_FUNCTIONS, - &clcd_function, - &emi_function, - &fsmc_function, - &spp_function, - &sdhci_function, - &i2s_function, - &uart1_function, - &uart1_modem_function, - &uart2_function, - &uart3_function, - &uart4_function, - &uart5_function, - &uart6_function, - &rs485_function, - &touchscreen_function, - &can0_function, - &can1_function, - &pwm0_1_function, - &pwm2_function, - &pwm3_function, - &ssp1_function, - &ssp2_function, - &mii2_function, - &mii0_1_function, - &i2c1_function, - &i2c2_function, -}; - -static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = { - { - .compatible = "st,spear320-pinmux", - }, - {}, -}; - -static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) -{ - int ret; - - spear3xx_machdata.groups = spear320_pingroups; - spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); - spear3xx_machdata.functions = spear320_functions; - spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); - - spear3xx_machdata.modes_supported = true; - spear3xx_machdata.pmx_modes = spear320_pmx_modes; - spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); - - pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); - - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; -} - -static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) -{ - return spear_pinctrl_remove(pdev); -} - -static struct platform_driver spear320_pinctrl_driver = { - .driver = { - .name = DRIVER_NAME, - .owner = THIS_MODULE, - .of_match_table = spear320_pinctrl_of_match, - }, - .probe = spear320_pinctrl_probe, - .remove = __devexit_p(spear320_pinctrl_remove), -}; - -static int __init spear320_pinctrl_init(void) -{ - return platform_driver_register(&spear320_pinctrl_driver); -} -arch_initcall(spear320_pinctrl_init); - -static void __exit spear320_pinctrl_exit(void) -{ - platform_driver_unregister(&spear320_pinctrl_driver); -} -module_exit(spear320_pinctrl_exit); - -MODULE_AUTHOR("Viresh Kumar "); -MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c b/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c deleted file mode 100644 index 832049a8b1c9..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Driver for the ST Microelectronics SPEAr3xx pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - -#include "pinctrl-spear3xx.h" - -/* pins */ -static const struct pinctrl_pin_desc spear3xx_pins[] = { - PINCTRL_PIN(0, "PLGPIO0"), - PINCTRL_PIN(1, "PLGPIO1"), - PINCTRL_PIN(2, "PLGPIO2"), - PINCTRL_PIN(3, "PLGPIO3"), - PINCTRL_PIN(4, "PLGPIO4"), - PINCTRL_PIN(5, "PLGPIO5"), - PINCTRL_PIN(6, "PLGPIO6"), - PINCTRL_PIN(7, "PLGPIO7"), - PINCTRL_PIN(8, "PLGPIO8"), - PINCTRL_PIN(9, "PLGPIO9"), - PINCTRL_PIN(10, "PLGPIO10"), - PINCTRL_PIN(11, "PLGPIO11"), - PINCTRL_PIN(12, "PLGPIO12"), - PINCTRL_PIN(13, "PLGPIO13"), - PINCTRL_PIN(14, "PLGPIO14"), - PINCTRL_PIN(15, "PLGPIO15"), - PINCTRL_PIN(16, "PLGPIO16"), - PINCTRL_PIN(17, "PLGPIO17"), - PINCTRL_PIN(18, "PLGPIO18"), - PINCTRL_PIN(19, "PLGPIO19"), - PINCTRL_PIN(20, "PLGPIO20"), - PINCTRL_PIN(21, "PLGPIO21"), - PINCTRL_PIN(22, "PLGPIO22"), - PINCTRL_PIN(23, "PLGPIO23"), - PINCTRL_PIN(24, "PLGPIO24"), - PINCTRL_PIN(25, "PLGPIO25"), - PINCTRL_PIN(26, "PLGPIO26"), - PINCTRL_PIN(27, "PLGPIO27"), - PINCTRL_PIN(28, "PLGPIO28"), - PINCTRL_PIN(29, "PLGPIO29"), - PINCTRL_PIN(30, "PLGPIO30"), - PINCTRL_PIN(31, "PLGPIO31"), - PINCTRL_PIN(32, "PLGPIO32"), - PINCTRL_PIN(33, "PLGPIO33"), - PINCTRL_PIN(34, "PLGPIO34"), - PINCTRL_PIN(35, "PLGPIO35"), - PINCTRL_PIN(36, "PLGPIO36"), - PINCTRL_PIN(37, "PLGPIO37"), - PINCTRL_PIN(38, "PLGPIO38"), - PINCTRL_PIN(39, "PLGPIO39"), - PINCTRL_PIN(40, "PLGPIO40"), - PINCTRL_PIN(41, "PLGPIO41"), - PINCTRL_PIN(42, "PLGPIO42"), - PINCTRL_PIN(43, "PLGPIO43"), - PINCTRL_PIN(44, "PLGPIO44"), - PINCTRL_PIN(45, "PLGPIO45"), - PINCTRL_PIN(46, "PLGPIO46"), - PINCTRL_PIN(47, "PLGPIO47"), - PINCTRL_PIN(48, "PLGPIO48"), - PINCTRL_PIN(49, "PLGPIO49"), - PINCTRL_PIN(50, "PLGPIO50"), - PINCTRL_PIN(51, "PLGPIO51"), - PINCTRL_PIN(52, "PLGPIO52"), - PINCTRL_PIN(53, "PLGPIO53"), - PINCTRL_PIN(54, "PLGPIO54"), - PINCTRL_PIN(55, "PLGPIO55"), - PINCTRL_PIN(56, "PLGPIO56"), - PINCTRL_PIN(57, "PLGPIO57"), - PINCTRL_PIN(58, "PLGPIO58"), - PINCTRL_PIN(59, "PLGPIO59"), - PINCTRL_PIN(60, "PLGPIO60"), - PINCTRL_PIN(61, "PLGPIO61"), - PINCTRL_PIN(62, "PLGPIO62"), - PINCTRL_PIN(63, "PLGPIO63"), - PINCTRL_PIN(64, "PLGPIO64"), - PINCTRL_PIN(65, "PLGPIO65"), - PINCTRL_PIN(66, "PLGPIO66"), - PINCTRL_PIN(67, "PLGPIO67"), - PINCTRL_PIN(68, "PLGPIO68"), - PINCTRL_PIN(69, "PLGPIO69"), - PINCTRL_PIN(70, "PLGPIO70"), - PINCTRL_PIN(71, "PLGPIO71"), - PINCTRL_PIN(72, "PLGPIO72"), - PINCTRL_PIN(73, "PLGPIO73"), - PINCTRL_PIN(74, "PLGPIO74"), - PINCTRL_PIN(75, "PLGPIO75"), - PINCTRL_PIN(76, "PLGPIO76"), - PINCTRL_PIN(77, "PLGPIO77"), - PINCTRL_PIN(78, "PLGPIO78"), - PINCTRL_PIN(79, "PLGPIO79"), - PINCTRL_PIN(80, "PLGPIO80"), - PINCTRL_PIN(81, "PLGPIO81"), - PINCTRL_PIN(82, "PLGPIO82"), - PINCTRL_PIN(83, "PLGPIO83"), - PINCTRL_PIN(84, "PLGPIO84"), - PINCTRL_PIN(85, "PLGPIO85"), - PINCTRL_PIN(86, "PLGPIO86"), - PINCTRL_PIN(87, "PLGPIO87"), - PINCTRL_PIN(88, "PLGPIO88"), - PINCTRL_PIN(89, "PLGPIO89"), - PINCTRL_PIN(90, "PLGPIO90"), - PINCTRL_PIN(91, "PLGPIO91"), - PINCTRL_PIN(92, "PLGPIO92"), - PINCTRL_PIN(93, "PLGPIO93"), - PINCTRL_PIN(94, "PLGPIO94"), - PINCTRL_PIN(95, "PLGPIO95"), - PINCTRL_PIN(96, "PLGPIO96"), - PINCTRL_PIN(97, "PLGPIO97"), - PINCTRL_PIN(98, "PLGPIO98"), - PINCTRL_PIN(99, "PLGPIO99"), - PINCTRL_PIN(100, "PLGPIO100"), - PINCTRL_PIN(101, "PLGPIO101"), -}; - -/* firda_pins */ -static const unsigned firda_pins[] = { 0, 1 }; -static struct spear_muxreg firda_muxreg[] = { - { - .reg = -1, - .mask = PMX_FIRDA_MASK, - .val = PMX_FIRDA_MASK, - }, -}; - -static struct spear_modemux firda_modemux[] = { - { - .modes = ~0, - .muxregs = firda_muxreg, - .nmuxregs = ARRAY_SIZE(firda_muxreg), - }, -}; - -struct spear_pingroup spear3xx_firda_pingroup = { - .name = "firda_grp", - .pins = firda_pins, - .npins = ARRAY_SIZE(firda_pins), - .modemuxs = firda_modemux, - .nmodemuxs = ARRAY_SIZE(firda_modemux), -}; - -static const char *const firda_grps[] = { "firda_grp" }; -struct spear_function spear3xx_firda_function = { - .name = "firda", - .groups = firda_grps, - .ngroups = ARRAY_SIZE(firda_grps), -}; - -/* i2c_pins */ -static const unsigned i2c_pins[] = { 4, 5 }; -static struct spear_muxreg i2c_muxreg[] = { - { - .reg = -1, - .mask = PMX_I2C_MASK, - .val = PMX_I2C_MASK, - }, -}; - -static struct spear_modemux i2c_modemux[] = { - { - .modes = ~0, - .muxregs = i2c_muxreg, - .nmuxregs = ARRAY_SIZE(i2c_muxreg), - }, -}; - -struct spear_pingroup spear3xx_i2c_pingroup = { - .name = "i2c0_grp", - .pins = i2c_pins, - .npins = ARRAY_SIZE(i2c_pins), - .modemuxs = i2c_modemux, - .nmodemuxs = ARRAY_SIZE(i2c_modemux), -}; - -static const char *const i2c_grps[] = { "i2c0_grp" }; -struct spear_function spear3xx_i2c_function = { - .name = "i2c0", - .groups = i2c_grps, - .ngroups = ARRAY_SIZE(i2c_grps), -}; - -/* ssp_cs_pins */ -static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; -static struct spear_muxreg ssp_cs_muxreg[] = { - { - .reg = -1, - .mask = PMX_SSP_CS_MASK, - .val = PMX_SSP_CS_MASK, - }, -}; - -static struct spear_modemux ssp_cs_modemux[] = { - { - .modes = ~0, - .muxregs = ssp_cs_muxreg, - .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), - }, -}; - -struct spear_pingroup spear3xx_ssp_cs_pingroup = { - .name = "ssp_cs_grp", - .pins = ssp_cs_pins, - .npins = ARRAY_SIZE(ssp_cs_pins), - .modemuxs = ssp_cs_modemux, - .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), -}; - -static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; -struct spear_function spear3xx_ssp_cs_function = { - .name = "ssp_cs", - .groups = ssp_cs_grps, - .ngroups = ARRAY_SIZE(ssp_cs_grps), -}; - -/* ssp_pins */ -static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; -static struct spear_muxreg ssp_muxreg[] = { - { - .reg = -1, - .mask = PMX_SSP_MASK, - .val = PMX_SSP_MASK, - }, -}; - -static struct spear_modemux ssp_modemux[] = { - { - .modes = ~0, - .muxregs = ssp_muxreg, - .nmuxregs = ARRAY_SIZE(ssp_muxreg), - }, -}; - -struct spear_pingroup spear3xx_ssp_pingroup = { - .name = "ssp0_grp", - .pins = ssp_pins, - .npins = ARRAY_SIZE(ssp_pins), - .modemuxs = ssp_modemux, - .nmodemuxs = ARRAY_SIZE(ssp_modemux), -}; - -static const char *const ssp_grps[] = { "ssp0_grp" }; -struct spear_function spear3xx_ssp_function = { - .name = "ssp0", - .groups = ssp_grps, - .ngroups = ARRAY_SIZE(ssp_grps), -}; - -/* mii_pins */ -static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27 }; -static struct spear_muxreg mii_muxreg[] = { - { - .reg = -1, - .mask = PMX_MII_MASK, - .val = PMX_MII_MASK, - }, -}; - -static struct spear_modemux mii_modemux[] = { - { - .modes = ~0, - .muxregs = mii_muxreg, - .nmuxregs = ARRAY_SIZE(mii_muxreg), - }, -}; - -struct spear_pingroup spear3xx_mii_pingroup = { - .name = "mii0_grp", - .pins = mii_pins, - .npins = ARRAY_SIZE(mii_pins), - .modemuxs = mii_modemux, - .nmodemuxs = ARRAY_SIZE(mii_modemux), -}; - -static const char *const mii_grps[] = { "mii0_grp" }; -struct spear_function spear3xx_mii_function = { - .name = "mii0", - .groups = mii_grps, - .ngroups = ARRAY_SIZE(mii_grps), -}; - -/* gpio0_pin0_pins */ -static const unsigned gpio0_pin0_pins[] = { 28 }; -static struct spear_muxreg gpio0_pin0_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN0_MASK, - .val = PMX_GPIO_PIN0_MASK, - }, -}; - -static struct spear_modemux gpio0_pin0_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin0_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { - .name = "gpio0_pin0_grp", - .pins = gpio0_pin0_pins, - .npins = ARRAY_SIZE(gpio0_pin0_pins), - .modemuxs = gpio0_pin0_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), -}; - -/* gpio0_pin1_pins */ -static const unsigned gpio0_pin1_pins[] = { 29 }; -static struct spear_muxreg gpio0_pin1_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN1_MASK, - .val = PMX_GPIO_PIN1_MASK, - }, -}; - -static struct spear_modemux gpio0_pin1_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin1_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { - .name = "gpio0_pin1_grp", - .pins = gpio0_pin1_pins, - .npins = ARRAY_SIZE(gpio0_pin1_pins), - .modemuxs = gpio0_pin1_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), -}; - -/* gpio0_pin2_pins */ -static const unsigned gpio0_pin2_pins[] = { 30 }; -static struct spear_muxreg gpio0_pin2_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN2_MASK, - .val = PMX_GPIO_PIN2_MASK, - }, -}; - -static struct spear_modemux gpio0_pin2_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin2_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { - .name = "gpio0_pin2_grp", - .pins = gpio0_pin2_pins, - .npins = ARRAY_SIZE(gpio0_pin2_pins), - .modemuxs = gpio0_pin2_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), -}; - -/* gpio0_pin3_pins */ -static const unsigned gpio0_pin3_pins[] = { 31 }; -static struct spear_muxreg gpio0_pin3_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN3_MASK, - .val = PMX_GPIO_PIN3_MASK, - }, -}; - -static struct spear_modemux gpio0_pin3_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin3_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { - .name = "gpio0_pin3_grp", - .pins = gpio0_pin3_pins, - .npins = ARRAY_SIZE(gpio0_pin3_pins), - .modemuxs = gpio0_pin3_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), -}; - -/* gpio0_pin4_pins */ -static const unsigned gpio0_pin4_pins[] = { 32 }; -static struct spear_muxreg gpio0_pin4_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN4_MASK, - .val = PMX_GPIO_PIN4_MASK, - }, -}; - -static struct spear_modemux gpio0_pin4_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin4_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { - .name = "gpio0_pin4_grp", - .pins = gpio0_pin4_pins, - .npins = ARRAY_SIZE(gpio0_pin4_pins), - .modemuxs = gpio0_pin4_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), -}; - -/* gpio0_pin5_pins */ -static const unsigned gpio0_pin5_pins[] = { 33 }; -static struct spear_muxreg gpio0_pin5_muxreg[] = { - { - .reg = -1, - .mask = PMX_GPIO_PIN5_MASK, - .val = PMX_GPIO_PIN5_MASK, - }, -}; - -static struct spear_modemux gpio0_pin5_modemux[] = { - { - .modes = ~0, - .muxregs = gpio0_pin5_muxreg, - .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), - }, -}; - -struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { - .name = "gpio0_pin5_grp", - .pins = gpio0_pin5_pins, - .npins = ARRAY_SIZE(gpio0_pin5_pins), - .modemuxs = gpio0_pin5_modemux, - .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), -}; - -static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", - "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", -}; -struct spear_function spear3xx_gpio0_function = { - .name = "gpio0", - .groups = gpio0_grps, - .ngroups = ARRAY_SIZE(gpio0_grps), -}; - -/* uart0_ext_pins */ -static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; -static struct spear_muxreg uart0_ext_muxreg[] = { - { - .reg = -1, - .mask = PMX_UART0_MODEM_MASK, - .val = PMX_UART0_MODEM_MASK, - }, -}; - -static struct spear_modemux uart0_ext_modemux[] = { - { - .modes = ~0, - .muxregs = uart0_ext_muxreg, - .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), - }, -}; - -struct spear_pingroup spear3xx_uart0_ext_pingroup = { - .name = "uart0_ext_grp", - .pins = uart0_ext_pins, - .npins = ARRAY_SIZE(uart0_ext_pins), - .modemuxs = uart0_ext_modemux, - .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), -}; - -static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; -struct spear_function spear3xx_uart0_ext_function = { - .name = "uart0_ext", - .groups = uart0_ext_grps, - .ngroups = ARRAY_SIZE(uart0_ext_grps), -}; - -/* uart0_pins */ -static const unsigned uart0_pins[] = { 2, 3 }; -static struct spear_muxreg uart0_muxreg[] = { - { - .reg = -1, - .mask = PMX_UART0_MASK, - .val = PMX_UART0_MASK, - }, -}; - -static struct spear_modemux uart0_modemux[] = { - { - .modes = ~0, - .muxregs = uart0_muxreg, - .nmuxregs = ARRAY_SIZE(uart0_muxreg), - }, -}; - -struct spear_pingroup spear3xx_uart0_pingroup = { - .name = "uart0_grp", - .pins = uart0_pins, - .npins = ARRAY_SIZE(uart0_pins), - .modemuxs = uart0_modemux, - .nmodemuxs = ARRAY_SIZE(uart0_modemux), -}; - -static const char *const uart0_grps[] = { "uart0_grp" }; -struct spear_function spear3xx_uart0_function = { - .name = "uart0", - .groups = uart0_grps, - .ngroups = ARRAY_SIZE(uart0_grps), -}; - -/* timer_0_1_pins */ -static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; -static struct spear_muxreg timer_0_1_muxreg[] = { - { - .reg = -1, - .mask = PMX_TIMER_0_1_MASK, - .val = PMX_TIMER_0_1_MASK, - }, -}; - -static struct spear_modemux timer_0_1_modemux[] = { - { - .modes = ~0, - .muxregs = timer_0_1_muxreg, - .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), - }, -}; - -struct spear_pingroup spear3xx_timer_0_1_pingroup = { - .name = "timer_0_1_grp", - .pins = timer_0_1_pins, - .npins = ARRAY_SIZE(timer_0_1_pins), - .modemuxs = timer_0_1_modemux, - .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), -}; - -static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; -struct spear_function spear3xx_timer_0_1_function = { - .name = "timer_0_1", - .groups = timer_0_1_grps, - .ngroups = ARRAY_SIZE(timer_0_1_grps), -}; - -/* timer_2_3_pins */ -static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; -static struct spear_muxreg timer_2_3_muxreg[] = { - { - .reg = -1, - .mask = PMX_TIMER_2_3_MASK, - .val = PMX_TIMER_2_3_MASK, - }, -}; - -static struct spear_modemux timer_2_3_modemux[] = { - { - .modes = ~0, - .muxregs = timer_2_3_muxreg, - .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), - }, -}; - -struct spear_pingroup spear3xx_timer_2_3_pingroup = { - .name = "timer_2_3_grp", - .pins = timer_2_3_pins, - .npins = ARRAY_SIZE(timer_2_3_pins), - .modemuxs = timer_2_3_modemux, - .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), -}; - -static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; -struct spear_function spear3xx_timer_2_3_function = { - .name = "timer_2_3", - .groups = timer_2_3_grps, - .ngroups = ARRAY_SIZE(timer_2_3_grps), -}; - -struct spear_pinctrl_machdata spear3xx_machdata = { - .pins = spear3xx_pins, - .npins = ARRAY_SIZE(spear3xx_pins), -}; diff --git a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h b/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h deleted file mode 100644 index 5d5fdd8df7b8..000000000000 --- a/trunk/drivers/pinctrl/spear/pinctrl-spear3xx.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Header file for the ST Microelectronics SPEAr3xx pinmux - * - * Copyright (C) 2012 ST Microelectronics - * Viresh Kumar - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __PINMUX_SPEAR3XX_H__ -#define __PINMUX_SPEAR3XX_H__ - -#include "pinctrl-spear.h" - -/* pad mux declarations */ -#define PMX_FIRDA_MASK (1 << 14) -#define PMX_I2C_MASK (1 << 13) -#define PMX_SSP_CS_MASK (1 << 12) -#define PMX_SSP_MASK (1 << 11) -#define PMX_MII_MASK (1 << 10) -#define PMX_GPIO_PIN0_MASK (1 << 9) -#define PMX_GPIO_PIN1_MASK (1 << 8) -#define PMX_GPIO_PIN2_MASK (1 << 7) -#define PMX_GPIO_PIN3_MASK (1 << 6) -#define PMX_GPIO_PIN4_MASK (1 << 5) -#define PMX_GPIO_PIN5_MASK (1 << 4) -#define PMX_UART0_MODEM_MASK (1 << 3) -#define PMX_UART0_MASK (1 << 2) -#define PMX_TIMER_2_3_MASK (1 << 1) -#define PMX_TIMER_0_1_MASK (1 << 0) - -extern struct spear_pingroup spear3xx_firda_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup; -extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup; -extern struct spear_pingroup spear3xx_i2c_pingroup; -extern struct spear_pingroup spear3xx_mii_pingroup; -extern struct spear_pingroup spear3xx_ssp_cs_pingroup; -extern struct spear_pingroup spear3xx_ssp_pingroup; -extern struct spear_pingroup spear3xx_timer_0_1_pingroup; -extern struct spear_pingroup spear3xx_timer_2_3_pingroup; -extern struct spear_pingroup spear3xx_uart0_ext_pingroup; -extern struct spear_pingroup spear3xx_uart0_pingroup; - -#define SPEAR3XX_COMMON_PINGROUPS \ - &spear3xx_firda_pingroup, \ - &spear3xx_gpio0_pin0_pingroup, \ - &spear3xx_gpio0_pin1_pingroup, \ - &spear3xx_gpio0_pin2_pingroup, \ - &spear3xx_gpio0_pin3_pingroup, \ - &spear3xx_gpio0_pin4_pingroup, \ - &spear3xx_gpio0_pin5_pingroup, \ - &spear3xx_i2c_pingroup, \ - &spear3xx_mii_pingroup, \ - &spear3xx_ssp_cs_pingroup, \ - &spear3xx_ssp_pingroup, \ - &spear3xx_timer_0_1_pingroup, \ - &spear3xx_timer_2_3_pingroup, \ - &spear3xx_uart0_ext_pingroup, \ - &spear3xx_uart0_pingroup - -extern struct spear_function spear3xx_firda_function; -extern struct spear_function spear3xx_gpio0_function; -extern struct spear_function spear3xx_i2c_function; -extern struct spear_function spear3xx_mii_function; -extern struct spear_function spear3xx_ssp_cs_function; -extern struct spear_function spear3xx_ssp_function; -extern struct spear_function spear3xx_timer_0_1_function; -extern struct spear_function spear3xx_timer_2_3_function; -extern struct spear_function spear3xx_uart0_ext_function; -extern struct spear_function spear3xx_uart0_function; - -#define SPEAR3XX_COMMON_FUNCTIONS \ - &spear3xx_firda_function, \ - &spear3xx_gpio0_function, \ - &spear3xx_i2c_function, \ - &spear3xx_mii_function, \ - &spear3xx_ssp_cs_function, \ - &spear3xx_ssp_function, \ - &spear3xx_timer_0_1_function, \ - &spear3xx_timer_2_3_function, \ - &spear3xx_uart0_ext_function, \ - &spear3xx_uart0_function - -extern struct spear_pinctrl_machdata spear3xx_machdata; - -#endif /* __PINMUX_SPEAR3XX_H__ */ diff --git a/trunk/drivers/s390/block/dasd_eckd.c b/trunk/drivers/s390/block/dasd_eckd.c index bc2e8a7c265b..c21871a4e73d 100644 --- a/trunk/drivers/s390/block/dasd_eckd.c +++ b/trunk/drivers/s390/block/dasd_eckd.c @@ -2844,7 +2844,6 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( sector_t recid, trkid; unsigned int offs; unsigned int count, count_to_trk_end; - int ret; basedev = block->base; if (rq_data_dir(req) == READ) { @@ -2885,8 +2884,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( itcw = itcw_init(cqr->data, itcw_size, itcw_op, 0, ctidaw, 0); if (IS_ERR(itcw)) { - ret = -EINVAL; - goto out_error; + dasd_sfree_request(cqr, startdev); + return ERR_PTR(-EINVAL); } cqr->cpaddr = itcw_get_tcw(itcw); if (prepare_itcw(itcw, first_trk, last_trk, @@ -2898,8 +2897,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( /* Clock not in sync and XRC is enabled. * Try again later. */ - ret = -EAGAIN; - goto out_error; + dasd_sfree_request(cqr, startdev); + return ERR_PTR(-EAGAIN); } len_to_track_end = 0; /* @@ -2938,10 +2937,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( tidaw_flags = 0; last_tidaw = itcw_add_tidaw(itcw, tidaw_flags, dst, part_len); - if (IS_ERR(last_tidaw)) { - ret = -EINVAL; - goto out_error; - } + if (IS_ERR(last_tidaw)) + return ERR_PTR(-EINVAL); dst += part_len; } } @@ -2950,10 +2947,8 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( dst = page_address(bv->bv_page) + bv->bv_offset; last_tidaw = itcw_add_tidaw(itcw, 0x00, dst, bv->bv_len); - if (IS_ERR(last_tidaw)) { - ret = -EINVAL; - goto out_error; - } + if (IS_ERR(last_tidaw)) + return ERR_PTR(-EINVAL); } } last_tidaw->flags |= TIDAW_FLAGS_LAST; @@ -2973,9 +2968,6 @@ static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track( cqr->buildclk = get_clock(); cqr->status = DASD_CQR_FILLED; return cqr; -out_error: - dasd_sfree_request(cqr, startdev); - return ERR_PTR(ret); } static struct dasd_ccw_req *dasd_eckd_build_cp(struct dasd_device *startdev, diff --git a/trunk/drivers/s390/char/vmur.c b/trunk/drivers/s390/char/vmur.c index 73bef0bd394c..85f4a9a5d12e 100644 --- a/trunk/drivers/s390/char/vmur.c +++ b/trunk/drivers/s390/char/vmur.c @@ -903,7 +903,7 @@ static int ur_set_online(struct ccw_device *cdev) goto fail_urdev_put; } - urd->char_device->ops = &ur_fops; + cdev_init(urd->char_device, &ur_fops); urd->char_device->dev = MKDEV(major, minor); urd->char_device->owner = ur_fops.owner; diff --git a/trunk/drivers/tty/amiserial.c b/trunk/drivers/tty/amiserial.c index 6cc4358f68c1..24145c30c9b0 100644 --- a/trunk/drivers/tty/amiserial.c +++ b/trunk/drivers/tty/amiserial.c @@ -1073,10 +1073,8 @@ static int set_serial_info(struct tty_struct *tty, struct serial_state *state, (new_serial.close_delay != port->close_delay) || (new_serial.xmit_fifo_size != state->xmit_fifo_size) || ((new_serial.flags & ~ASYNC_USR_MASK) != - (port->flags & ~ASYNC_USR_MASK))) { - tty_unlock(); + (port->flags & ~ASYNC_USR_MASK))) return -EPERM; - } port->flags = ((port->flags & ~ASYNC_USR_MASK) | (new_serial.flags & ASYNC_USR_MASK)); state->custom_divisor = new_serial.custom_divisor; diff --git a/trunk/drivers/tty/serial/clps711x.c b/trunk/drivers/tty/serial/clps711x.c index 836fe2731234..e6c3dbd781d6 100644 --- a/trunk/drivers/tty/serial/clps711x.c +++ b/trunk/drivers/tty/serial/clps711x.c @@ -154,9 +154,10 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id) port->x_char = 0; return IRQ_HANDLED; } - - if (uart_circ_empty(xmit) || uart_tx_stopped(port)) - goto disable_tx_irq; + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { + clps711xuart_stop_tx(port); + return IRQ_HANDLED; + } count = port->fifosize >> 1; do { @@ -170,11 +171,8 @@ static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id) if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); - if (uart_circ_empty(xmit)) { - disable_tx_irq: - disable_irq_nosync(TX_IRQ(port)); - tx_enabled(port) = 0; - } + if (uart_circ_empty(xmit)) + clps711xuart_stop_tx(port); return IRQ_HANDLED; } diff --git a/trunk/drivers/tty/serial/pch_uart.c b/trunk/drivers/tty/serial/pch_uart.c index c2816f494807..bbbec4a74cfb 100644 --- a/trunk/drivers/tty/serial/pch_uart.c +++ b/trunk/drivers/tty/serial/pch_uart.c @@ -1447,11 +1447,9 @@ static int pch_uart_verify_port(struct uart_port *port, __func__); return -EOPNOTSUPP; #endif + priv->use_dma = 1; priv->use_dma_flag = 1; dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); - if (!priv->use_dma) - pch_request_dma(port); - priv->use_dma = 1; } return 0; diff --git a/trunk/drivers/usb/core/hub.c b/trunk/drivers/usb/core/hub.c index ec6c97dadbe4..a2aa9d652c67 100644 --- a/trunk/drivers/usb/core/hub.c +++ b/trunk/drivers/usb/core/hub.c @@ -1667,6 +1667,7 @@ void usb_disconnect(struct usb_device **pdev) { struct usb_device *udev = *pdev; int i; + struct usb_hcd *hcd = bus_to_hcd(udev->bus); /* mark the device as inactive, so any further urb submissions for * this device (and any of its children) will fail immediately. @@ -1689,7 +1690,9 @@ void usb_disconnect(struct usb_device **pdev) * so that the hardware is now fully quiesced. */ dev_dbg (&udev->dev, "unregistering device\n"); + mutex_lock(hcd->bandwidth_mutex); usb_disable_device(udev, 0); + mutex_unlock(hcd->bandwidth_mutex); usb_hcd_synchronize_unlinks(udev); usb_remove_ep_devs(&udev->ep0); diff --git a/trunk/drivers/usb/core/message.c b/trunk/drivers/usb/core/message.c index ca717da3be95..aed3e07942d4 100644 --- a/trunk/drivers/usb/core/message.c +++ b/trunk/drivers/usb/core/message.c @@ -1136,6 +1136,8 @@ void usb_disable_interface(struct usb_device *dev, struct usb_interface *intf, * Deallocates hcd/hardware state for the endpoints (nuking all or most * pending urbs) and usbcore state for the interfaces, so that usbcore * must usb_set_configuration() before any interfaces could be used. + * + * Must be called with hcd->bandwidth_mutex held. */ void usb_disable_device(struct usb_device *dev, int skip_ep0) { @@ -1188,9 +1190,7 @@ void usb_disable_device(struct usb_device *dev, int skip_ep0) usb_disable_endpoint(dev, i + USB_DIR_IN, false); } /* Remove endpoints from the host controller internal state */ - mutex_lock(hcd->bandwidth_mutex); usb_hcd_alloc_bandwidth(dev, NULL, NULL, NULL); - mutex_unlock(hcd->bandwidth_mutex); /* Second pass: remove endpoint pointers */ } for (i = skip_ep0; i < 16; ++i) { @@ -1750,6 +1750,7 @@ int usb_set_configuration(struct usb_device *dev, int configuration) /* if it's already configured, clear out old state first. * getting rid of old interfaces means unbinding their drivers. */ + mutex_lock(hcd->bandwidth_mutex); if (dev->state != USB_STATE_ADDRESS) usb_disable_device(dev, 1); /* Skip ep0 */ @@ -1762,7 +1763,6 @@ int usb_set_configuration(struct usb_device *dev, int configuration) * host controller will not allow submissions to dropped endpoints. If * this call fails, the device state is unchanged. */ - mutex_lock(hcd->bandwidth_mutex); ret = usb_hcd_alloc_bandwidth(dev, cp, NULL, NULL); if (ret < 0) { mutex_unlock(hcd->bandwidth_mutex); diff --git a/trunk/drivers/usb/dwc3/core.c b/trunk/drivers/usb/dwc3/core.c index 99b58d84553a..7bd815a507e8 100644 --- a/trunk/drivers/usb/dwc3/core.c +++ b/trunk/drivers/usb/dwc3/core.c @@ -206,11 +206,11 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc) for (i = 0; i < dwc->num_event_buffers; i++) { evt = dwc->ev_buffs[i]; - if (evt) + if (evt) { dwc3_free_one_event_buffer(dwc, evt); + dwc->ev_buffs[i] = NULL; + } } - - kfree(dwc->ev_buffs); } /** diff --git a/trunk/drivers/usb/dwc3/ep0.c b/trunk/drivers/usb/dwc3/ep0.c index 3584a169886f..25910e251c04 100644 --- a/trunk/drivers/usb/dwc3/ep0.c +++ b/trunk/drivers/usb/dwc3/ep0.c @@ -353,9 +353,6 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, dwc->test_mode_nr = wIndex >> 8; dwc->test_mode = true; - break; - default: - return -EINVAL; } break; @@ -562,20 +559,15 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, length = trb->size & DWC3_TRB_SIZE_MASK; if (dwc->ep0_bounced) { - unsigned transfer_size = ur->length; - unsigned maxp = ep0->endpoint.maxpacket; - - transfer_size += (maxp - (transfer_size % maxp)); transferred = min_t(u32, ur->length, - transfer_size - length); + ep0->endpoint.maxpacket - length); memcpy(ur->buf, dwc->ep0_bounce, transferred); dwc->ep0_bounced = false; } else { transferred = ur->length - length; + ur->actual += transferred; } - ur->actual += transferred; - if ((epnum & 1) && ur->actual < ur->length) { /* for some reason we did not get everything out */ diff --git a/trunk/drivers/usb/gadget/at91_udc.c b/trunk/drivers/usb/gadget/at91_udc.c index 9d7bcd910074..0c935d7c65bd 100644 --- a/trunk/drivers/usb/gadget/at91_udc.c +++ b/trunk/drivers/usb/gadget/at91_udc.c @@ -1863,8 +1863,8 @@ static int __devinit at91udc_probe(struct platform_device *pdev) mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); } else { - if (request_irq(gpio_to_irq(udc->board.vbus_pin), - at91_vbus_irq, 0, driver_name, udc)) { + if (request_irq(udc->board.vbus_pin, at91_vbus_irq, + 0, driver_name, udc)) { DBG("request vbus irq %d failed\n", udc->board.vbus_pin); retval = -EBUSY; @@ -1886,7 +1886,7 @@ static int __devinit at91udc_probe(struct platform_device *pdev) return 0; fail4: if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled) - free_irq(gpio_to_irq(udc->board.vbus_pin), udc); + free_irq(udc->board.vbus_pin, udc); fail3: if (gpio_is_valid(udc->board.vbus_pin)) gpio_free(udc->board.vbus_pin); @@ -1924,7 +1924,7 @@ static int __exit at91udc_remove(struct platform_device *pdev) device_init_wakeup(&pdev->dev, 0); remove_debug_file(udc); if (gpio_is_valid(udc->board.vbus_pin)) { - free_irq(gpio_to_irq(udc->board.vbus_pin), udc); + free_irq(udc->board.vbus_pin, udc); gpio_free(udc->board.vbus_pin); } free_irq(udc->udp_irq, udc); diff --git a/trunk/drivers/usb/gadget/f_fs.c b/trunk/drivers/usb/gadget/f_fs.c index f52cb1ae45d9..1cbba70836bc 100644 --- a/trunk/drivers/usb/gadget/f_fs.c +++ b/trunk/drivers/usb/gadget/f_fs.c @@ -712,7 +712,7 @@ static long ffs_ep0_ioctl(struct file *file, unsigned code, unsigned long value) if (code == FUNCTIONFS_INTERFACE_REVMAP) { struct ffs_function *func = ffs->func; ret = func ? ffs_func_revmap_intf(func, value) : -ENODEV; - } else if (gadget && gadget->ops->ioctl) { + } else if (gadget->ops->ioctl) { ret = gadget->ops->ioctl(gadget, code, value); } else { ret = -ENOTTY; @@ -1382,7 +1382,6 @@ static void functionfs_unbind(struct ffs_data *ffs) ffs->ep0req = NULL; ffs->gadget = NULL; ffs_data_put(ffs); - clear_bit(FFS_FL_BOUND, &ffs->flags); } } diff --git a/trunk/drivers/usb/gadget/f_rndis.c b/trunk/drivers/usb/gadget/f_rndis.c index 52343654f5df..7b1cf18df5e3 100644 --- a/trunk/drivers/usb/gadget/f_rndis.c +++ b/trunk/drivers/usb/gadget/f_rndis.c @@ -500,7 +500,6 @@ rndis_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) if (buf) { memcpy(req->buf, buf, n); req->complete = rndis_response_complete; - req->context = rndis; rndis_free_response(rndis->config, buf); value = n; } diff --git a/trunk/drivers/usb/gadget/fsl_udc_core.c b/trunk/drivers/usb/gadget/fsl_udc_core.c index 55abfb6bd612..5f94e79cd6b9 100644 --- a/trunk/drivers/usb/gadget/fsl_udc_core.c +++ b/trunk/drivers/usb/gadget/fsl_udc_core.c @@ -730,7 +730,7 @@ static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req) : (1 << (ep_index(ep))); /* check if the pipe is empty */ - if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) { + if (!(list_empty(&ep->queue))) { /* Add td to the end */ struct fsl_req *lastreq; lastreq = list_entry(ep->queue.prev, struct fsl_req, queue); @@ -918,6 +918,10 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) return -ENOMEM; } + /* Update ep0 state */ + if ((ep_index(ep) == 0)) + udc->ep0_state = DATA_STATE_XMIT; + /* irq handler advances the queue */ if (req != NULL) list_add_tail(&req->queue, &ep->queue); @@ -1275,8 +1279,7 @@ static int ep0_prime_status(struct fsl_udc *udc, int direction) udc->ep0_dir = USB_DIR_OUT; ep = &udc->eps[0]; - if (udc->ep0_state != DATA_STATE_XMIT) - udc->ep0_state = WAIT_FOR_OUT_STATUS; + udc->ep0_state = WAIT_FOR_OUT_STATUS; req->ep = ep; req->req.length = 0; @@ -1381,9 +1384,6 @@ static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value, list_add_tail(&req->queue, &ep->queue); udc->ep0_state = DATA_STATE_XMIT; - if (ep0_prime_status(udc, EP_DIR_OUT)) - ep0stall(udc); - return; stall: ep0stall(udc); @@ -1492,14 +1492,6 @@ static void setup_received_irq(struct fsl_udc *udc, spin_lock(&udc->lock); udc->ep0_state = (setup->bRequestType & USB_DIR_IN) ? DATA_STATE_XMIT : DATA_STATE_RECV; - /* - * If the data stage is IN, send status prime immediately. - * See 2.0 Spec chapter 8.5.3.3 for detail. - */ - if (udc->ep0_state == DATA_STATE_XMIT) - if (ep0_prime_status(udc, EP_DIR_OUT)) - ep0stall(udc); - } else { /* No data phase, IN status from gadget */ udc->ep0_dir = USB_DIR_IN; @@ -1528,8 +1520,9 @@ static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0, switch (udc->ep0_state) { case DATA_STATE_XMIT: - /* already primed at setup_received_irq */ - udc->ep0_state = WAIT_FOR_OUT_STATUS; + /* receive status phase */ + if (ep0_prime_status(udc, EP_DIR_OUT)) + ep0stall(udc); break; case DATA_STATE_RECV: /* send status phase */ diff --git a/trunk/drivers/usb/gadget/g_ffs.c b/trunk/drivers/usb/gadget/g_ffs.c index a85eaf40b948..331cd6729d3c 100644 --- a/trunk/drivers/usb/gadget/g_ffs.c +++ b/trunk/drivers/usb/gadget/g_ffs.c @@ -161,7 +161,7 @@ static struct usb_composite_driver gfs_driver = { static struct ffs_data *gfs_ffs_data; static unsigned long gfs_registered; -static int __init gfs_init(void) +static int gfs_init(void) { ENTER(); @@ -169,7 +169,7 @@ static int __init gfs_init(void) } module_init(gfs_init); -static void __exit gfs_exit(void) +static void gfs_exit(void) { ENTER(); diff --git a/trunk/drivers/usb/gadget/s3c-hsotg.c b/trunk/drivers/usb/gadget/s3c-hsotg.c index 105b206cd844..69295ba9d99a 100644 --- a/trunk/drivers/usb/gadget/s3c-hsotg.c +++ b/trunk/drivers/usb/gadget/s3c-hsotg.c @@ -340,7 +340,7 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) /* currently we allocate TX FIFOs for all possible endpoints, * and assume that they are all the same size. */ - for (ep = 1; ep <= 15; ep++) { + for (ep = 0; ep <= 15; ep++) { val = addr; val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; addr += size; @@ -741,7 +741,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg, /* write size / packets */ writel(epsize, hsotg->regs + epsize_reg); - if (using_dma(hsotg) && !continuing) { + if (using_dma(hsotg)) { unsigned int dma_reg; /* write DMA address to control register, buffer already @@ -1696,12 +1696,10 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg, reg |= mpsval; writel(reg, regs + S3C_DIEPCTL(ep)); - if (ep) { - reg = readl(regs + S3C_DOEPCTL(ep)); - reg &= ~S3C_DxEPCTL_MPS_MASK; - reg |= mpsval; - writel(reg, regs + S3C_DOEPCTL(ep)); - } + reg = readl(regs + S3C_DOEPCTL(ep)); + reg &= ~S3C_DxEPCTL_MPS_MASK; + reg |= mpsval; + writel(reg, regs + S3C_DOEPCTL(ep)); return; @@ -1921,8 +1919,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, ints & S3C_DIEPMSK_TxFIFOEmpty) { dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", __func__, idx); - if (!using_dma(hsotg)) - s3c_hsotg_trytx(hsotg, hs_ep); + s3c_hsotg_trytx(hsotg, hs_ep); } } } diff --git a/trunk/drivers/usb/gadget/udc-core.c b/trunk/drivers/usb/gadget/udc-core.c index 2fa9865babed..56da49f31d6c 100644 --- a/trunk/drivers/usb/gadget/udc-core.c +++ b/trunk/drivers/usb/gadget/udc-core.c @@ -264,8 +264,8 @@ static void usb_gadget_remove_driver(struct usb_udc *udc) if (udc_is_newstyle(udc)) { udc->driver->disconnect(udc->gadget); udc->driver->unbind(udc->gadget); - usb_gadget_disconnect(udc->gadget); usb_gadget_udc_stop(udc->gadget, udc->driver); + usb_gadget_disconnect(udc->gadget); } else { usb_gadget_stop(udc->gadget, udc->driver); } @@ -411,12 +411,8 @@ static ssize_t usb_udc_softconn_store(struct device *dev, struct usb_udc *udc = container_of(dev, struct usb_udc, dev); if (sysfs_streq(buf, "connect")) { - if (udc_is_newstyle(udc)) - usb_gadget_udc_start(udc->gadget, udc->driver); usb_gadget_connect(udc->gadget); } else if (sysfs_streq(buf, "disconnect")) { - if (udc_is_newstyle(udc)) - usb_gadget_udc_stop(udc->gadget, udc->driver); usb_gadget_disconnect(udc->gadget); } else { dev_err(dev, "unsupported command '%s'\n", buf); diff --git a/trunk/drivers/usb/gadget/uvc_queue.c b/trunk/drivers/usb/gadget/uvc_queue.c index 0cdf89d32a15..d776adb2da67 100644 --- a/trunk/drivers/usb/gadget/uvc_queue.c +++ b/trunk/drivers/usb/gadget/uvc_queue.c @@ -543,11 +543,11 @@ static int uvc_queue_enable(struct uvc_video_queue *queue, int enable) return ret; } -/* called with queue->irqlock held.. */ static struct uvc_buffer * uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf) { struct uvc_buffer *nextbuf; + unsigned long flags; if ((queue->flags & UVC_QUEUE_DROP_INCOMPLETE) && buf->buf.length != buf->buf.bytesused) { @@ -556,12 +556,14 @@ uvc_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *buf) return buf; } + spin_lock_irqsave(&queue->irqlock, flags); list_del(&buf->queue); if (!list_empty(&queue->irqqueue)) nextbuf = list_first_entry(&queue->irqqueue, struct uvc_buffer, queue); else nextbuf = NULL; + spin_unlock_irqrestore(&queue->irqlock, flags); buf->buf.sequence = queue->sequence++; do_gettimeofday(&buf->buf.timestamp); diff --git a/trunk/drivers/usb/host/ehci-fsl.c b/trunk/drivers/usb/host/ehci-fsl.c index d0a84bd3f3eb..3e7345172e03 100644 --- a/trunk/drivers/usb/host/ehci-fsl.c +++ b/trunk/drivers/usb/host/ehci-fsl.c @@ -218,9 +218,6 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, u32 portsc; struct usb_hcd *hcd = ehci_to_hcd(ehci); void __iomem *non_ehci = hcd->regs; - struct fsl_usb2_platform_data *pdata; - - pdata = hcd->self.controller->platform_data; portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); @@ -237,9 +234,7 @@ static void ehci_fsl_setup_phy(struct ehci_hcd *ehci, /* fall through */ case FSL_USB2_PHY_UTMI: /* enable UTMI PHY */ - if (pdata->have_sysif_regs) - setbits32(non_ehci + FSL_SOC_USB_CTRL, - CTRL_UTMI_PHY_EN); + setbits32(non_ehci + FSL_SOC_USB_CTRL, CTRL_UTMI_PHY_EN); portsc |= PORT_PTS_UTMI; break; case FSL_USB2_PHY_NONE: diff --git a/trunk/drivers/usb/host/ehci-hcd.c b/trunk/drivers/usb/host/ehci-hcd.c index 4a3bc5b7a06f..806cc95317aa 100644 --- a/trunk/drivers/usb/host/ehci-hcd.c +++ b/trunk/drivers/usb/host/ehci-hcd.c @@ -858,13 +858,8 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) goto dead; } - /* - * We don't use STS_FLR, but some controllers don't like it to - * remain on, so mask it out along with the other status bits. - */ - masked_status = status & (INTR_MASK | STS_FLR); - /* Shared IRQ? */ + masked_status = status & INTR_MASK; if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { spin_unlock(&ehci->lock); return IRQ_NONE; @@ -915,7 +910,7 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) pcd_status = status; /* resume root hub? */ - if (ehci->rh_state == EHCI_RH_SUSPENDED) + if (!(cmd & CMD_RUN)) usb_hcd_resume_root_hub(hcd); /* get per-port change detect bits */ diff --git a/trunk/drivers/usb/host/ehci-omap.c b/trunk/drivers/usb/host/ehci-omap.c index 5c78f9e71466..bba9850f32f0 100644 --- a/trunk/drivers/usb/host/ehci-omap.c +++ b/trunk/drivers/usb/host/ehci-omap.c @@ -42,7 +42,6 @@ #include #include #include -#include /* EHCI Register Set */ #define EHCI_INSNREG04 (0xA0) @@ -192,19 +191,6 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) } } - if (pdata->phy_reset) { - if (gpio_is_valid(pdata->reset_gpio_port[0])) - gpio_request_one(pdata->reset_gpio_port[0], - GPIOF_OUT_INIT_LOW, "USB1 PHY reset"); - - if (gpio_is_valid(pdata->reset_gpio_port[1])) - gpio_request_one(pdata->reset_gpio_port[1], - GPIOF_OUT_INIT_LOW, "USB2 PHY reset"); - - /* Hold the PHY in RESET for enough time till DIR is high */ - udelay(10); - } - pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -251,19 +237,6 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) /* root ports should always stay powered */ ehci_port_power(omap_ehci, 1); - if (pdata->phy_reset) { - /* Hold the PHY in RESET for enough time till - * PHY is settled and ready - */ - udelay(10); - - if (gpio_is_valid(pdata->reset_gpio_port[0])) - gpio_set_value(pdata->reset_gpio_port[0], 1); - - if (gpio_is_valid(pdata->reset_gpio_port[1])) - gpio_set_value(pdata->reset_gpio_port[1], 1); - } - return 0; err_add_hcd: @@ -286,9 +259,8 @@ static int ehci_hcd_omap_probe(struct platform_device *pdev) */ static int ehci_hcd_omap_remove(struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct usb_hcd *hcd = dev_get_drvdata(dev); - struct ehci_hcd_omap_platform_data *pdata = dev->platform_data; + struct device *dev = &pdev->dev; + struct usb_hcd *hcd = dev_get_drvdata(dev); usb_remove_hcd(hcd); disable_put_regulator(dev->platform_data); @@ -297,13 +269,6 @@ static int ehci_hcd_omap_remove(struct platform_device *pdev) pm_runtime_put_sync(dev); pm_runtime_disable(dev); - if (pdata->phy_reset) { - if (gpio_is_valid(pdata->reset_gpio_port[0])) - gpio_free(pdata->reset_gpio_port[0]); - - if (gpio_is_valid(pdata->reset_gpio_port[1])) - gpio_free(pdata->reset_gpio_port[1]); - } return 0; } diff --git a/trunk/drivers/usb/host/ehci-tegra.c b/trunk/drivers/usb/host/ehci-tegra.c index 86183366647f..73544bd440bd 100644 --- a/trunk/drivers/usb/host/ehci-tegra.c +++ b/trunk/drivers/usb/host/ehci-tegra.c @@ -731,6 +731,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) err = -ENODEV; goto fail; } + set_irq_flags(irq, IRQF_VALID); #ifdef CONFIG_USB_OTG_UTILS if (pdata->operating_mode == TEGRA_USB_OTG) { diff --git a/trunk/drivers/usb/host/ohci-at91.c b/trunk/drivers/usb/host/ohci-at91.c index 13ebeca8e73e..09f597ad6e00 100644 --- a/trunk/drivers/usb/host/ohci-at91.c +++ b/trunk/drivers/usb/host/ohci-at91.c @@ -94,7 +94,7 @@ static void at91_stop_hc(struct platform_device *pdev) /*-------------------------------------------------------------------------*/ -static void __devexit usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); +static void usb_hcd_at91_remove (struct usb_hcd *, struct platform_device *); /* configure so an HC device and id are always provided */ /* always called with process context; sleeping is OK */ @@ -108,7 +108,7 @@ static void __devexit usb_hcd_at91_remove (struct usb_hcd *, struct platform_dev * then invokes the start() method for the HCD associated with it * through the hotplug entry's driver_data. */ -static int __devinit usb_hcd_at91_probe(const struct hc_driver *driver, +static int usb_hcd_at91_probe(const struct hc_driver *driver, struct platform_device *pdev) { int retval; @@ -203,7 +203,7 @@ static int __devinit usb_hcd_at91_probe(const struct hc_driver *driver, * context, "rmmod" or something similar. * */ -static void __devexit usb_hcd_at91_remove(struct usb_hcd *hcd, +static void usb_hcd_at91_remove(struct usb_hcd *hcd, struct platform_device *pdev) { usb_remove_hcd(hcd); @@ -545,7 +545,7 @@ static int __devinit ohci_at91_of_init(struct platform_device *pdev) /*-------------------------------------------------------------------------*/ -static int __devinit ohci_hcd_at91_drv_probe(struct platform_device *pdev) +static int ohci_hcd_at91_drv_probe(struct platform_device *pdev) { struct at91_usbh_data *pdata; int i; @@ -620,7 +620,7 @@ static int __devinit ohci_hcd_at91_drv_probe(struct platform_device *pdev) return usb_hcd_at91_probe(&ohci_at91_hc_driver, pdev); } -static int __devexit ohci_hcd_at91_drv_remove(struct platform_device *pdev) +static int ohci_hcd_at91_drv_remove(struct platform_device *pdev) { struct at91_usbh_data *pdata = pdev->dev.platform_data; int i; @@ -696,7 +696,7 @@ MODULE_ALIAS("platform:at91_ohci"); static struct platform_driver ohci_hcd_at91_driver = { .probe = ohci_hcd_at91_drv_probe, - .remove = __devexit_p(ohci_hcd_at91_drv_remove), + .remove = ohci_hcd_at91_drv_remove, .shutdown = usb_hcd_platform_shutdown, .suspend = ohci_hcd_at91_drv_suspend, .resume = ohci_hcd_at91_drv_resume, diff --git a/trunk/drivers/usb/misc/usbtest.c b/trunk/drivers/usb/misc/usbtest.c index 9dcb68f04f03..959145baf3cf 100644 --- a/trunk/drivers/usb/misc/usbtest.c +++ b/trunk/drivers/usb/misc/usbtest.c @@ -423,7 +423,7 @@ alloc_sglist(int nents, int max, int vary) unsigned i; unsigned size = max; - sg = kmalloc_array(nents, sizeof *sg, GFP_KERNEL); + sg = kmalloc(nents * sizeof *sg, GFP_KERNEL); if (!sg) return NULL; sg_init_table(sg, nents); @@ -904,9 +904,6 @@ test_ctrl_queue(struct usbtest_dev *dev, struct usbtest_param *param) struct ctrl_ctx context; int i; - if (param->sglen == 0 || param->iterations > UINT_MAX / param->sglen) - return -EOPNOTSUPP; - spin_lock_init(&context.lock); context.dev = dev; init_completion(&context.complete); @@ -1984,6 +1981,8 @@ usbtest_ioctl(struct usb_interface *intf, unsigned int code, void *buf) /* queued control messaging */ case 10: + if (param->sglen == 0) + break; retval = 0; dev_info(&intf->dev, "TEST 10: queue %d control calls, %d times\n", @@ -2277,8 +2276,6 @@ usbtest_probe(struct usb_interface *intf, const struct usb_device_id *id) if (status < 0) { WARNING(dev, "couldn't get endpoints, %d\n", status); - kfree(dev->buf); - kfree(dev); return status; } /* may find bulk or ISO pipes */ diff --git a/trunk/drivers/usb/misc/yurex.c b/trunk/drivers/usb/misc/yurex.c index 70201462e19c..897edda42270 100644 --- a/trunk/drivers/usb/misc/yurex.c +++ b/trunk/drivers/usb/misc/yurex.c @@ -99,7 +99,9 @@ static void yurex_delete(struct kref *kref) usb_put_dev(dev->udev); if (dev->cntl_urb) { usb_kill_urb(dev->cntl_urb); - kfree(dev->cntl_req); + if (dev->cntl_req) + usb_free_coherent(dev->udev, YUREX_BUF_SIZE, + dev->cntl_req, dev->cntl_urb->setup_dma); if (dev->cntl_buffer) usb_free_coherent(dev->udev, YUREX_BUF_SIZE, dev->cntl_buffer, dev->cntl_urb->transfer_dma); @@ -232,7 +234,9 @@ static int yurex_probe(struct usb_interface *interface, const struct usb_device_ } /* allocate buffer for control req */ - dev->cntl_req = kmalloc(YUREX_BUF_SIZE, GFP_KERNEL); + dev->cntl_req = usb_alloc_coherent(dev->udev, YUREX_BUF_SIZE, + GFP_KERNEL, + &dev->cntl_urb->setup_dma); if (!dev->cntl_req) { err("Could not allocate cntl_req"); goto error; @@ -282,7 +286,7 @@ static int yurex_probe(struct usb_interface *interface, const struct usb_device_ usb_rcvintpipe(dev->udev, dev->int_in_endpointAddr), dev->int_buffer, YUREX_BUF_SIZE, yurex_interrupt, dev, 1); - dev->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; + dev->cntl_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; if (usb_submit_urb(dev->urb, GFP_KERNEL)) { retval = -EIO; err("Could not submitting URB"); diff --git a/trunk/drivers/usb/musb/musb_core.c b/trunk/drivers/usb/musb/musb_core.c index 66aaccf04490..0f8b82918a40 100644 --- a/trunk/drivers/usb/musb/musb_core.c +++ b/trunk/drivers/usb/musb/musb_core.c @@ -137,9 +137,6 @@ static int musb_ulpi_read(struct usb_phy *phy, u32 offset) int i = 0; u8 r; u8 power; - int ret; - - pm_runtime_get_sync(phy->io_dev); /* Make sure the transceiver is not in low power mode */ power = musb_readb(addr, MUSB_POWER); @@ -157,22 +154,15 @@ static int musb_ulpi_read(struct usb_phy *phy, u32 offset) while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) & MUSB_ULPI_REG_CMPLT)) { i++; - if (i == 10000) { - ret = -ETIMEDOUT; - goto out; - } + if (i == 10000) + return -ETIMEDOUT; } r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); r &= ~MUSB_ULPI_REG_CMPLT; musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); - ret = musb_readb(addr, MUSB_ULPI_REG_DATA); - -out: - pm_runtime_put(phy->io_dev); - - return ret; + return musb_readb(addr, MUSB_ULPI_REG_DATA); } static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) @@ -181,9 +171,6 @@ static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) int i = 0; u8 r = 0; u8 power; - int ret = 0; - - pm_runtime_get_sync(phy->io_dev); /* Make sure the transceiver is not in low power mode */ power = musb_readb(addr, MUSB_POWER); @@ -197,20 +184,15 @@ static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data) while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) & MUSB_ULPI_REG_CMPLT)) { i++; - if (i == 10000) { - ret = -ETIMEDOUT; - goto out; - } + if (i == 10000) + return -ETIMEDOUT; } r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); r &= ~MUSB_ULPI_REG_CMPLT; musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); -out: - pm_runtime_put(phy->io_dev); - - return ret; + return 0; } #else #define musb_ulpi_read NULL @@ -1922,17 +1904,14 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) if (!musb->isr) { status = -ENODEV; - goto fail2; + goto fail3; } if (!musb->xceiv->io_ops) { - musb->xceiv->io_dev = musb->controller; musb->xceiv->io_priv = musb->mregs; musb->xceiv->io_ops = &musb_ulpi_access; } - pm_runtime_get_sync(musb->controller); - #ifndef CONFIG_MUSB_PIO_ONLY if (use_dma && dev->dma_mask) { struct dma_controller *c; @@ -2044,8 +2023,6 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) goto fail5; #endif - pm_runtime_put(musb->controller); - dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", ({char *s; switch (musb->board_mode) { @@ -2070,9 +2047,6 @@ musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) musb_gadget_cleanup(musb); fail3: - pm_runtime_put_sync(musb->controller); - -fail2: if (musb->irq_wake) device_init_wakeup(dev, 0); musb_platform_exit(musb); diff --git a/trunk/drivers/usb/musb/musb_host.c b/trunk/drivers/usb/musb/musb_host.c index ef8d744800ac..79cb0af779fa 100644 --- a/trunk/drivers/usb/musb/musb_host.c +++ b/trunk/drivers/usb/musb/musb_host.c @@ -2098,7 +2098,7 @@ static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) } /* turn off DMA requests, discard state, stop polling ... */ - if (ep->epnum && is_in) { + if (is_in) { /* giveback saves bulk toggle */ csr = musb_h_flush_rxfifo(ep, 0); diff --git a/trunk/drivers/usb/musb/omap2430.c b/trunk/drivers/usb/musb/omap2430.c index c7785e81254c..2ae0bb309994 100644 --- a/trunk/drivers/usb/musb/omap2430.c +++ b/trunk/drivers/usb/musb/omap2430.c @@ -282,8 +282,7 @@ static void musb_otg_notifier_work(struct work_struct *data_notifier_work) static int omap2430_musb_init(struct musb *musb) { - u32 l; - int status = 0; + u32 l, status = 0; struct device *dev = musb->controller; struct musb_hdrc_platform_data *plat = dev->platform_data; struct omap_musb_board_data *data = plat->board_data; @@ -302,7 +301,7 @@ static int omap2430_musb_init(struct musb *musb) status = pm_runtime_get_sync(dev); if (status < 0) { - dev_err(dev, "pm_runtime_get_sync FAILED %d\n", status); + dev_err(dev, "pm_runtime_get_sync FAILED"); goto err1; } @@ -334,7 +333,6 @@ static int omap2430_musb_init(struct musb *musb) setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); - pm_runtime_put_noidle(musb->controller); return 0; err1: @@ -454,14 +452,14 @@ static int __devinit omap2430_probe(struct platform_device *pdev) goto err2; } - pm_runtime_enable(&pdev->dev); - ret = platform_device_add(musb); if (ret) { dev_err(&pdev->dev, "failed to register musb device\n"); goto err2; } + pm_runtime_enable(&pdev->dev); + return 0; err2: @@ -480,6 +478,7 @@ static int __devexit omap2430_remove(struct platform_device *pdev) platform_device_del(glue->musb); platform_device_put(glue->musb); + pm_runtime_put(&pdev->dev); kfree(glue); return 0; @@ -492,13 +491,11 @@ static int omap2430_runtime_suspend(struct device *dev) struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); - if (musb) { - musb->context.otg_interfsel = musb_readl(musb->mregs, - OTG_INTERFSEL); + musb->context.otg_interfsel = musb_readl(musb->mregs, + OTG_INTERFSEL); - omap2430_low_level_exit(musb); - usb_phy_set_suspend(musb->xceiv, 1); - } + omap2430_low_level_exit(musb); + usb_phy_set_suspend(musb->xceiv, 1); return 0; } @@ -508,13 +505,11 @@ static int omap2430_runtime_resume(struct device *dev) struct omap2430_glue *glue = dev_get_drvdata(dev); struct musb *musb = glue_to_musb(glue); - if (musb) { - omap2430_low_level_init(musb); - musb_writel(musb->mregs, OTG_INTERFSEL, - musb->context.otg_interfsel); + omap2430_low_level_init(musb); + musb_writel(musb->mregs, OTG_INTERFSEL, + musb->context.otg_interfsel); - usb_phy_set_suspend(musb->xceiv, 0); - } + usb_phy_set_suspend(musb->xceiv, 0); return 0; } diff --git a/trunk/drivers/usb/serial/cp210x.c b/trunk/drivers/usb/serial/cp210x.c index ec30f95ef399..0310e2df59f5 100644 --- a/trunk/drivers/usb/serial/cp210x.c +++ b/trunk/drivers/usb/serial/cp210x.c @@ -287,8 +287,7 @@ static int cp210x_get_config(struct usb_serial_port *port, u8 request, /* Issue the request, attempting to read 'size' bytes */ result = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0), request, REQTYPE_DEVICE_TO_HOST, 0x0000, - port_priv->bInterfaceNumber, buf, size, - USB_CTRL_GET_TIMEOUT); + port_priv->bInterfaceNumber, buf, size, 300); /* Convert data into an array of integers */ for (i = 0; i < length; i++) @@ -341,14 +340,12 @@ static int cp210x_set_config(struct usb_serial_port *port, u8 request, result = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), request, REQTYPE_HOST_TO_DEVICE, 0x0000, - port_priv->bInterfaceNumber, buf, size, - USB_CTRL_SET_TIMEOUT); + port_priv->bInterfaceNumber, buf, size, 300); } else { result = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), request, REQTYPE_HOST_TO_DEVICE, data[0], - port_priv->bInterfaceNumber, NULL, 0, - USB_CTRL_SET_TIMEOUT); + port_priv->bInterfaceNumber, NULL, 0, 300); } kfree(buf); diff --git a/trunk/drivers/usb/serial/sierra.c b/trunk/drivers/usb/serial/sierra.c index 8c8bf806f6fa..fdd5aa2c8d82 100644 --- a/trunk/drivers/usb/serial/sierra.c +++ b/trunk/drivers/usb/serial/sierra.c @@ -221,7 +221,7 @@ static const struct sierra_iface_info typeB_interface_list = { }; /* 'blacklist' of interfaces not served by this driver */ -static const u8 direct_ip_non_serial_ifaces[] = { 7, 8, 9, 10, 11, 19, 20 }; +static const u8 direct_ip_non_serial_ifaces[] = { 7, 8, 9, 10, 11 }; static const struct sierra_iface_info direct_ip_interface_blacklist = { .infolen = ARRAY_SIZE(direct_ip_non_serial_ifaces), .ifaceinfo = direct_ip_non_serial_ifaces, @@ -289,6 +289,7 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x1199, 0x6856) }, /* Sierra Wireless AirCard 881 U */ { USB_DEVICE(0x1199, 0x6859) }, /* Sierra Wireless AirCard 885 E */ { USB_DEVICE(0x1199, 0x685A) }, /* Sierra Wireless AirCard 885 E */ + { USB_DEVICE(0x1199, 0x68A2) }, /* Sierra Wireless MC7710 */ /* Sierra Wireless C885 */ { USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x6880, 0xFF, 0xFF, 0xFF)}, /* Sierra Wireless C888, Air Card 501, USB 303, USB 304 */ @@ -298,9 +299,6 @@ static const struct usb_device_id id_table[] = { /* Sierra Wireless HSPA Non-Composite Device */ { USB_DEVICE_AND_INTERFACE_INFO(0x1199, 0x6892, 0xFF, 0xFF, 0xFF)}, { USB_DEVICE(0x1199, 0x6893) }, /* Sierra Wireless Device */ - { USB_DEVICE(0x1199, 0x68A2), /* Sierra Wireless MC77xx in QMI mode */ - .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist - }, { USB_DEVICE(0x1199, 0x68A3), /* Sierra Wireless Direct IP modems */ .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist }, diff --git a/trunk/drivers/uwb/hwa-rc.c b/trunk/drivers/uwb/hwa-rc.c index 810c90ae2c55..66797e9c5010 100644 --- a/trunk/drivers/uwb/hwa-rc.c +++ b/trunk/drivers/uwb/hwa-rc.c @@ -645,8 +645,7 @@ void hwarc_neep_cb(struct urb *urb) dev_err(dev, "NEEP: URB error %d\n", urb->status); } result = usb_submit_urb(urb, GFP_ATOMIC); - if (result < 0 && result != -ENODEV && result != -EPERM) { - /* ignoring unrecoverable errors */ + if (result < 0) { dev_err(dev, "NEEP: Can't resubmit URB (%d) resetting device\n", result); goto error; diff --git a/trunk/drivers/uwb/neh.c b/trunk/drivers/uwb/neh.c index 8cb71bb333c2..a269937be1b8 100644 --- a/trunk/drivers/uwb/neh.c +++ b/trunk/drivers/uwb/neh.c @@ -107,7 +107,6 @@ struct uwb_rc_neh { u8 evt_type; __le16 evt; u8 context; - u8 completed; uwb_rc_cmd_cb_f cb; void *arg; @@ -410,7 +409,6 @@ static void uwb_rc_neh_grok_event(struct uwb_rc *rc, struct uwb_rceb *rceb, size struct device *dev = &rc->uwb_dev.dev; struct uwb_rc_neh *neh; struct uwb_rceb *notif; - unsigned long flags; if (rceb->bEventContext == 0) { notif = kmalloc(size, GFP_ATOMIC); @@ -424,11 +422,7 @@ static void uwb_rc_neh_grok_event(struct uwb_rc *rc, struct uwb_rceb *rceb, size } else { neh = uwb_rc_neh_lookup(rc, rceb); if (neh) { - spin_lock_irqsave(&rc->neh_lock, flags); - /* to guard against a timeout */ - neh->completed = 1; - del_timer(&neh->timer); - spin_unlock_irqrestore(&rc->neh_lock, flags); + del_timer_sync(&neh->timer); uwb_rc_neh_cb(neh, rceb, size); } else dev_warn(dev, "event 0x%02x/%04x/%02x (%zu bytes): nobody cared\n", @@ -574,10 +568,6 @@ static void uwb_rc_neh_timer(unsigned long arg) unsigned long flags; spin_lock_irqsave(&rc->neh_lock, flags); - if (neh->completed) { - spin_unlock_irqrestore(&rc->neh_lock, flags); - return; - } if (neh->context) __uwb_rc_neh_rm(rc, neh); else diff --git a/trunk/drivers/vhost/test.c b/trunk/drivers/vhost/test.c index 3de00d9fae2e..fc9a1d75281f 100644 --- a/trunk/drivers/vhost/test.c +++ b/trunk/drivers/vhost/test.c @@ -155,7 +155,7 @@ static int vhost_test_release(struct inode *inode, struct file *f) vhost_test_stop(n, &private); vhost_test_flush(n); - vhost_dev_cleanup(&n->dev, false); + vhost_dev_cleanup(&n->dev); /* We do an extra flush before freeing memory, * since jobs can re-queue themselves. */ vhost_test_flush(n); diff --git a/trunk/drivers/virtio/virtio_balloon.c b/trunk/drivers/virtio/virtio_balloon.c index c2d05a8279fd..05f0a80818a2 100644 --- a/trunk/drivers/virtio/virtio_balloon.c +++ b/trunk/drivers/virtio/virtio_balloon.c @@ -28,13 +28,6 @@ #include #include -/* - * Balloon device works in 4K page units. So each page is pointed to by - * multiple balloon pages. All memory counters in this driver are in balloon - * page units. - */ -#define VIRTIO_BALLOON_PAGES_PER_PAGE (PAGE_SIZE >> VIRTIO_BALLOON_PFN_SHIFT) - struct virtio_balloon { struct virtio_device *vdev; @@ -49,13 +42,8 @@ struct virtio_balloon /* Waiting for host to ack the pages we released. */ struct completion acked; - /* Number of balloon pages we've told the Host we're not using. */ + /* The pages we've told the Host we're not using. */ unsigned int num_pages; - /* - * The pages we've told the Host we're not using. - * Each page on this list adds VIRTIO_BALLOON_PAGES_PER_PAGE - * to num_pages above. - */ struct list_head pages; /* The array of pfns we tell the Host about. */ @@ -78,13 +66,7 @@ static u32 page_to_balloon_pfn(struct page *page) BUILD_BUG_ON(PAGE_SHIFT < VIRTIO_BALLOON_PFN_SHIFT); /* Convert pfn from Linux page size to balloon page size. */ - return pfn * VIRTIO_BALLOON_PAGES_PER_PAGE; -} - -static struct page *balloon_pfn_to_page(u32 pfn) -{ - BUG_ON(pfn % VIRTIO_BALLOON_PAGES_PER_PAGE); - return pfn_to_page(pfn / VIRTIO_BALLOON_PAGES_PER_PAGE); + return pfn >> (PAGE_SHIFT - VIRTIO_BALLOON_PFN_SHIFT); } static void balloon_ack(struct virtqueue *vq) @@ -114,23 +96,12 @@ static void tell_host(struct virtio_balloon *vb, struct virtqueue *vq) wait_for_completion(&vb->acked); } -static void set_page_pfns(u32 pfns[], struct page *page) -{ - unsigned int i; - - /* Set balloon pfns pointing at this page. - * Note that the first pfn points at start of the page. */ - for (i = 0; i < VIRTIO_BALLOON_PAGES_PER_PAGE; i++) - pfns[i] = page_to_balloon_pfn(page) + i; -} - static void fill_balloon(struct virtio_balloon *vb, size_t num) { /* We can only do one array worth at a time. */ num = min(num, ARRAY_SIZE(vb->pfns)); - for (vb->num_pfns = 0; vb->num_pfns < num; - vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) { + for (vb->num_pfns = 0; vb->num_pfns < num; vb->num_pfns++) { struct page *page = alloc_page(GFP_HIGHUSER | __GFP_NORETRY | __GFP_NOMEMALLOC | __GFP_NOWARN); if (!page) { @@ -142,9 +113,9 @@ static void fill_balloon(struct virtio_balloon *vb, size_t num) msleep(200); break; } - set_page_pfns(vb->pfns + vb->num_pfns, page); - vb->num_pages += VIRTIO_BALLOON_PAGES_PER_PAGE; + vb->pfns[vb->num_pfns] = page_to_balloon_pfn(page); totalram_pages--; + vb->num_pages++; list_add(&page->lru, &vb->pages); } @@ -159,9 +130,8 @@ static void release_pages_by_pfn(const u32 pfns[], unsigned int num) { unsigned int i; - /* Find pfns pointing at start of each page, get pages and free them. */ - for (i = 0; i < num; i += VIRTIO_BALLOON_PAGES_PER_PAGE) { - __free_page(balloon_pfn_to_page(pfns[i])); + for (i = 0; i < num; i++) { + __free_page(pfn_to_page(pfns[i])); totalram_pages++; } } @@ -173,12 +143,11 @@ static void leak_balloon(struct virtio_balloon *vb, size_t num) /* We can only do one array worth at a time. */ num = min(num, ARRAY_SIZE(vb->pfns)); - for (vb->num_pfns = 0; vb->num_pfns < num; - vb->num_pfns += VIRTIO_BALLOON_PAGES_PER_PAGE) { + for (vb->num_pfns = 0; vb->num_pfns < num; vb->num_pfns++) { page = list_first_entry(&vb->pages, struct page, lru); list_del(&page->lru); - set_page_pfns(vb->pfns + vb->num_pfns, page); - vb->num_pages -= VIRTIO_BALLOON_PAGES_PER_PAGE; + vb->pfns[vb->num_pfns] = page_to_balloon_pfn(page); + vb->num_pages--; } /* @@ -265,14 +234,11 @@ static void virtballoon_changed(struct virtio_device *vdev) static inline s64 towards_target(struct virtio_balloon *vb) { - __le32 v; - s64 target; - + u32 v; vb->vdev->config->get(vb->vdev, offsetof(struct virtio_balloon_config, num_pages), &v, sizeof(v)); - target = le32_to_cpu(v); - return target - vb->num_pages; + return (s64)v - vb->num_pages; } static void update_balloon_size(struct virtio_balloon *vb) diff --git a/trunk/drivers/xen/gntdev.c b/trunk/drivers/xen/gntdev.c index 1ffd03bf8e10..99d8151c824a 100644 --- a/trunk/drivers/xen/gntdev.c +++ b/trunk/drivers/xen/gntdev.c @@ -722,7 +722,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma) vma->vm_flags |= VM_RESERVED|VM_DONTEXPAND; if (use_ptemod) - vma->vm_flags |= VM_DONTCOPY; + vma->vm_flags |= VM_DONTCOPY|VM_PFNMAP; vma->vm_private_data = map; diff --git a/trunk/drivers/xen/grant-table.c b/trunk/drivers/xen/grant-table.c index f100ce20b16b..b4d4eac761db 100644 --- a/trunk/drivers/xen/grant-table.c +++ b/trunk/drivers/xen/grant-table.c @@ -1029,7 +1029,6 @@ int gnttab_init(void) int i; unsigned int max_nr_glist_frames, nr_glist_frames; unsigned int nr_init_grefs; - int ret; nr_grant_frames = 1; boot_max_nr_grant_frames = __max_nr_grant_frames(); @@ -1048,16 +1047,12 @@ int gnttab_init(void) nr_glist_frames = (nr_grant_frames * GREFS_PER_GRANT_FRAME + RPP - 1) / RPP; for (i = 0; i < nr_glist_frames; i++) { gnttab_list[i] = (grant_ref_t *)__get_free_page(GFP_KERNEL); - if (gnttab_list[i] == NULL) { - ret = -ENOMEM; + if (gnttab_list[i] == NULL) goto ini_nomem; - } } - if (gnttab_resume() < 0) { - ret = -ENODEV; - goto ini_nomem; - } + if (gnttab_resume() < 0) + return -ENODEV; nr_init_grefs = nr_grant_frames * GREFS_PER_GRANT_FRAME; @@ -1075,7 +1070,7 @@ int gnttab_init(void) for (i--; i >= 0; i--) free_page((unsigned long)gnttab_list[i]); kfree(gnttab_list); - return ret; + return -ENOMEM; } EXPORT_SYMBOL_GPL(gnttab_init); diff --git a/trunk/drivers/xen/manage.c b/trunk/drivers/xen/manage.c index 412b96cc5305..9e14ae6cd49c 100644 --- a/trunk/drivers/xen/manage.c +++ b/trunk/drivers/xen/manage.c @@ -132,7 +132,6 @@ static void do_suspend(void) err = dpm_suspend_end(PMSG_FREEZE); if (err) { printk(KERN_ERR "dpm_suspend_end failed: %d\n", err); - si.cancelled = 0; goto out_resume; } diff --git a/trunk/drivers/xen/xenbus/xenbus_probe_frontend.c b/trunk/drivers/xen/xenbus/xenbus_probe_frontend.c index a31b54d48839..f20c5f178b40 100644 --- a/trunk/drivers/xen/xenbus/xenbus_probe_frontend.c +++ b/trunk/drivers/xen/xenbus/xenbus_probe_frontend.c @@ -135,7 +135,7 @@ static int read_backend_details(struct xenbus_device *xendev) return xenbus_read_otherend_details(xendev, "backend-id", "backend"); } -static int is_device_connecting(struct device *dev, void *data, bool ignore_nonessential) +static int is_device_connecting(struct device *dev, void *data) { struct xenbus_device *xendev = to_xenbus_device(dev); struct device_driver *drv = data; @@ -152,41 +152,16 @@ static int is_device_connecting(struct device *dev, void *data, bool ignore_none if (drv && (dev->driver != drv)) return 0; - if (ignore_nonessential) { - /* With older QEMU, for PVonHVM guests the guest config files - * could contain: vfb = [ 'vnc=1, vnclisten=0.0.0.0'] - * which is nonsensical as there is no PV FB (there can be - * a PVKB) running as HVM guest. */ - - if ((strncmp(xendev->nodename, "device/vkbd", 11) == 0)) - return 0; - - if ((strncmp(xendev->nodename, "device/vfb", 10) == 0)) - return 0; - } xendrv = to_xenbus_driver(dev->driver); return (xendev->state < XenbusStateConnected || (xendev->state == XenbusStateConnected && xendrv->is_ready && !xendrv->is_ready(xendev))); } -static int essential_device_connecting(struct device *dev, void *data) -{ - return is_device_connecting(dev, data, true /* ignore PV[KBB+FB] */); -} -static int non_essential_device_connecting(struct device *dev, void *data) -{ - return is_device_connecting(dev, data, false); -} -static int exists_essential_connecting_device(struct device_driver *drv) +static int exists_connecting_device(struct device_driver *drv) { return bus_for_each_dev(&xenbus_frontend.bus, NULL, drv, - essential_device_connecting); -} -static int exists_non_essential_connecting_device(struct device_driver *drv) -{ - return bus_for_each_dev(&xenbus_frontend.bus, NULL, drv, - non_essential_device_connecting); + is_device_connecting); } static int print_device_status(struct device *dev, void *data) @@ -217,23 +192,6 @@ static int print_device_status(struct device *dev, void *data) /* We only wait for device setup after most initcalls have run. */ static int ready_to_wait_for_devices; -static bool wait_loop(unsigned long start, unsigned int max_delay, - unsigned int *seconds_waited) -{ - if (time_after(jiffies, start + (*seconds_waited+5)*HZ)) { - if (!*seconds_waited) - printk(KERN_WARNING "XENBUS: Waiting for " - "devices to initialise: "); - *seconds_waited += 5; - printk("%us...", max_delay - *seconds_waited); - if (*seconds_waited == max_delay) - return true; - } - - schedule_timeout_interruptible(HZ/10); - - return false; -} /* * On a 5-minute timeout, wait for all devices currently configured. We need * to do this to guarantee that the filesystems and / or network devices @@ -257,14 +215,19 @@ static void wait_for_devices(struct xenbus_driver *xendrv) if (!ready_to_wait_for_devices || !xen_domain()) return; - while (exists_non_essential_connecting_device(drv)) - if (wait_loop(start, 30, &seconds_waited)) - break; - - /* Skips PVKB and PVFB check.*/ - while (exists_essential_connecting_device(drv)) - if (wait_loop(start, 270, &seconds_waited)) - break; + while (exists_connecting_device(drv)) { + if (time_after(jiffies, start + (seconds_waited+5)*HZ)) { + if (!seconds_waited) + printk(KERN_WARNING "XENBUS: Waiting for " + "devices to initialise: "); + seconds_waited += 5; + printk("%us...", 300 - seconds_waited); + if (seconds_waited == 300) + break; + } + + schedule_timeout_interruptible(HZ/10); + } if (seconds_waited) printk("\n"); diff --git a/trunk/fs/aio.c b/trunk/fs/aio.c index 67a6db3e1b6f..da887604dfc5 100644 --- a/trunk/fs/aio.c +++ b/trunk/fs/aio.c @@ -93,8 +93,9 @@ static void aio_free_ring(struct kioctx *ctx) put_page(info->ring_pages[i]); if (info->mmap_size) { - BUG_ON(ctx->mm != current->mm); - vm_munmap(info->mmap_base, info->mmap_size); + down_write(&ctx->mm->mmap_sem); + do_munmap(ctx->mm, info->mmap_base, info->mmap_size); + up_write(&ctx->mm->mmap_sem); } if (info->ring_pages && info->ring_pages != info->internal_pages) @@ -388,17 +389,6 @@ void exit_aio(struct mm_struct *mm) "exit_aio:ioctx still alive: %d %d %d\n", atomic_read(&ctx->users), ctx->dead, ctx->reqs_active); - /* - * We don't need to bother with munmap() here - - * exit_mmap(mm) is coming and it'll unmap everything. - * Since aio_free_ring() uses non-zero ->mmap_size - * as indicator that it needs to unmap the area, - * just set it to 0; aio_free_ring() is the only - * place that uses ->mmap_size, so it's safe. - * That way we get all munmap done to current->mm - - * all other callers have ctx->mm == current->mm. - */ - ctx->ring_info.mmap_size = 0; put_ioctx(ctx); } } diff --git a/trunk/fs/binfmt_aout.c b/trunk/fs/binfmt_aout.c index d146e181d10d..2eb12f13593d 100644 --- a/trunk/fs/binfmt_aout.c +++ b/trunk/fs/binfmt_aout.c @@ -50,7 +50,9 @@ static int set_brk(unsigned long start, unsigned long end) end = PAGE_ALIGN(end); if (end > start) { unsigned long addr; - addr = vm_brk(start, end - start); + down_write(¤t->mm->mmap_sem); + addr = do_brk(start, end - start); + up_write(¤t->mm->mmap_sem); if (BAD_ADDR(addr)) return addr; } @@ -278,7 +280,9 @@ static int load_aout_binary(struct linux_binprm * bprm, struct pt_regs * regs) pos = 32; map_size = ex.a_text+ex.a_data; #endif - error = vm_brk(text_addr & PAGE_MASK, map_size); + down_write(¤t->mm->mmap_sem); + error = do_brk(text_addr & PAGE_MASK, map_size); + up_write(¤t->mm->mmap_sem); if (error != (text_addr & PAGE_MASK)) { send_sig(SIGKILL, current, 0); return error; @@ -309,7 +313,9 @@ static int load_aout_binary(struct linux_binprm * bprm, struct pt_regs * regs) if (!bprm->file->f_op->mmap||((fd_offset & ~PAGE_MASK) != 0)) { loff_t pos = fd_offset; - vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); + down_write(¤t->mm->mmap_sem); + do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data); + up_write(¤t->mm->mmap_sem); bprm->file->f_op->read(bprm->file, (char __user *)N_TXTADDR(ex), ex.a_text+ex.a_data, &pos); @@ -319,20 +325,24 @@ static int load_aout_binary(struct linux_binprm * bprm, struct pt_regs * regs) goto beyond_if; } - error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, + down_write(¤t->mm->mmap_sem); + error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE, fd_offset); + up_write(¤t->mm->mmap_sem); if (error != N_TXTADDR(ex)) { send_sig(SIGKILL, current, 0); return error; } - error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data, + down_write(¤t->mm->mmap_sem); + error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_EXECUTABLE, fd_offset + ex.a_text); + up_write(¤t->mm->mmap_sem); if (error != N_DATADDR(ex)) { send_sig(SIGKILL, current, 0); return error; @@ -402,7 +412,9 @@ static int load_aout_library(struct file *file) "N_TXTOFF is not page aligned. Please convert library: %s\n", file->f_path.dentry->d_name.name); } - vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); + down_write(¤t->mm->mmap_sem); + do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss); + up_write(¤t->mm->mmap_sem); file->f_op->read(file, (char __user *)start_addr, ex.a_text + ex.a_data, &pos); @@ -413,10 +425,12 @@ static int load_aout_library(struct file *file) goto out; } /* Now use mmap to map the library into memory. */ - error = vm_mmap(file, start_addr, ex.a_text + ex.a_data, + down_write(¤t->mm->mmap_sem); + error = do_mmap(file, start_addr, ex.a_text + ex.a_data, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE, N_TXTOFF(ex)); + up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr) goto out; @@ -424,7 +438,9 @@ static int load_aout_library(struct file *file) len = PAGE_ALIGN(ex.a_text + ex.a_data); bss = ex.a_text + ex.a_data + ex.a_bss; if (bss > len) { - error = vm_brk(start_addr + len, bss - len); + down_write(¤t->mm->mmap_sem); + error = do_brk(start_addr + len, bss - len); + up_write(¤t->mm->mmap_sem); retval = error; if (error != start_addr + len) goto out; diff --git a/trunk/fs/binfmt_elf.c b/trunk/fs/binfmt_elf.c index 16f735417072..48ffb3dc610a 100644 --- a/trunk/fs/binfmt_elf.c +++ b/trunk/fs/binfmt_elf.c @@ -82,7 +82,9 @@ static int set_brk(unsigned long start, unsigned long end) end = ELF_PAGEALIGN(end); if (end > start) { unsigned long addr; - addr = vm_brk(start, end - start); + down_write(¤t->mm->mmap_sem); + addr = do_brk(start, end - start); + up_write(¤t->mm->mmap_sem); if (BAD_ADDR(addr)) return addr; } @@ -512,7 +514,9 @@ static unsigned long load_elf_interp(struct elfhdr *interp_elf_ex, elf_bss = ELF_PAGESTART(elf_bss + ELF_MIN_ALIGN - 1); /* Map the last of the bss segment */ - error = vm_brk(elf_bss, last_bss - elf_bss); + down_write(¤t->mm->mmap_sem); + error = do_brk(elf_bss, last_bss - elf_bss); + up_write(¤t->mm->mmap_sem); if (BAD_ADDR(error)) goto out_close; } @@ -958,8 +962,10 @@ static int load_elf_binary(struct linux_binprm *bprm, struct pt_regs *regs) and some applications "depend" upon this behavior. Since we do not have the power to recompile these, we emulate the SVr4 behavior. Sigh. */ - error = vm_mmap(NULL, 0, PAGE_SIZE, PROT_READ | PROT_EXEC, + down_write(¤t->mm->mmap_sem); + error = do_mmap(NULL, 0, PAGE_SIZE, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE, 0); + up_write(¤t->mm->mmap_sem); } #ifdef ELF_PLAT_INIT @@ -1044,7 +1050,8 @@ static int load_elf_library(struct file *file) eppnt++; /* Now use mmap to map the library into memory. */ - error = vm_mmap(file, + down_write(¤t->mm->mmap_sem); + error = do_mmap(file, ELF_PAGESTART(eppnt->p_vaddr), (eppnt->p_filesz + ELF_PAGEOFFSET(eppnt->p_vaddr)), @@ -1052,6 +1059,7 @@ static int load_elf_library(struct file *file) MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE, (eppnt->p_offset - ELF_PAGEOFFSET(eppnt->p_vaddr))); + up_write(¤t->mm->mmap_sem); if (error != ELF_PAGESTART(eppnt->p_vaddr)) goto out_free_ph; @@ -1064,8 +1072,11 @@ static int load_elf_library(struct file *file) len = ELF_PAGESTART(eppnt->p_filesz + eppnt->p_vaddr + ELF_MIN_ALIGN - 1); bss = eppnt->p_memsz + eppnt->p_vaddr; - if (bss > len) - vm_brk(len, bss - len); + if (bss > len) { + down_write(¤t->mm->mmap_sem); + do_brk(len, bss - len); + up_write(¤t->mm->mmap_sem); + } error = 0; out_free_ph: diff --git a/trunk/fs/binfmt_elf_fdpic.c b/trunk/fs/binfmt_elf_fdpic.c index d390a0fffc65..9bd5612a8224 100644 --- a/trunk/fs/binfmt_elf_fdpic.c +++ b/trunk/fs/binfmt_elf_fdpic.c @@ -390,17 +390,21 @@ static int load_elf_fdpic_binary(struct linux_binprm *bprm, (executable_stack == EXSTACK_DEFAULT && VM_STACK_FLAGS & VM_EXEC)) stack_prot |= PROT_EXEC; - current->mm->start_brk = vm_mmap(NULL, 0, stack_size, stack_prot, + down_write(¤t->mm->mmap_sem); + current->mm->start_brk = do_mmap(NULL, 0, stack_size, stack_prot, MAP_PRIVATE | MAP_ANONYMOUS | MAP_UNINITIALIZED | MAP_GROWSDOWN, 0); if (IS_ERR_VALUE(current->mm->start_brk)) { + up_write(¤t->mm->mmap_sem); retval = current->mm->start_brk; current->mm->start_brk = 0; goto error_kill; } + up_write(¤t->mm->mmap_sem); + current->mm->brk = current->mm->start_brk; current->mm->context.end_brk = current->mm->start_brk; current->mm->context.end_brk += @@ -951,8 +955,10 @@ static int elf_fdpic_map_file_constdisp_on_uclinux( if (params->flags & ELF_FDPIC_FLAG_EXECUTABLE) mflags |= MAP_EXECUTABLE; - maddr = vm_mmap(NULL, load_addr, top - base, + down_write(&mm->mmap_sem); + maddr = do_mmap(NULL, load_addr, top - base, PROT_READ | PROT_WRITE | PROT_EXEC, mflags, 0); + up_write(&mm->mmap_sem); if (IS_ERR_VALUE(maddr)) return (int) maddr; @@ -1090,8 +1096,10 @@ static int elf_fdpic_map_file_by_direct_mmap(struct elf_fdpic_params *params, /* create the mapping */ disp = phdr->p_vaddr & ~PAGE_MASK; - maddr = vm_mmap(file, maddr, phdr->p_memsz + disp, prot, flags, + down_write(&mm->mmap_sem); + maddr = do_mmap(file, maddr, phdr->p_memsz + disp, prot, flags, phdr->p_offset - disp); + up_write(&mm->mmap_sem); kdebug("mmap[%d] sz=%lx pr=%x fl=%x of=%lx --> %08lx", loop, phdr->p_memsz + disp, prot, flags, @@ -1135,8 +1143,10 @@ static int elf_fdpic_map_file_by_direct_mmap(struct elf_fdpic_params *params, unsigned long xmaddr; flags |= MAP_FIXED | MAP_ANONYMOUS; - xmaddr = vm_mmap(NULL, xaddr, excess - excess1, + down_write(&mm->mmap_sem); + xmaddr = do_mmap(NULL, xaddr, excess - excess1, prot, flags, 0); + up_write(&mm->mmap_sem); kdebug("mmap[%d] " " ad=%lx sz=%lx pr=%x fl=%x of=0 --> %08lx", diff --git a/trunk/fs/binfmt_flat.c b/trunk/fs/binfmt_flat.c index 6b2daf99fab8..024d20ee3ca3 100644 --- a/trunk/fs/binfmt_flat.c +++ b/trunk/fs/binfmt_flat.c @@ -542,8 +542,10 @@ static int load_flat_file(struct linux_binprm * bprm, */ DBG_FLT("BINFMT_FLAT: ROM mapping of file (we hope)\n"); - textpos = vm_mmap(bprm->file, 0, text_len, PROT_READ|PROT_EXEC, + down_write(¤t->mm->mmap_sem); + textpos = do_mmap(bprm->file, 0, text_len, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_EXECUTABLE, 0); + up_write(¤t->mm->mmap_sem); if (!textpos || IS_ERR_VALUE(textpos)) { if (!textpos) textpos = (unsigned long) -ENOMEM; @@ -554,8 +556,10 @@ static int load_flat_file(struct linux_binprm * bprm, len = data_len + extra + MAX_SHARED_LIBS * sizeof(unsigned long); len = PAGE_ALIGN(len); - realdatastart = vm_mmap(0, 0, len, + down_write(¤t->mm->mmap_sem); + realdatastart = do_mmap(0, 0, len, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE, 0); + up_write(¤t->mm->mmap_sem); if (realdatastart == 0 || IS_ERR_VALUE(realdatastart)) { if (!realdatastart) @@ -599,8 +603,10 @@ static int load_flat_file(struct linux_binprm * bprm, len = text_len + data_len + extra + MAX_SHARED_LIBS * sizeof(unsigned long); len = PAGE_ALIGN(len); - textpos = vm_mmap(0, 0, len, + down_write(¤t->mm->mmap_sem); + textpos = do_mmap(0, 0, len, PROT_READ | PROT_EXEC | PROT_WRITE, MAP_PRIVATE, 0); + up_write(¤t->mm->mmap_sem); if (!textpos || IS_ERR_VALUE(textpos)) { if (!textpos) diff --git a/trunk/fs/binfmt_som.c b/trunk/fs/binfmt_som.c index 4517aaff61b4..e4fc746629a7 100644 --- a/trunk/fs/binfmt_som.c +++ b/trunk/fs/binfmt_som.c @@ -147,8 +147,10 @@ static int map_som_binary(struct file *file, code_size = SOM_PAGEALIGN(hpuxhdr->exec_tsize); current->mm->start_code = code_start; current->mm->end_code = code_start + code_size; - retval = vm_mmap(file, code_start, code_size, prot, + down_write(¤t->mm->mmap_sem); + retval = do_mmap(file, code_start, code_size, prot, flags, SOM_PAGESTART(hpuxhdr->exec_tfile)); + up_write(¤t->mm->mmap_sem); if (retval < 0 && retval > -1024) goto out; @@ -156,16 +158,20 @@ static int map_som_binary(struct file *file, data_size = SOM_PAGEALIGN(hpuxhdr->exec_dsize); current->mm->start_data = data_start; current->mm->end_data = bss_start = data_start + data_size; - retval = vm_mmap(file, data_start, data_size, + down_write(¤t->mm->mmap_sem); + retval = do_mmap(file, data_start, data_size, prot | PROT_WRITE, flags, SOM_PAGESTART(hpuxhdr->exec_dfile)); + up_write(¤t->mm->mmap_sem); if (retval < 0 && retval > -1024) goto out; som_brk = bss_start + SOM_PAGEALIGN(hpuxhdr->exec_bsize); current->mm->start_brk = current->mm->brk = som_brk; - retval = vm_mmap(NULL, bss_start, som_brk - bss_start, + down_write(¤t->mm->mmap_sem); + retval = do_mmap(NULL, bss_start, som_brk - bss_start, prot | PROT_WRITE, MAP_FIXED | MAP_PRIVATE, 0); + up_write(¤t->mm->mmap_sem); if (retval > 0 || retval < -1024) retval = 0; out: diff --git a/trunk/fs/btrfs/ctree.h b/trunk/fs/btrfs/ctree.h index 3f65a812e282..5b8ef8eb3521 100644 --- a/trunk/fs/btrfs/ctree.h +++ b/trunk/fs/btrfs/ctree.h @@ -2166,7 +2166,7 @@ BTRFS_SETGET_STACK_FUNCS(root_last_snapshot, struct btrfs_root_item, static inline bool btrfs_root_readonly(struct btrfs_root *root) { - return (root->root_item.flags & cpu_to_le64(BTRFS_ROOT_SUBVOL_RDONLY)) != 0; + return root->root_item.flags & BTRFS_ROOT_SUBVOL_RDONLY; } /* struct btrfs_root_backup */ diff --git a/trunk/fs/cifs/connect.c b/trunk/fs/cifs/connect.c index f31dc9ac37b7..d81e933a796b 100644 --- a/trunk/fs/cifs/connect.c +++ b/trunk/fs/cifs/connect.c @@ -109,8 +109,6 @@ enum { /* Options which could be blank */ Opt_blank_pass, - Opt_blank_user, - Opt_blank_ip, Opt_err }; @@ -185,15 +183,11 @@ static const match_table_t cifs_mount_option_tokens = { { Opt_wsize, "wsize=%s" }, { Opt_actimeo, "actimeo=%s" }, - { Opt_blank_user, "user=" }, - { Opt_blank_user, "username=" }, { Opt_user, "user=%s" }, { Opt_user, "username=%s" }, { Opt_blank_pass, "pass=" }, { Opt_pass, "pass=%s" }, { Opt_pass, "password=%s" }, - { Opt_blank_ip, "ip=" }, - { Opt_blank_ip, "addr=" }, { Opt_ip, "ip=%s" }, { Opt_ip, "addr=%s" }, { Opt_unc, "unc=%s" }, @@ -1123,7 +1117,7 @@ static int get_option_ul(substring_t args[], unsigned long *option) string = match_strdup(args); if (string == NULL) return -ENOMEM; - rc = kstrtoul(string, 0, option); + rc = kstrtoul(string, 10, option); kfree(string); return rc; @@ -1540,17 +1534,15 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, /* String Arguments */ - case Opt_blank_user: - /* null user, ie. anonymous authentication */ - vol->nullauth = 1; - vol->username = NULL; - break; case Opt_user: string = match_strdup(args); if (string == NULL) goto out_nomem; - if (strnlen(string, MAX_USERNAME_SIZE) > + if (!*string) { + /* null user, ie. anonymous authentication */ + vol->nullauth = 1; + } else if (strnlen(string, MAX_USERNAME_SIZE) > MAX_USERNAME_SIZE) { printk(KERN_WARNING "CIFS: username too long\n"); goto cifs_parse_mount_err; @@ -1619,15 +1611,14 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, } vol->password[j] = '\0'; break; - case Opt_blank_ip: - vol->UNCip = NULL; - break; case Opt_ip: string = match_strdup(args); if (string == NULL) goto out_nomem; - if (strnlen(string, INET6_ADDRSTRLEN) > + if (!*string) { + vol->UNCip = NULL; + } else if (strnlen(string, INET6_ADDRSTRLEN) > INET6_ADDRSTRLEN) { printk(KERN_WARNING "CIFS: ip address " "too long\n"); @@ -1645,6 +1636,12 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: invalid path to " + "network resource\n"); + goto cifs_parse_mount_err; + } + temp_len = strnlen(string, 300); if (temp_len == 300) { printk(KERN_WARNING "CIFS: UNC name too long\n"); @@ -1673,7 +1670,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; - if (strnlen(string, 256) == 256) { + if (!*string) { + printk(KERN_WARNING "CIFS: invalid domain" + " name\n"); + goto cifs_parse_mount_err; + } else if (strnlen(string, 256) == 256) { printk(KERN_WARNING "CIFS: domain name too" " long\n"); goto cifs_parse_mount_err; @@ -1692,7 +1693,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; - if (!cifs_convert_address( + if (!*string) { + printk(KERN_WARNING "CIFS: srcaddr value not" + " specified\n"); + goto cifs_parse_mount_err; + } else if (!cifs_convert_address( (struct sockaddr *)&vol->srcaddr, string, strlen(string))) { printk(KERN_WARNING "CIFS: Could not parse" @@ -1705,6 +1710,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: Invalid path" + " prefix\n"); + goto cifs_parse_mount_err; + } temp_len = strnlen(string, 1024); if (string[0] != '/') temp_len++; /* missing leading slash */ @@ -1732,7 +1742,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; - if (strnlen(string, 1024) >= 65) { + if (!*string) { + printk(KERN_WARNING "CIFS: Invalid iocharset" + " specified\n"); + goto cifs_parse_mount_err; + } else if (strnlen(string, 1024) >= 65) { printk(KERN_WARNING "CIFS: iocharset name " "too long.\n"); goto cifs_parse_mount_err; @@ -1757,6 +1771,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: No socket option" + " specified\n"); + goto cifs_parse_mount_err; + } if (strnicmp(string, "TCP_NODELAY", 11) == 0) vol->sockopt_tcp_nodelay = 1; break; @@ -1765,6 +1784,12 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: Invalid (empty)" + " netbiosname\n"); + break; + } + memset(vol->source_rfc1001_name, 0x20, RFC1001_NAME_LEN); /* @@ -1792,6 +1817,11 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: Empty server" + " netbiosname specified\n"); + break; + } /* last byte, type, is 0x20 for servr type */ memset(vol->target_rfc1001_name, 0x20, RFC1001_NAME_LEN_WITH_NULL); @@ -1818,6 +1848,12 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + cERROR(1, "no protocol version specified" + " after vers= mount option"); + goto cifs_parse_mount_err; + } + if (strnicmp(string, "cifs", 4) == 0 || strnicmp(string, "1", 1) == 0) { /* This is the default */ @@ -1832,6 +1868,12 @@ cifs_parse_mount_options(const char *mountdata, const char *devname, if (string == NULL) goto out_nomem; + if (!*string) { + printk(KERN_WARNING "CIFS: no security flavor" + " specified\n"); + break; + } + if (cifs_parse_security_flavors(string, vol) != 0) goto cifs_parse_mount_err; break; diff --git a/trunk/fs/ext4/ext4.h b/trunk/fs/ext4/ext4.h index 0e01e90add8b..ab2594a30f86 100644 --- a/trunk/fs/ext4/ext4.h +++ b/trunk/fs/ext4/ext4.h @@ -1203,6 +1203,9 @@ struct ext4_sb_info { unsigned long s_ext_blocks; unsigned long s_ext_extents; #endif + /* ext4 extent cache stats */ + unsigned long extent_cache_hits; + unsigned long extent_cache_misses; /* for buddy allocator */ struct ext4_group_info ***s_group_info; diff --git a/trunk/fs/ext4/extents.c b/trunk/fs/ext4/extents.c index abcdeab67f52..1421938e6792 100644 --- a/trunk/fs/ext4/extents.c +++ b/trunk/fs/ext4/extents.c @@ -2066,6 +2066,10 @@ static int ext4_ext_check_cache(struct inode *inode, ext4_lblk_t block, ret = 1; } errout: + if (!ret) + sbi->extent_cache_misses++; + else + sbi->extent_cache_hits++; trace_ext4_ext_in_cache(inode, block, ret); spin_unlock(&EXT4_I(inode)->i_block_reservation_lock); return ret; @@ -2878,7 +2882,7 @@ static int ext4_split_extent_at(handle_t *handle, if (err) goto fix_extent_len; /* update the extent length and mark as initialized */ - ex->ee_len = cpu_to_le16(ee_len); + ex->ee_len = cpu_to_le32(ee_len); ext4_ext_try_to_merge(inode, path, ex); err = ext4_ext_dirty(handle, inode, path + depth); goto out; diff --git a/trunk/fs/ext4/super.c b/trunk/fs/ext4/super.c index 6da193564e43..ceebaf853beb 100644 --- a/trunk/fs/ext4/super.c +++ b/trunk/fs/ext4/super.c @@ -1305,20 +1305,20 @@ static int set_qf_name(struct super_block *sb, int qtype, substring_t *args) ext4_msg(sb, KERN_ERR, "Cannot change journaled " "quota options when quota turned on"); - return -1; + return 0; } qname = match_strdup(args); if (!qname) { ext4_msg(sb, KERN_ERR, "Not enough memory for storing quotafile name"); - return -1; + return 0; } if (sbi->s_qf_names[qtype] && strcmp(sbi->s_qf_names[qtype], qname)) { ext4_msg(sb, KERN_ERR, "%s quota file already specified", QTYPE2NAME(qtype)); kfree(qname); - return -1; + return 0; } sbi->s_qf_names[qtype] = qname; if (strchr(sbi->s_qf_names[qtype], '/')) { @@ -1326,7 +1326,7 @@ static int set_qf_name(struct super_block *sb, int qtype, substring_t *args) "quotafile must be on filesystem root"); kfree(sbi->s_qf_names[qtype]); sbi->s_qf_names[qtype] = NULL; - return -1; + return 0; } set_opt(sb, QUOTA); return 1; @@ -1341,7 +1341,7 @@ static int clear_qf_name(struct super_block *sb, int qtype) sbi->s_qf_names[qtype]) { ext4_msg(sb, KERN_ERR, "Cannot change journaled quota options" " when quota turned on"); - return -1; + return 0; } /* * The space will be released later when all options are confirmed @@ -1450,16 +1450,6 @@ static int handle_mount_opt(struct super_block *sb, char *opt, int token, const struct mount_opts *m; int arg = 0; -#ifdef CONFIG_QUOTA - if (token == Opt_usrjquota) - return set_qf_name(sb, USRQUOTA, &args[0]); - else if (token == Opt_grpjquota) - return set_qf_name(sb, GRPQUOTA, &args[0]); - else if (token == Opt_offusrjquota) - return clear_qf_name(sb, USRQUOTA); - else if (token == Opt_offgrpjquota) - return clear_qf_name(sb, GRPQUOTA); -#endif if (args->from && match_int(args, &arg)) return -1; switch (token) { @@ -1559,6 +1549,18 @@ static int handle_mount_opt(struct super_block *sb, char *opt, int token, sbi->s_mount_opt |= m->mount_opt; } #ifdef CONFIG_QUOTA + } else if (token == Opt_usrjquota) { + if (!set_qf_name(sb, USRQUOTA, &args[0])) + return -1; + } else if (token == Opt_grpjquota) { + if (!set_qf_name(sb, GRPQUOTA, &args[0])) + return -1; + } else if (token == Opt_offusrjquota) { + if (!clear_qf_name(sb, USRQUOTA)) + return -1; + } else if (token == Opt_offgrpjquota) { + if (!clear_qf_name(sb, GRPQUOTA)) + return -1; } else if (m->flags & MOPT_QFMT) { if (sb_any_quota_loaded(sb) && sbi->s_jquota_fmt != m->mount_opt) { @@ -2364,6 +2366,18 @@ static ssize_t lifetime_write_kbytes_show(struct ext4_attr *a, EXT4_SB(sb)->s_sectors_written_start) >> 1))); } +static ssize_t extent_cache_hits_show(struct ext4_attr *a, + struct ext4_sb_info *sbi, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%lu\n", sbi->extent_cache_hits); +} + +static ssize_t extent_cache_misses_show(struct ext4_attr *a, + struct ext4_sb_info *sbi, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%lu\n", sbi->extent_cache_misses); +} + static ssize_t inode_readahead_blks_store(struct ext4_attr *a, struct ext4_sb_info *sbi, const char *buf, size_t count) @@ -2421,6 +2435,8 @@ static struct ext4_attr ext4_attr_##name = __ATTR(name, mode, show, store) EXT4_RO_ATTR(delayed_allocation_blocks); EXT4_RO_ATTR(session_write_kbytes); EXT4_RO_ATTR(lifetime_write_kbytes); +EXT4_RO_ATTR(extent_cache_hits); +EXT4_RO_ATTR(extent_cache_misses); EXT4_ATTR_OFFSET(inode_readahead_blks, 0644, sbi_ui_show, inode_readahead_blks_store, s_inode_readahead_blks); EXT4_RW_ATTR_SBI_UI(inode_goal, s_inode_goal); @@ -2436,6 +2452,8 @@ static struct attribute *ext4_attrs[] = { ATTR_LIST(delayed_allocation_blocks), ATTR_LIST(session_write_kbytes), ATTR_LIST(lifetime_write_kbytes), + ATTR_LIST(extent_cache_hits), + ATTR_LIST(extent_cache_misses), ATTR_LIST(inode_readahead_blks), ATTR_LIST(inode_goal), ATTR_LIST(mb_stats), diff --git a/trunk/fs/fuse/dir.c b/trunk/fs/fuse/dir.c index df5ac048dc74..206632887bb4 100644 --- a/trunk/fs/fuse/dir.c +++ b/trunk/fs/fuse/dir.c @@ -387,6 +387,9 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, if (fc->no_create) return -ENOSYS; + if (flags & O_DIRECT) + return -EINVAL; + forget = fuse_alloc_forget(); if (!forget) return -ENOMEM; @@ -641,12 +644,13 @@ static int fuse_unlink(struct inode *dir, struct dentry *entry) fuse_put_request(fc, req); if (!err) { struct inode *inode = entry->d_inode; - struct fuse_inode *fi = get_fuse_inode(inode); - spin_lock(&fc->lock); - fi->attr_version = ++fc->attr_version; - drop_nlink(inode); - spin_unlock(&fc->lock); + /* + * Set nlink to zero so the inode can be cleared, if the inode + * does have more links this will be discovered at the next + * lookup/getattr. + */ + clear_nlink(inode); fuse_invalidate_attr(inode); fuse_invalidate_attr(dir); fuse_invalidate_entry_cache(entry); @@ -758,17 +762,8 @@ static int fuse_link(struct dentry *entry, struct inode *newdir, will reflect changes in the backing inode (link count, etc.) */ - if (!err) { - struct fuse_inode *fi = get_fuse_inode(inode); - - spin_lock(&fc->lock); - fi->attr_version = ++fc->attr_version; - inc_nlink(inode); - spin_unlock(&fc->lock); - fuse_invalidate_attr(inode); - } else if (err == -EINTR) { + if (!err || err == -EINTR) fuse_invalidate_attr(inode); - } return err; } diff --git a/trunk/fs/fuse/file.c b/trunk/fs/fuse/file.c index 504e61b7fd75..a841868bf9ce 100644 --- a/trunk/fs/fuse/file.c +++ b/trunk/fs/fuse/file.c @@ -194,6 +194,10 @@ int fuse_open_common(struct inode *inode, struct file *file, bool isdir) struct fuse_conn *fc = get_fuse_conn(inode); int err; + /* VFS checks this, but only _after_ ->open() */ + if (file->f_flags & O_DIRECT) + return -EINVAL; + err = generic_file_open(inode, file); if (err) return err; @@ -928,23 +932,17 @@ static ssize_t fuse_file_aio_write(struct kiocb *iocb, const struct iovec *iov, struct file *file = iocb->ki_filp; struct address_space *mapping = file->f_mapping; size_t count = 0; - size_t ocount = 0; ssize_t written = 0; - ssize_t written_buffered = 0; struct inode *inode = mapping->host; ssize_t err; struct iov_iter i; - loff_t endbyte = 0; WARN_ON(iocb->ki_pos != pos); - ocount = 0; - err = generic_segment_checks(iov, &nr_segs, &ocount, VERIFY_READ); + err = generic_segment_checks(iov, &nr_segs, &count, VERIFY_READ); if (err) return err; - count = ocount; - mutex_lock(&inode->i_mutex); vfs_check_frozen(inode->i_sb, SB_FREEZE_WRITE); @@ -964,41 +962,11 @@ static ssize_t fuse_file_aio_write(struct kiocb *iocb, const struct iovec *iov, file_update_time(file); - if (file->f_flags & O_DIRECT) { - written = generic_file_direct_write(iocb, iov, &nr_segs, - pos, &iocb->ki_pos, - count, ocount); - if (written < 0 || written == count) - goto out; - - pos += written; - count -= written; + iov_iter_init(&i, iov, nr_segs, count, 0); + written = fuse_perform_write(file, mapping, &i, pos); + if (written >= 0) + iocb->ki_pos = pos + written; - iov_iter_init(&i, iov, nr_segs, count, written); - written_buffered = fuse_perform_write(file, mapping, &i, pos); - if (written_buffered < 0) { - err = written_buffered; - goto out; - } - endbyte = pos + written_buffered - 1; - - err = filemap_write_and_wait_range(file->f_mapping, pos, - endbyte); - if (err) - goto out; - - invalidate_mapping_pages(file->f_mapping, - pos >> PAGE_CACHE_SHIFT, - endbyte >> PAGE_CACHE_SHIFT); - - written += written_buffered; - iocb->ki_pos = pos + written_buffered; - } else { - iov_iter_init(&i, iov, nr_segs, count, 0); - written = fuse_perform_write(file, mapping, &i, pos); - if (written >= 0) - iocb->ki_pos = pos + written; - } out: current->backing_dev_info = NULL; mutex_unlock(&inode->i_mutex); @@ -1133,24 +1101,6 @@ static ssize_t fuse_direct_read(struct file *file, char __user *buf, return res; } -static ssize_t __fuse_direct_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - struct inode *inode = file->f_path.dentry->d_inode; - ssize_t res; - - res = generic_write_checks(file, ppos, &count, 0); - if (!res) { - res = fuse_direct_io(file, buf, count, ppos, 1); - if (res > 0) - fuse_write_update_size(inode, *ppos); - } - - fuse_invalidate_attr(inode); - - return res; -} - static ssize_t fuse_direct_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { @@ -1162,9 +1112,16 @@ static ssize_t fuse_direct_write(struct file *file, const char __user *buf, /* Don't allow parallel writes to the same file */ mutex_lock(&inode->i_mutex); - res = __fuse_direct_write(file, buf, count, ppos); + res = generic_write_checks(file, ppos, &count, 0); + if (!res) { + res = fuse_direct_io(file, buf, count, ppos, 1); + if (res > 0) + fuse_write_update_size(inode, *ppos); + } mutex_unlock(&inode->i_mutex); + fuse_invalidate_attr(inode); + return res; } @@ -2120,57 +2077,6 @@ int fuse_notify_poll_wakeup(struct fuse_conn *fc, return 0; } -static ssize_t fuse_loop_dio(struct file *filp, const struct iovec *iov, - unsigned long nr_segs, loff_t *ppos, int rw) -{ - const struct iovec *vector = iov; - ssize_t ret = 0; - - while (nr_segs > 0) { - void __user *base; - size_t len; - ssize_t nr; - - base = vector->iov_base; - len = vector->iov_len; - vector++; - nr_segs--; - - if (rw == WRITE) - nr = __fuse_direct_write(filp, base, len, ppos); - else - nr = fuse_direct_read(filp, base, len, ppos); - - if (nr < 0) { - if (!ret) - ret = nr; - break; - } - ret += nr; - if (nr != len) - break; - } - - return ret; -} - - -static ssize_t -fuse_direct_IO(int rw, struct kiocb *iocb, const struct iovec *iov, - loff_t offset, unsigned long nr_segs) -{ - ssize_t ret = 0; - struct file *file = NULL; - loff_t pos = 0; - - file = iocb->ki_filp; - pos = offset; - - ret = fuse_loop_dio(file, iov, nr_segs, &pos, rw); - - return ret; -} - static const struct file_operations fuse_file_operations = { .llseek = fuse_file_llseek, .read = do_sync_read, @@ -2214,7 +2120,6 @@ static const struct address_space_operations fuse_file_aops = { .readpages = fuse_readpages, .set_page_dirty = __set_page_dirty_nobuffers, .bmap = fuse_bmap, - .direct_IO = fuse_direct_IO, }; void fuse_init_file_inode(struct inode *inode) diff --git a/trunk/fs/fuse/inode.c b/trunk/fs/fuse/inode.c index 26783eb2b1fc..4aec5995867e 100644 --- a/trunk/fs/fuse/inode.c +++ b/trunk/fs/fuse/inode.c @@ -947,7 +947,6 @@ static int fuse_fill_super(struct super_block *sb, void *data, int silent) sb->s_magic = FUSE_SUPER_MAGIC; sb->s_op = &fuse_super_operations; sb->s_maxbytes = MAX_LFS_FILESIZE; - sb->s_time_gran = 1; sb->s_export_op = &fuse_export_operations; file = fget(d.fd); diff --git a/trunk/fs/lockd/clnt4xdr.c b/trunk/fs/lockd/clnt4xdr.c index 13ad1539fbf2..3ddcbb1c0a43 100644 --- a/trunk/fs/lockd/clnt4xdr.c +++ b/trunk/fs/lockd/clnt4xdr.c @@ -241,7 +241,7 @@ static int decode_nlm4_stat(struct xdr_stream *xdr, __be32 *stat) p = xdr_inline_decode(xdr, 4); if (unlikely(p == NULL)) goto out_overflow; - if (unlikely(ntohl(*p) > ntohl(nlm4_failed))) + if (unlikely(*p > nlm4_failed)) goto out_bad_xdr; *stat = *p; return 0; diff --git a/trunk/fs/lockd/clntxdr.c b/trunk/fs/lockd/clntxdr.c index d269ada7670e..3d35e3e80c1c 100644 --- a/trunk/fs/lockd/clntxdr.c +++ b/trunk/fs/lockd/clntxdr.c @@ -236,7 +236,7 @@ static int decode_nlm_stat(struct xdr_stream *xdr, p = xdr_inline_decode(xdr, 4); if (unlikely(p == NULL)) goto out_overflow; - if (unlikely(ntohl(*p) > ntohl(nlm_lck_denied_grace_period))) + if (unlikely(*p > nlm_lck_denied_grace_period)) goto out_enum; *stat = *p; return 0; diff --git a/trunk/fs/nfsd/nfs3xdr.c b/trunk/fs/nfsd/nfs3xdr.c index 43f46cd9edea..08c6e36ab2eb 100644 --- a/trunk/fs/nfsd/nfs3xdr.c +++ b/trunk/fs/nfsd/nfs3xdr.c @@ -803,13 +803,13 @@ encode_entry_baggage(struct nfsd3_readdirres *cd, __be32 *p, const char *name, return p; } -static __be32 +static int compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, const char *name, int namlen) { struct svc_export *exp; struct dentry *dparent, *dchild; - __be32 rv = nfserr_noent; + int rv = 0; dparent = cd->fh.fh_dentry; exp = cd->fh.fh_export; @@ -817,20 +817,26 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, if (isdotent(name, namlen)) { if (namlen == 2) { dchild = dget_parent(dparent); - /* filesystem root - cannot return filehandle for ".." */ - if (dchild == dparent) - goto out; + if (dchild == dparent) { + /* filesystem root - cannot return filehandle for ".." */ + dput(dchild); + return -ENOENT; + } } else dchild = dget(dparent); } else dchild = lookup_one_len(name, dparent, namlen); if (IS_ERR(dchild)) - return rv; + return -ENOENT; + rv = -ENOENT; if (d_mountpoint(dchild)) goto out; + rv = fh_compose(fhp, exp, dchild, &cd->fh); + if (rv) + goto out; if (!dchild->d_inode) goto out; - rv = fh_compose(fhp, exp, dchild, &cd->fh); + rv = 0; out: dput(dchild); return rv; @@ -839,7 +845,7 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, static __be32 *encode_entryplus_baggage(struct nfsd3_readdirres *cd, __be32 *p, const char *name, int namlen) { struct svc_fh fh; - __be32 err; + int err; fh_init(&fh, NFS3_FHSIZE); err = compose_entry_fh(cd, &fh, name, namlen); diff --git a/trunk/fs/nfsd/nfs4proc.c b/trunk/fs/nfsd/nfs4proc.c index 987e719fbae8..2ed14dfd00a2 100644 --- a/trunk/fs/nfsd/nfs4proc.c +++ b/trunk/fs/nfsd/nfs4proc.c @@ -235,15 +235,15 @@ do_open_lookup(struct svc_rqst *rqstp, struct svc_fh *current_fh, struct nfsd4_o */ if (open->op_createmode == NFS4_CREATE_EXCLUSIVE && status == 0) open->op_bmval[1] = (FATTR4_WORD1_TIME_ACCESS | - FATTR4_WORD1_TIME_MODIFY); + FATTR4_WORD1_TIME_MODIFY); } else { status = nfsd_lookup(rqstp, current_fh, open->op_fname.data, open->op_fname.len, resfh); fh_unlock(current_fh); + if (status) + goto out; + status = nfsd_check_obj_isreg(resfh); } - if (status) - goto out; - status = nfsd_check_obj_isreg(resfh); if (status) goto out; @@ -841,7 +841,6 @@ nfsd4_setattr(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct nfsd4_setattr *setattr) { __be32 status = nfs_ok; - int err; if (setattr->sa_iattr.ia_valid & ATTR_SIZE) { nfs4_lock_state(); @@ -853,9 +852,9 @@ nfsd4_setattr(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, return status; } } - err = fh_want_write(&cstate->current_fh); - if (err) - return nfserrno(err); + status = fh_want_write(&cstate->current_fh); + if (status) + return status; status = nfs_ok; status = check_attr_support(rqstp, cstate, setattr->sa_bmval, diff --git a/trunk/fs/nfsd/nfs4state.c b/trunk/fs/nfsd/nfs4state.c index 7f71c69cdcdf..1841f8bf845e 100644 --- a/trunk/fs/nfsd/nfs4state.c +++ b/trunk/fs/nfsd/nfs4state.c @@ -4211,14 +4211,16 @@ nfsd4_lock(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, * vfs_test_lock. (Arguably perhaps test_lock should be done with an * inode operation.) */ -static __be32 nfsd_test_lock(struct svc_rqst *rqstp, struct svc_fh *fhp, struct file_lock *lock) +static int nfsd_test_lock(struct svc_rqst *rqstp, struct svc_fh *fhp, struct file_lock *lock) { struct file *file; - __be32 err = nfsd_open(rqstp, fhp, S_IFREG, NFSD_MAY_READ, &file); - if (!err) { - err = nfserrno(vfs_test_lock(file, lock)); - nfsd_close(file); - } + int err; + + err = nfsd_open(rqstp, fhp, S_IFREG, NFSD_MAY_READ, &file); + if (err) + return err; + err = vfs_test_lock(file, lock); + nfsd_close(file); return err; } @@ -4232,6 +4234,7 @@ nfsd4_lockt(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, struct inode *inode; struct file_lock file_lock; struct nfs4_lockowner *lo; + int error; __be32 status; if (locks_in_grace()) @@ -4277,10 +4280,12 @@ nfsd4_lockt(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, nfs4_transform_lock_offset(&file_lock); - status = nfsd_test_lock(rqstp, &cstate->current_fh, &file_lock); - if (status) + status = nfs_ok; + error = nfsd_test_lock(rqstp, &cstate->current_fh, &file_lock); + if (error) { + status = nfserrno(error); goto out; - + } if (file_lock.fl_type != F_UNLCK) { status = nfserr_denied; nfs4_set_lock_denied(&file_lock, &lockt->lt_denied); diff --git a/trunk/fs/nfsd/nfs4xdr.c b/trunk/fs/nfsd/nfs4xdr.c index 74c00bc92b9a..bcd8904ab1e3 100644 --- a/trunk/fs/nfsd/nfs4xdr.c +++ b/trunk/fs/nfsd/nfs4xdr.c @@ -1392,7 +1392,7 @@ nfsd4_decode_test_stateid(struct nfsd4_compoundargs *argp, struct nfsd4_test_sta for (i = 0; i < test_stateid->ts_num_ids; i++) { stateid = kmalloc(sizeof(struct nfsd4_test_stateid_id), GFP_KERNEL); if (!stateid) { - status = nfserrno(-ENOMEM); + status = PTR_ERR(stateid); goto out; } @@ -3410,7 +3410,7 @@ nfsd4_encode_test_stateid(struct nfsd4_compoundres *resp, int nfserr, *p++ = htonl(test_stateid->ts_num_ids); list_for_each_entry_safe(stateid, next, &test_stateid->ts_stateid_list, ts_id_list) { - *p++ = stateid->ts_id_status; + *p++ = htonl(stateid->ts_id_status); } ADJUST_ARGS(); diff --git a/trunk/fs/nfsd/vfs.c b/trunk/fs/nfsd/vfs.c index 568666156ea4..296d671654d6 100644 --- a/trunk/fs/nfsd/vfs.c +++ b/trunk/fs/nfsd/vfs.c @@ -1458,7 +1458,7 @@ do_nfsd_create(struct svc_rqst *rqstp, struct svc_fh *fhp, switch (createmode) { case NFS3_CREATE_UNCHECKED: if (! S_ISREG(dchild->d_inode->i_mode)) - goto out; + err = nfserr_exist; else if (truncp) { /* in nfsv4, we need to treat this case a little * differently. we don't want to truncate the diff --git a/trunk/fs/ocfs2/alloc.c b/trunk/fs/ocfs2/alloc.c index 31b9463fba1f..3165aebb43c8 100644 --- a/trunk/fs/ocfs2/alloc.c +++ b/trunk/fs/ocfs2/alloc.c @@ -1134,7 +1134,7 @@ static int ocfs2_adjust_rightmost_branch(handle_t *handle, } el = path_leaf_el(path); - rec = &el->l_recs[le16_to_cpu(el->l_next_free_rec) - 1]; + rec = &el->l_recs[le32_to_cpu(el->l_next_free_rec) - 1]; ocfs2_adjust_rightmost_records(handle, et, path, rec); diff --git a/trunk/fs/ocfs2/refcounttree.c b/trunk/fs/ocfs2/refcounttree.c index 9f32d7cbb7a3..cf7823382664 100644 --- a/trunk/fs/ocfs2/refcounttree.c +++ b/trunk/fs/ocfs2/refcounttree.c @@ -1036,14 +1036,14 @@ static int ocfs2_get_refcount_cpos_end(struct ocfs2_caching_info *ci, tmp_el = left_path->p_node[subtree_root].el; blkno = left_path->p_node[subtree_root+1].bh->b_blocknr; - for (i = 0; i < le16_to_cpu(tmp_el->l_next_free_rec); i++) { + for (i = 0; i < le32_to_cpu(tmp_el->l_next_free_rec); i++) { if (le64_to_cpu(tmp_el->l_recs[i].e_blkno) == blkno) { *cpos_end = le32_to_cpu(tmp_el->l_recs[i+1].e_cpos); break; } } - BUG_ON(i == le16_to_cpu(tmp_el->l_next_free_rec)); + BUG_ON(i == le32_to_cpu(tmp_el->l_next_free_rec)); out: ocfs2_free_path(left_path); @@ -1468,7 +1468,7 @@ static int ocfs2_divide_leaf_refcount_block(struct buffer_head *ref_leaf_bh, trace_ocfs2_divide_leaf_refcount_block( (unsigned long long)ref_leaf_bh->b_blocknr, - le16_to_cpu(rl->rl_count), le16_to_cpu(rl->rl_used)); + le32_to_cpu(rl->rl_count), le32_to_cpu(rl->rl_used)); /* * XXX: Improvement later. @@ -2411,7 +2411,7 @@ static int ocfs2_calc_refcount_meta_credits(struct super_block *sb, rb = (struct ocfs2_refcount_block *) prev_bh->b_data; - if (le16_to_cpu(rb->rf_records.rl_used) + + if (le64_to_cpu(rb->rf_records.rl_used) + recs_add > le16_to_cpu(rb->rf_records.rl_count)) ref_blocks++; @@ -2476,7 +2476,7 @@ static int ocfs2_calc_refcount_meta_credits(struct super_block *sb, if (prev_bh) { rb = (struct ocfs2_refcount_block *)prev_bh->b_data; - if (le16_to_cpu(rb->rf_records.rl_used) + recs_add > + if (le64_to_cpu(rb->rf_records.rl_used) + recs_add > le16_to_cpu(rb->rf_records.rl_count)) ref_blocks++; @@ -3629,7 +3629,7 @@ int ocfs2_refcounted_xattr_delete_need(struct inode *inode, * one will split a refcount rec, so totally we need * clusters * 2 new refcount rec. */ - if (le16_to_cpu(rb->rf_records.rl_used) + clusters * 2 > + if (le64_to_cpu(rb->rf_records.rl_used) + clusters * 2 > le16_to_cpu(rb->rf_records.rl_count)) ref_blocks++; diff --git a/trunk/fs/ocfs2/suballoc.c b/trunk/fs/ocfs2/suballoc.c index f169da4624fd..ba5d97e4a73e 100644 --- a/trunk/fs/ocfs2/suballoc.c +++ b/trunk/fs/ocfs2/suballoc.c @@ -600,7 +600,7 @@ static void ocfs2_bg_alloc_cleanup(handle_t *handle, ret = ocfs2_free_clusters(handle, cluster_ac->ac_inode, cluster_ac->ac_bh, le64_to_cpu(rec->e_blkno), - le16_to_cpu(rec->e_leaf_clusters)); + le32_to_cpu(rec->e_leaf_clusters)); if (ret) mlog_errno(ret); /* Try all the clusters to free */ @@ -1628,7 +1628,7 @@ static int ocfs2_bg_discontig_fix_by_rec(struct ocfs2_suballoc_result *res, { unsigned int bpc = le16_to_cpu(cl->cl_bpc); unsigned int bitoff = le32_to_cpu(rec->e_cpos) * bpc; - unsigned int bitcount = le16_to_cpu(rec->e_leaf_clusters) * bpc; + unsigned int bitcount = le32_to_cpu(rec->e_leaf_clusters) * bpc; if (res->sr_bit_offset < bitoff) return 0; diff --git a/trunk/include/linux/clk-private.h b/trunk/include/linux/clk-private.h index eb3f84bc5325..5e4312b6f5cc 100644 --- a/trunk/include/linux/clk-private.h +++ b/trunk/include/linux/clk-private.h @@ -30,7 +30,7 @@ struct clk { const struct clk_ops *ops; struct clk_hw *hw; struct clk *parent; - const char **parent_names; + char **parent_names; struct clk **parents; u8 num_parents; unsigned long rate; @@ -55,22 +55,12 @@ struct clk { * alternative macro for static initialization */ -#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \ - _parents) \ - static struct clk _name = { \ - .name = #_name, \ - .ops = &_ops, \ - .hw = &_name##_hw.hw, \ - .parent_names = _parent_names, \ - .num_parents = ARRAY_SIZE(_parent_names), \ - .parents = _parents, \ - .flags = _flags, \ - } +extern struct clk_ops clk_fixed_rate_ops; #define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ _fixed_rate_flags) \ static struct clk _name; \ - static const char *_name##_parent_names[] = {}; \ + static char *_name##_parent_names[] = {}; \ static struct clk_fixed_rate _name##_hw = { \ .hw = { \ .clk = &_name, \ @@ -78,14 +68,23 @@ struct clk { .fixed_rate = _rate, \ .flags = _fixed_rate_flags, \ }; \ - DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \ - _name##_parent_names, NULL); + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_fixed_rate_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_gate_ops; #define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ _flags, _reg, _bit_idx, \ _gate_flags, _lock) \ static struct clk _name; \ - static const char *_name##_parent_names[] = { \ + static char *_name##_parent_names[] = { \ _parent_name, \ }; \ static struct clk *_name##_parents[] = { \ @@ -100,14 +99,24 @@ struct clk { .flags = _gate_flags, \ .lock = _lock, \ }; \ - DEFINE_CLK(_name, clk_gate_ops, _flags, \ - _name##_parent_names, _name##_parents); + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .parents = _name##_parents, \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_divider_ops; #define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ _flags, _reg, _shift, _width, \ _divider_flags, _lock) \ static struct clk _name; \ - static const char *_name##_parent_names[] = { \ + static char *_name##_parent_names[] = { \ _parent_name, \ }; \ static struct clk *_name##_parents[] = { \ @@ -123,8 +132,18 @@ struct clk { .flags = _divider_flags, \ .lock = _lock, \ }; \ - DEFINE_CLK(_name, clk_divider_ops, _flags, \ - _name##_parent_names, _name##_parents); + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_divider_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _name##_parent_names, \ + .num_parents = \ + ARRAY_SIZE(_name##_parent_names), \ + .parents = _name##_parents, \ + .flags = _flags, \ + }; + +extern struct clk_ops clk_mux_ops; #define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ _reg, _shift, _width, \ @@ -140,28 +159,16 @@ struct clk { .flags = _mux_flags, \ .lock = _lock, \ }; \ - DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \ - _parents); - -#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \ - _parent_ptr, _flags, \ - _mult, _div) \ - static struct clk _name; \ - static const char *_name##_parent_names[] = { \ - _parent_name, \ - }; \ - static struct clk *_name##_parents[] = { \ - _parent_ptr, \ - }; \ - static struct clk_fixed_factor _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .mult = _mult, \ - .div = _div, \ - }; \ - DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \ - _name##_parent_names, _name##_parents); + static struct clk _name = { \ + .name = #_name, \ + .ops = &clk_mux_ops, \ + .hw = &_name##_hw.hw, \ + .parent_names = _parent_names, \ + .num_parents = \ + ARRAY_SIZE(_parent_names), \ + .parents = _parents, \ + .flags = _flags, \ + }; /** * __clk_init - initialize the data structures in a struct clk @@ -182,12 +189,8 @@ struct clk { * * It is not necessary to call clk_register if __clk_init is used directly with * statically initialized clock data. - * - * Returns 0 on success, otherwise an error code. */ -int __clk_init(struct device *dev, struct clk *clk); - -struct clk *__clk_register(struct device *dev, struct clk_hw *hw); +void __clk_init(struct device *dev, struct clk *clk); #endif /* CONFIG_COMMON_CLK */ #endif /* CLK_PRIVATE_H */ diff --git a/trunk/include/linux/clk-provider.h b/trunk/include/linux/clk-provider.h index c1c23b9ec368..5508897ad376 100644 --- a/trunk/include/linux/clk-provider.h +++ b/trunk/include/linux/clk-provider.h @@ -15,6 +15,19 @@ #ifdef CONFIG_COMMON_CLK +/** + * struct clk_hw - handle for traversing from a struct clk to its corresponding + * hardware-specific structure. struct clk_hw should be declared within struct + * clk_foo and then referenced by the struct clk instance that uses struct + * clk_foo's clk_ops + * + * clk: pointer to the struct clk instance that points back to this struct + * clk_hw instance + */ +struct clk_hw { + struct clk *clk; +}; + /* * flags used across common struct clk. these flags should only affect the * top-level framework. custom flags for dealing with hardware specifics @@ -26,8 +39,6 @@ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ -struct clk_hw; - /** * struct clk_ops - Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers @@ -77,11 +88,19 @@ struct clk_hw; * array index into the value programmed into the hardware. * Returns 0 on success, -EERROR otherwise. * - * @set_rate: Change the rate of this clock. The requested rate is specified - * by the second argument, which should typically be the return - * of .round_rate call. The third argument gives the parent rate - * which is likely helpful for most .set_rate implementation. - * Returns 0 on success, -EERROR otherwise. + * @set_rate: Change the rate of this clock. If this callback returns + * CLK_SET_RATE_PARENT, the rate change will be propagated to the + * parent clock (which may propagate again if the parent clock + * also sets this flag). The requested rate of the parent is + * passed back from the callback in the second 'unsigned long *' + * argument. Note that it is up to the hardware clock's set_rate + * implementation to insure that clocks do not run out of spec + * when propgating the call to set_rate up to the parent. One way + * to do this is to gate the clock (via clk_disable and/or + * clk_unprepare) before calling clk_set_rate, then ungating it + * afterward. If your clock also has the CLK_GATE_SET_RATE flag + * set then this will insure safety. Returns 0 on success, + * -EERROR otherwise. * * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable @@ -106,46 +125,10 @@ struct clk_ops { unsigned long *); int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); - int (*set_rate)(struct clk_hw *hw, unsigned long, - unsigned long); + int (*set_rate)(struct clk_hw *hw, unsigned long); void (*init)(struct clk_hw *hw); }; -/** - * struct clk_init_data - holds init data that's common to all clocks and is - * shared between the clock provider and the common clock framework. - * - * @name: clock name - * @ops: operations this clock supports - * @parent_names: array of string names for all possible parents - * @num_parents: number of possible parents - * @flags: framework-level hints and quirks - */ -struct clk_init_data { - const char *name; - const struct clk_ops *ops; - const char **parent_names; - u8 num_parents; - unsigned long flags; -}; - -/** - * struct clk_hw - handle for traversing from a struct clk to its corresponding - * hardware-specific structure. struct clk_hw should be declared within struct - * clk_foo and then referenced by the struct clk instance that uses struct - * clk_foo's clk_ops - * - * @clk: pointer to the struct clk instance that points back to this struct - * clk_hw instance - * - * @init: pointer to struct clk_init_data that contains the init data shared - * with the common clock framework. - */ -struct clk_hw { - struct clk *clk; - struct clk_init_data *init; -}; - /* * DOC: Basic clock implementations common to many platforms * @@ -166,7 +149,6 @@ struct clk_fixed_rate { u8 flags; }; -extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); @@ -183,7 +165,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name, * Clock which can gate its output. Implements .enable & .disable * * Flags: - * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to + * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to * enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock */ @@ -193,11 +175,11 @@ struct clk_gate { u8 bit_idx; u8 flags; spinlock_t *lock; + char *parent[1]; }; #define CLK_GATE_SET_TO_DISABLE BIT(0) -extern const struct clk_ops clk_gate_ops; struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, @@ -230,12 +212,12 @@ struct clk_divider { u8 width; u8 flags; spinlock_t *lock; + char *parent[1]; }; #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) -extern const struct clk_ops clk_divider_ops; struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, @@ -256,7 +238,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name, * * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 - * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) + * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two) */ struct clk_mux { struct clk_hw hw; @@ -270,47 +252,29 @@ struct clk_mux { #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) -extern const struct clk_ops clk_mux_ops; struct clk *clk_register_mux(struct device *dev, const char *name, - const char **parent_names, u8 num_parents, unsigned long flags, + char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); -/** - * struct clk_fixed_factor - fixed multiplier and divider clock - * - * @hw: handle between common and hardware-specific interfaces - * @mult: multiplier - * @div: divider - * - * Clock with a fixed multiplier and divider. The output frequency is the - * parent clock rate divided by div and multiplied by mult. - * Implements .recalc_rate, .set_rate and .round_rate - */ - -struct clk_fixed_factor { - struct clk_hw hw; - unsigned int mult; - unsigned int div; -}; - -extern struct clk_ops clk_fixed_factor_ops; -struct clk *clk_register_fixed_factor(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, - unsigned int mult, unsigned int div); - /** * clk_register - allocate a new clock, register it and return an opaque cookie * @dev: device that is registering this clock + * @name: clock name + * @ops: operations this clock supports * @hw: link to hardware-specific clock data + * @parent_names: array of string names for all possible parents + * @num_parents: number of possible parents + * @flags: framework-level hints and quirks * * clk_register is the primary interface for populating the clock tree with new * clock nodes. It returns a pointer to the newly allocated struct clk which * cannot be dereferenced by driver code but may be used in conjuction with the - * rest of the clock API. In the event of an error clk_register will return an - * error code; drivers must test for an error code after calling clk_register. + * rest of the clock API. */ -struct clk *clk_register(struct device *dev, struct clk_hw *hw); +struct clk *clk_register(struct device *dev, const char *name, + const struct clk_ops *ops, struct clk_hw *hw, + char **parent_names, u8 num_parents, unsigned long flags); /* helper functions */ const char *__clk_get_name(struct clk *clk); diff --git a/trunk/include/linux/clk.h b/trunk/include/linux/clk.h index ad5c43e8ae8a..b0252726df61 100644 --- a/trunk/include/linux/clk.h +++ b/trunk/include/linux/clk.h @@ -81,7 +81,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb); int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); -#endif +#endif /* !CONFIG_COMMON_CLK */ /** * clk_get - lookup and obtain a reference to a clock producer. @@ -100,26 +100,6 @@ int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); */ struct clk *clk_get(struct device *dev, const char *id); -/** - * devm_clk_get - lookup and obtain a managed reference to a clock producer. - * @dev: device for clock "consumer" - * @id: clock comsumer ID - * - * Returns a struct clk corresponding to the clock producer, or - * valid IS_ERR() condition containing errno. The implementation - * uses @dev and @id to determine the clock consumer, and thereby - * the clock producer. (IOW, @id may be identical strings, but - * clk_get may return different clock producers depending on @dev.) - * - * Drivers must assume that the clock source is not enabled. - * - * devm_clk_get should not be called from within interrupt context. - * - * The clock will automatically be freed when the device is unbound - * from the bus. - */ -struct clk *devm_clk_get(struct device *dev, const char *id); - /** * clk_prepare - prepare a clock source * @clk: clock source @@ -226,18 +206,6 @@ unsigned long clk_get_rate(struct clk *clk); */ void clk_put(struct clk *clk); -/** - * devm_clk_put - "free" a managed clock source - * @dev: device used to acuqire the clock - * @clk: clock source acquired with devm_clk_get() - * - * Note: drivers must ensure that all clk_enable calls made on this - * clock source are balanced by clk_disable calls prior to calling - * this function. - * - * clk_put should not be called from within interrupt context. - */ -void devm_clk_put(struct device *dev, struct clk *clk); /* * The remaining APIs are optional for machine class support. @@ -252,7 +220,7 @@ void devm_clk_put(struct device *dev, struct clk *clk); * Returns rounded clock rate in Hz, or negative errno. */ long clk_round_rate(struct clk *clk, unsigned long rate); - + /** * clk_set_rate - set the clock rate for a clock source * @clk: clock source @@ -261,7 +229,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate); * Returns success (0) or negative errno. */ int clk_set_rate(struct clk *clk, unsigned long rate); - + /** * clk_set_parent - set the parent clock source for this clock * @clk: clock source diff --git a/trunk/include/linux/clkdev.h b/trunk/include/linux/clkdev.h index a6a6f603103b..d9a4fd028c9d 100644 --- a/trunk/include/linux/clkdev.h +++ b/trunk/include/linux/clkdev.h @@ -40,7 +40,4 @@ void clkdev_drop(struct clk_lookup *cl); void clkdev_add_table(struct clk_lookup *, size_t); int clk_add_alias(const char *, const char *, char *, struct device *); -int clk_register_clkdev(struct clk *, const char *, const char *, ...); -int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t); - #endif diff --git a/trunk/include/linux/fuse.h b/trunk/include/linux/fuse.h index 8f2ab8fef929..8ba2c9460b28 100644 --- a/trunk/include/linux/fuse.h +++ b/trunk/include/linux/fuse.h @@ -593,7 +593,7 @@ struct fuse_dirent { __u64 off; __u32 namelen; __u32 type; - char name[]; + char name[0]; }; #define FUSE_NAME_OFFSET offsetof(struct fuse_dirent, name) diff --git a/trunk/include/linux/i2c/twl.h b/trunk/include/linux/i2c/twl.h index 1f90de0cfdbe..2463b6100333 100644 --- a/trunk/include/linux/i2c/twl.h +++ b/trunk/include/linux/i2c/twl.h @@ -666,11 +666,23 @@ struct twl4030_codec_data { unsigned int check_defaults:1; unsigned int reset_registers:1; unsigned int hs_extmute:1; + u16 hs_left_step; + u16 hs_right_step; + u16 hf_left_step; + u16 hf_right_step; void (*set_hs_extmute)(int mute); }; struct twl4030_vibra_data { unsigned int coexist; + + /* twl6040 */ + unsigned int vibldrv_res; /* left driver resistance */ + unsigned int vibrdrv_res; /* right driver resistance */ + unsigned int viblmotor_res; /* left motor resistance */ + unsigned int vibrmotor_res; /* right motor resistance */ + int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */ + int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ }; struct twl4030_audio_data { diff --git a/trunk/include/linux/kvm_host.h b/trunk/include/linux/kvm_host.h index 72cbf08d45fb..665a260c7e09 100644 --- a/trunk/include/linux/kvm_host.h +++ b/trunk/include/linux/kvm_host.h @@ -596,7 +596,6 @@ void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id); #ifdef CONFIG_IOMMU_API int kvm_iommu_map_pages(struct kvm *kvm, struct kvm_memory_slot *slot); -void kvm_iommu_unmap_pages(struct kvm *kvm, struct kvm_memory_slot *slot); int kvm_iommu_map_guest(struct kvm *kvm); int kvm_iommu_unmap_guest(struct kvm *kvm); int kvm_assign_device(struct kvm *kvm, @@ -610,11 +609,6 @@ static inline int kvm_iommu_map_pages(struct kvm *kvm, return 0; } -static inline void kvm_iommu_unmap_pages(struct kvm *kvm, - struct kvm_memory_slot *slot) -{ -} - static inline int kvm_iommu_map_guest(struct kvm *kvm) { return -ENODEV; diff --git a/trunk/include/linux/mfd/db5500-prcmu.h b/trunk/include/linux/mfd/db5500-prcmu.h index 5a049dfaf153..9890687f582d 100644 --- a/trunk/include/linux/mfd/db5500-prcmu.h +++ b/trunk/include/linux/mfd/db5500-prcmu.h @@ -8,14 +8,41 @@ #ifndef __MFD_DB5500_PRCMU_H #define __MFD_DB5500_PRCMU_H -static inline int prcmu_resetout(u8 resoutn, u8 state) +#ifdef CONFIG_MFD_DB5500_PRCMU + +void db5500_prcmu_early_init(void); +int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state); +int db5500_prcmu_set_display_clocks(void); +int db5500_prcmu_disable_dsipll(void); +int db5500_prcmu_enable_dsipll(void); +int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); +int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +void db5500_prcmu_enable_wakeups(u32 wakeups); +int db5500_prcmu_request_clock(u8 clock, bool enable); +void db5500_prcmu_config_abb_event_readout(u32 abb_events); +void db5500_prcmu_get_abb_event_buffer(void __iomem **buf); +int prcmu_resetout(u8 resoutn, u8 state); +int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll); +int db5500_prcmu_config_esram0_deep_sleep(u8 state); +void db5500_prcmu_system_reset(u16 reset_code); +u16 db5500_prcmu_get_reset_code(void); +bool db5500_prcmu_is_ac_wake_requested(void); +int db5500_prcmu_set_arm_opp(u8 opp); +int db5500_prcmu_get_arm_opp(void); + +#else /* !CONFIG_UX500_SOC_DB5500 */ + +static inline void db5500_prcmu_early_init(void) {} + +static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) { - return 0; + return -ENOSYS; } -static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) +static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) { - return 0; + return -ENOSYS; } static inline int db5500_prcmu_request_clock(u8 clock, bool enable) @@ -23,83 +50,70 @@ static inline int db5500_prcmu_request_clock(u8 clock, bool enable) return 0; } -static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) +static inline int db5500_prcmu_set_display_clocks(void) { return 0; } -static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) +static inline int db5500_prcmu_disable_dsipll(void) { return 0; } -static inline u16 db5500_prcmu_get_reset_code(void) +static inline int db5500_prcmu_enable_dsipll(void) { return 0; } -static inline bool db5500_prcmu_is_ac_wake_requested(void) +static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) { return 0; } -static inline int db5500_prcmu_set_arm_opp(u8 opp) +static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} + +static inline int prcmu_resetout(u8 resoutn, u8 state) { return 0; } -static inline int db5500_prcmu_get_arm_opp(void) +static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) { return 0; } -static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {} - static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {} +static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {} -static inline void db5500_prcmu_system_reset(u16 reset_code) {} - -static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} - -#ifdef CONFIG_MFD_DB5500_PRCMU - -void db5500_prcmu_early_init(void); -int db5500_prcmu_set_display_clocks(void); -int db5500_prcmu_disable_dsipll(void); -int db5500_prcmu_enable_dsipll(void); -int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); -int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); - -#else /* !CONFIG_UX500_SOC_DB5500 */ - -static inline void db5500_prcmu_early_init(void) {} - -static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) +static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) { - return -ENOSYS; + return 0; } -static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) +static inline void db5500_prcmu_system_reset(u16 reset_code) {} + +static inline u16 db5500_prcmu_get_reset_code(void) { - return -ENOSYS; + return 0; } -static inline int db5500_prcmu_set_display_clocks(void) +static inline bool db5500_prcmu_is_ac_wake_requested(void) { return 0; } -static inline int db5500_prcmu_disable_dsipll(void) +static inline int db5500_prcmu_set_arm_opp(u8 opp) { return 0; } -static inline int db5500_prcmu_enable_dsipll(void) +static inline int db5500_prcmu_get_arm_opp(void) { return 0; } + #endif /* CONFIG_MFD_DB5500_PRCMU */ #endif /* __MFD_DB5500_PRCMU_H */ diff --git a/trunk/include/linux/mfd/rc5t583.h b/trunk/include/linux/mfd/rc5t583.h index 0b64b19d81ab..a2c61609d21d 100644 --- a/trunk/include/linux/mfd/rc5t583.h +++ b/trunk/include/linux/mfd/rc5t583.h @@ -26,7 +26,6 @@ #include #include -#include #define RC5T583_MAX_REGS 0xF8 @@ -280,44 +279,14 @@ struct rc5t583_platform_data { bool enable_shutdown; }; -static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_write(rc5t583->regmap, reg, val); -} - -static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - unsigned int ival; - int ret; - ret = regmap_read(rc5t583->regmap, reg, &ival); - if (!ret) - *val = (uint8_t)ival; - return ret; -} - -static inline int rc5t583_set_bits(struct device *dev, unsigned int reg, - unsigned int bit_mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask); -} - -static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg, - unsigned int bit_mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0); -} - -static inline int rc5t583_update(struct device *dev, unsigned int reg, - unsigned int val, unsigned int mask) -{ - struct rc5t583 *rc5t583 = dev_get_drvdata(dev); - return regmap_update_bits(rc5t583->regmap, reg, mask, val); -} - +int rc5t583_write(struct device *dev, u8 reg, uint8_t val); +int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val); +int rc5t583_set_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask); +int rc5t583_clear_bits(struct device *dev, unsigned int reg, + unsigned int bit_mask); +int rc5t583_update(struct device *dev, unsigned int reg, + unsigned int val, unsigned int mask); int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id, int ext_pwr_req, int deepsleep_slot_nr); int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base); diff --git a/trunk/include/linux/mfd/twl6040.h b/trunk/include/linux/mfd/twl6040.h index b15b5f03f5c4..9bc9ac651dad 100644 --- a/trunk/include/linux/mfd/twl6040.h +++ b/trunk/include/linux/mfd/twl6040.h @@ -174,35 +174,8 @@ #define TWL6040_SYSCLK_SEL_LPPLL 0 #define TWL6040_SYSCLK_SEL_HPPLL 1 -struct twl6040_codec_data { - u16 hs_left_step; - u16 hs_right_step; - u16 hf_left_step; - u16 hf_right_step; -}; - -struct twl6040_vibra_data { - unsigned int vibldrv_res; /* left driver resistance */ - unsigned int vibrdrv_res; /* right driver resistance */ - unsigned int viblmotor_res; /* left motor resistance */ - unsigned int vibrmotor_res; /* right motor resistance */ - int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */ - int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ -}; - -struct twl6040_platform_data { - int audpwron_gpio; /* audio power-on gpio */ - unsigned int irq_base; - - struct twl6040_codec_data *codec; - struct twl6040_vibra_data *vibra; -}; - -struct regmap; - struct twl6040 { struct device *dev; - struct regmap *regmap; struct mutex mutex; struct mutex io_mutex; struct mutex irq_mutex; diff --git a/trunk/include/linux/mm.h b/trunk/include/linux/mm.h index 74aa71bea1e4..d8738a464b94 100644 --- a/trunk/include/linux/mm.h +++ b/trunk/include/linux/mm.h @@ -1393,20 +1393,29 @@ extern int install_special_mapping(struct mm_struct *mm, extern unsigned long get_unmapped_area(struct file *, unsigned long, unsigned long, unsigned long, unsigned long); +extern unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, + unsigned long len, unsigned long prot, + unsigned long flag, unsigned long pgoff); extern unsigned long mmap_region(struct file *file, unsigned long addr, unsigned long len, unsigned long flags, vm_flags_t vm_flags, unsigned long pgoff); -extern unsigned long do_mmap(struct file *, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); + +static inline unsigned long do_mmap(struct file *file, unsigned long addr, + unsigned long len, unsigned long prot, + unsigned long flag, unsigned long offset) +{ + unsigned long ret = -EINVAL; + if ((offset + PAGE_ALIGN(len)) < offset) + goto out; + if (!(offset & ~PAGE_MASK)) + ret = do_mmap_pgoff(file, addr, len, prot, flag, offset >> PAGE_SHIFT); +out: + return ret; +} + extern int do_munmap(struct mm_struct *, unsigned long, size_t); -/* These take the mm semaphore themselves */ -extern unsigned long vm_brk(unsigned long, unsigned long); -extern int vm_munmap(unsigned long, size_t); -extern unsigned long vm_mmap(struct file *, unsigned long, - unsigned long, unsigned long, - unsigned long, unsigned long); +extern unsigned long do_brk(unsigned long, unsigned long); /* truncate.c */ extern void truncate_inode_pages(struct address_space *, loff_t); diff --git a/trunk/include/linux/mmc/card.h b/trunk/include/linux/mmc/card.h index 629b823f8836..01beae78f079 100644 --- a/trunk/include/linux/mmc/card.h +++ b/trunk/include/linux/mmc/card.h @@ -481,7 +481,7 @@ struct mmc_driver { struct device_driver drv; int (*probe)(struct mmc_card *); void (*remove)(struct mmc_card *); - int (*suspend)(struct mmc_card *); + int (*suspend)(struct mmc_card *, pm_message_t); int (*resume)(struct mmc_card *); }; diff --git a/trunk/include/linux/nfsd/Kbuild b/trunk/include/linux/nfsd/Kbuild index 5b7d84ac954a..b8d4001212b3 100644 --- a/trunk/include/linux/nfsd/Kbuild +++ b/trunk/include/linux/nfsd/Kbuild @@ -1,4 +1,3 @@ -header-y += cld.h header-y += debug.h header-y += export.h header-y += nfsfh.h diff --git a/trunk/include/linux/of.h b/trunk/include/linux/of.h index 2ec1083af7ff..fa7fb1d97458 100644 --- a/trunk/include/linux/of.h +++ b/trunk/include/linux/of.h @@ -193,17 +193,6 @@ extern struct device_node *of_get_next_child(const struct device_node *node, for (child = of_get_next_child(parent, NULL); child != NULL; \ child = of_get_next_child(parent, child)) -static inline int of_get_child_count(const struct device_node *np) -{ - struct device_node *child; - int num = 0; - - for_each_child_of_node(np, child) - num++; - - return num; -} - extern struct device_node *of_find_node_with_property( struct device_node *from, const char *prop_name); #define for_each_node_with_property(dn, prop_name) \ @@ -270,37 +259,6 @@ extern void of_detach_node(struct device_node *); #endif #define of_match_ptr(_ptr) (_ptr) - -/* - * struct property *prop; - * const __be32 *p; - * u32 u; - * - * of_property_for_each_u32(np, "propname", prop, p, u) - * printk("U32 value: %x\n", u); - */ -const __be32 *of_prop_next_u32(struct property *prop, const __be32 *cur, - u32 *pu); -#define of_property_for_each_u32(np, propname, prop, p, u) \ - for (prop = of_find_property(np, propname, NULL), \ - p = of_prop_next_u32(prop, NULL, &u); \ - p; \ - p = of_prop_next_u32(prop, p, &u)) - -/* - * struct property *prop; - * const char *s; - * - * of_property_for_each_string(np, "propname", prop, s) - * printk("String value: %s\n", s); - */ -const char *of_prop_next_string(struct property *prop, const char *cur); -#define of_property_for_each_string(np, propname, prop, s) \ - for (prop = of_find_property(np, propname, NULL), \ - s = of_prop_next_string(prop, NULL); \ - s; \ - s = of_prop_next_string(prop, s)) - #else /* CONFIG_OF */ static inline bool of_have_populated_dt(void) @@ -311,11 +269,6 @@ static inline bool of_have_populated_dt(void) #define for_each_child_of_node(parent, child) \ while (0) -static inline int of_get_child_count(const struct device_node *np) -{ - return 0; -} - static inline int of_device_is_compatible(const struct device_node *device, const char *name) { @@ -396,10 +349,6 @@ static inline int of_machine_is_compatible(const char *compat) #define of_match_ptr(_ptr) NULL #define of_match_node(_matches, _node) NULL -#define of_property_for_each_u32(np, propname, prop, p, u) \ - while (0) -#define of_property_for_each_string(np, propname, prop, s) \ - while (0) #endif /* CONFIG_OF */ /** diff --git a/trunk/include/linux/pinctrl/consumer.h b/trunk/include/linux/pinctrl/consumer.h index 6dd96fb45482..191e72688481 100644 --- a/trunk/include/linux/pinctrl/consumer.h +++ b/trunk/include/linux/pinctrl/consumer.h @@ -36,9 +36,6 @@ extern struct pinctrl_state * __must_check pinctrl_lookup_state( const char *name); extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s); -extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev); -extern void devm_pinctrl_put(struct pinctrl *p); - #else /* !CONFIG_PINCTRL */ static inline int pinctrl_request_gpio(unsigned gpio) @@ -82,15 +79,6 @@ static inline int pinctrl_select_state(struct pinctrl *p, return 0; } -static inline struct pinctrl * __must_check devm_pinctrl_get(struct device *dev) -{ - return NULL; -} - -static inline void devm_pinctrl_put(struct pinctrl *p) -{ -} - #endif /* CONFIG_PINCTRL */ static inline struct pinctrl * __must_check pinctrl_get_select( @@ -125,38 +113,6 @@ static inline struct pinctrl * __must_check pinctrl_get_select_default( return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } -static inline struct pinctrl * __must_check devm_pinctrl_get_select( - struct device *dev, const char *name) -{ - struct pinctrl *p; - struct pinctrl_state *s; - int ret; - - p = devm_pinctrl_get(dev); - if (IS_ERR(p)) - return p; - - s = pinctrl_lookup_state(p, name); - if (IS_ERR(s)) { - devm_pinctrl_put(p); - return ERR_PTR(PTR_ERR(s)); - } - - ret = pinctrl_select_state(p, s); - if (ret < 0) { - devm_pinctrl_put(p); - return ERR_PTR(ret); - } - - return p; -} - -static inline struct pinctrl * __must_check devm_pinctrl_get_select_default( - struct device *dev) -{ - return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); -} - #ifdef CONFIG_PINCONF extern int pin_config_get(const char *dev_name, const char *name, diff --git a/trunk/include/linux/pinctrl/machine.h b/trunk/include/linux/pinctrl/machine.h index 7d22ab00343f..fee4349364f7 100644 --- a/trunk/include/linux/pinctrl/machine.h +++ b/trunk/include/linux/pinctrl/machine.h @@ -12,8 +12,6 @@ #ifndef __LINUX_PINCTRL_MACHINE_H #define __LINUX_PINCTRL_MACHINE_H -#include - #include "pinctrl-state.h" enum pinctrl_map_type { @@ -150,11 +148,11 @@ struct pinctrl_map { #define PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(dev, grp, cfgs) \ PIN_MAP_CONFIGS_GROUP(dev, PINCTRL_STATE_DEFAULT, dev, grp, cfgs) -#ifdef CONFIG_PINCTRL +#ifdef CONFIG_PINMUX extern int pinctrl_register_mappings(struct pinctrl_map const *map, unsigned num_maps); -extern void pinctrl_provide_dummies(void); + #else static inline int pinctrl_register_mappings(struct pinctrl_map const *map, @@ -163,8 +161,5 @@ static inline int pinctrl_register_mappings(struct pinctrl_map const *map, return 0; } -static inline void pinctrl_provide_dummies(void) -{ -} -#endif /* !CONFIG_PINCTRL */ +#endif /* !CONFIG_PINMUX */ #endif diff --git a/trunk/include/linux/pinctrl/pinconf.h b/trunk/include/linux/pinctrl/pinconf.h index e7a720104a47..ec431f03362d 100644 --- a/trunk/include/linux/pinctrl/pinconf.h +++ b/trunk/include/linux/pinctrl/pinconf.h @@ -25,6 +25,7 @@ struct seq_file; * @pin_config_get: get the config of a certain pin, if the requested config * is not available on this controller this should return -ENOTSUPP * and if it is available but disabled it should return -EINVAL + * @pin_config_get: get the config of a certain pin * @pin_config_set: configure an individual pin * @pin_config_group_get: get configurations for an entire pin group * @pin_config_group_set: configure all pins in a group @@ -32,8 +33,6 @@ struct seq_file; * per-device info for a certain pin in debugfs * @pin_config_group_dbg_show: optional debugfs display hook that will provide * per-device info for a certain group in debugfs - * @pin_config_config_dbg_show: optional debugfs display hook that will decode - * and display a driver's pin configuration parameter */ struct pinconf_ops { #ifdef CONFIG_GENERIC_PINCONF @@ -57,9 +56,6 @@ struct pinconf_ops { void (*pin_config_group_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, unsigned selector); - void (*pin_config_config_dbg_show) (struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned long config); }; #endif diff --git a/trunk/include/linux/pinctrl/pinctrl.h b/trunk/include/linux/pinctrl/pinctrl.h index 3b894a668d32..4e9f0788c221 100644 --- a/trunk/include/linux/pinctrl/pinctrl.h +++ b/trunk/include/linux/pinctrl/pinctrl.h @@ -21,11 +21,9 @@ struct device; struct pinctrl_dev; -struct pinctrl_map; struct pinmux_ops; struct pinconf_ops; struct gpio_chip; -struct device_node; /** * struct pinctrl_pin_desc - boards/machines provide information on their @@ -66,24 +64,17 @@ struct pinctrl_gpio_range { /** * struct pinctrl_ops - global pin control operations, to be implemented by * pin controller drivers. - * @get_groups_count: Returns the count of total number of groups registered. + * @list_groups: list the number of selectable named groups available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate the groups * @get_group_name: return the group name of the pin group * @get_group_pins: return an array of pins corresponding to a certain * group selector @pins, and the size of the array in @num_pins * @pin_dbg_show: optional debugfs display hook that will provide per-device * info for a certain pin in debugfs - * @dt_node_to_map: parse a device tree "pin configuration node", and create - * mapping table entries for it. These are returned through the @map and - * @num_maps output parameters. This function is optional, and may be - * omitted for pinctrl drivers that do not support device tree. - * @dt_free_map: free mapping table entries created via @dt_node_to_map. The - * top-level @map pointer must be freed, along with any dynamically - * allocated members of the mapping table entries themselves. This - * function is optional, and may be omitted for pinctrl drivers that do - * not support device tree. */ struct pinctrl_ops { - int (*get_groups_count) (struct pinctrl_dev *pctldev); + int (*list_groups) (struct pinctrl_dev *pctldev, unsigned selector); const char *(*get_group_name) (struct pinctrl_dev *pctldev, unsigned selector); int (*get_group_pins) (struct pinctrl_dev *pctldev, @@ -92,11 +83,6 @@ struct pinctrl_ops { unsigned *num_pins); void (*pin_dbg_show) (struct pinctrl_dev *pctldev, struct seq_file *s, unsigned offset); - int (*dt_node_to_map) (struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps); - void (*dt_free_map) (struct pinctrl_dev *pctldev, - struct pinctrl_map *map, unsigned num_maps); }; /** diff --git a/trunk/include/linux/pinctrl/pinmux.h b/trunk/include/linux/pinctrl/pinmux.h index 1818dcbdd9ab..47e9237edd47 100644 --- a/trunk/include/linux/pinctrl/pinmux.h +++ b/trunk/include/linux/pinctrl/pinmux.h @@ -23,14 +23,15 @@ struct pinctrl_dev; /** * struct pinmux_ops - pinmux operations, to be implemented by pin controller * drivers that support pinmuxing - * @request: called by the core to see if a certain pin can be made + * @request: called by the core to see if a certain pin can be made available * available for muxing. This is called by the core to acquire the pins * before selecting any actual mux setting across a function. The driver * is allowed to answer "no" by returning a negative error code * @free: the reverse function of the request() callback, frees a pin after * being requested - * @get_functions_count: returns number of selectable named functions available - * in this pinmux driver + * @list_functions: list the number of selectable named functions available + * in this pinmux driver, the core will begin on 0 and call this + * repeatedly as long as it returns >= 0 to enumerate mux settings * @get_function_name: return the function name of the muxing selector, * called by the core to figure out which mux setting it shall map a * certain device to @@ -61,7 +62,7 @@ struct pinctrl_dev; struct pinmux_ops { int (*request) (struct pinctrl_dev *pctldev, unsigned offset); int (*free) (struct pinctrl_dev *pctldev, unsigned offset); - int (*get_functions_count) (struct pinctrl_dev *pctldev); + int (*list_functions) (struct pinctrl_dev *pctldev, unsigned selector); const char *(*get_function_name) (struct pinctrl_dev *pctldev, unsigned selector); int (*get_function_groups) (struct pinctrl_dev *pctldev, diff --git a/trunk/include/linux/usb/otg.h b/trunk/include/linux/usb/otg.h index 38ab3f46346f..f67810f8f21b 100644 --- a/trunk/include/linux/usb/otg.h +++ b/trunk/include/linux/usb/otg.h @@ -94,7 +94,6 @@ struct usb_phy { struct usb_otg *otg; - struct device *io_dev; struct usb_phy_io_ops *io_ops; void __iomem *io_priv; diff --git a/trunk/lib/mpi/mpi-bit.c b/trunk/lib/mpi/mpi-bit.c index 0c505361da19..2f526627e4f5 100644 --- a/trunk/lib/mpi/mpi-bit.c +++ b/trunk/lib/mpi/mpi-bit.c @@ -177,8 +177,8 @@ int mpi_rshift(MPI x, MPI a, unsigned n) */ int mpi_lshift_limbs(MPI a, unsigned int count) { - const int n = a->nlimbs; - mpi_ptr_t ap; + mpi_ptr_t ap = a->d; + int n = a->nlimbs; int i; if (!count || !n) @@ -187,7 +187,6 @@ int mpi_lshift_limbs(MPI a, unsigned int count) if (RESIZE_IF_NEEDED(a, n + count) < 0) return -ENOMEM; - ap = a->d; for (i = n - 1; i >= 0; i--) ap[i + count] = ap[i]; for (i = 0; i < count; i++) diff --git a/trunk/mm/memblock.c b/trunk/mm/memblock.c index a44eab3157f8..99f285599501 100644 --- a/trunk/mm/memblock.c +++ b/trunk/mm/memblock.c @@ -330,9 +330,6 @@ static int __init_memblock memblock_add_region(struct memblock_type *type, phys_addr_t end = base + memblock_cap_size(base, &size); int i, nr_new; - if (!size) - return 0; - /* special case for empty array */ if (type->regions[0].size == 0) { WARN_ON(type->cnt != 1 || type->total_size); @@ -433,9 +430,6 @@ static int __init_memblock memblock_isolate_range(struct memblock_type *type, *start_rgn = *end_rgn = 0; - if (!size) - return 0; - /* we'll create at most two more regions */ while (type->cnt + 2 > type->max) if (memblock_double_array(type) < 0) @@ -520,6 +514,7 @@ int __init_memblock memblock_reserve(phys_addr_t base, phys_addr_t size) (unsigned long long)base, (unsigned long long)base + size, (void *)_RET_IP_); + BUG_ON(0 == size); return memblock_add_region(_rgn, base, size, MAX_NUMNODES); } diff --git a/trunk/mm/memcontrol.c b/trunk/mm/memcontrol.c index b868def9bcc1..a7165a60d0a7 100644 --- a/trunk/mm/memcontrol.c +++ b/trunk/mm/memcontrol.c @@ -3392,7 +3392,6 @@ void mem_cgroup_replace_page_cache(struct page *oldpage, * the newpage may be on LRU(or pagevec for LRU) already. We lock * LRU while we overwrite pc->mem_cgroup. */ - pc = lookup_page_cgroup(newpage); __mem_cgroup_commit_charge(memcg, newpage, 1, pc, type, true); } diff --git a/trunk/mm/mmap.c b/trunk/mm/mmap.c index 848ef52d9603..a7bf6a31c9f6 100644 --- a/trunk/mm/mmap.c +++ b/trunk/mm/mmap.c @@ -240,8 +240,6 @@ static struct vm_area_struct *remove_vma(struct vm_area_struct *vma) return next; } -static unsigned long do_brk(unsigned long addr, unsigned long len); - SYSCALL_DEFINE1(brk, unsigned long, brk) { unsigned long rlim, retval; @@ -953,7 +951,7 @@ static inline unsigned long round_hint_to_min(unsigned long hint) * The caller must hold down_write(¤t->mm->mmap_sem). */ -static unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, +unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, unsigned long pgoff) { @@ -1089,32 +1087,7 @@ static unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, return mmap_region(file, addr, len, flags, vm_flags, pgoff); } - -unsigned long do_mmap(struct file *file, unsigned long addr, - unsigned long len, unsigned long prot, - unsigned long flag, unsigned long offset) -{ - if (unlikely(offset + PAGE_ALIGN(len) < offset)) - return -EINVAL; - if (unlikely(offset & ~PAGE_MASK)) - return -EINVAL; - return do_mmap_pgoff(file, addr, len, prot, flag, offset >> PAGE_SHIFT); -} -EXPORT_SYMBOL(do_mmap); - -unsigned long vm_mmap(struct file *file, unsigned long addr, - unsigned long len, unsigned long prot, - unsigned long flag, unsigned long offset) -{ - unsigned long ret; - struct mm_struct *mm = current->mm; - - down_write(&mm->mmap_sem); - ret = do_mmap(file, addr, len, prot, flag, offset); - up_write(&mm->mmap_sem); - return ret; -} -EXPORT_SYMBOL(vm_mmap); +EXPORT_SYMBOL(do_mmap_pgoff); SYSCALL_DEFINE6(mmap_pgoff, unsigned long, addr, unsigned long, len, unsigned long, prot, unsigned long, flags, @@ -2132,25 +2105,21 @@ int do_munmap(struct mm_struct *mm, unsigned long start, size_t len) return 0; } + EXPORT_SYMBOL(do_munmap); -int vm_munmap(unsigned long start, size_t len) +SYSCALL_DEFINE2(munmap, unsigned long, addr, size_t, len) { int ret; struct mm_struct *mm = current->mm; + profile_munmap(addr); + down_write(&mm->mmap_sem); - ret = do_munmap(mm, start, len); + ret = do_munmap(mm, addr, len); up_write(&mm->mmap_sem); return ret; } -EXPORT_SYMBOL(vm_munmap); - -SYSCALL_DEFINE2(munmap, unsigned long, addr, size_t, len) -{ - profile_munmap(addr); - return vm_munmap(addr, len); -} static inline void verify_mm_writelocked(struct mm_struct *mm) { @@ -2167,7 +2136,7 @@ static inline void verify_mm_writelocked(struct mm_struct *mm) * anonymous maps. eventually we may be able to do some * brk-specific accounting here. */ -static unsigned long do_brk(unsigned long addr, unsigned long len) +unsigned long do_brk(unsigned long addr, unsigned long len) { struct mm_struct * mm = current->mm; struct vm_area_struct * vma, * prev; @@ -2263,17 +2232,7 @@ static unsigned long do_brk(unsigned long addr, unsigned long len) return addr; } -unsigned long vm_brk(unsigned long addr, unsigned long len) -{ - struct mm_struct *mm = current->mm; - unsigned long ret; - - down_write(&mm->mmap_sem); - ret = do_brk(addr, len); - up_write(&mm->mmap_sem); - return ret; -} -EXPORT_SYMBOL(vm_brk); +EXPORT_SYMBOL(do_brk); /* Release all mmaps. */ void exit_mmap(struct mm_struct *mm) diff --git a/trunk/mm/nommu.c b/trunk/mm/nommu.c index bb8f4f004a82..f59e170fceb4 100644 --- a/trunk/mm/nommu.c +++ b/trunk/mm/nommu.c @@ -1233,7 +1233,7 @@ static int do_mmap_private(struct vm_area_struct *vma, /* * handle mapping creation for uClinux */ -static unsigned long do_mmap_pgoff(struct file *file, +unsigned long do_mmap_pgoff(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, @@ -1470,32 +1470,7 @@ static unsigned long do_mmap_pgoff(struct file *file, show_free_areas(0); return -ENOMEM; } - -unsigned long do_mmap(struct file *file, unsigned long addr, - unsigned long len, unsigned long prot, - unsigned long flag, unsigned long offset) -{ - if (unlikely(offset + PAGE_ALIGN(len) < offset)) - return -EINVAL; - if (unlikely(offset & ~PAGE_MASK)) - return -EINVAL; - return do_mmap_pgoff(file, addr, len, prot, flag, offset >> PAGE_SHIFT); -} -EXPORT_SYMBOL(do_mmap); - -unsigned long vm_mmap(struct file *file, unsigned long addr, - unsigned long len, unsigned long prot, - unsigned long flag, unsigned long offset) -{ - unsigned long ret; - struct mm_struct *mm = current->mm; - - down_write(&mm->mmap_sem); - ret = do_mmap(file, addr, len, prot, flag, offset); - up_write(&mm->mmap_sem); - return ret; -} -EXPORT_SYMBOL(vm_mmap); +EXPORT_SYMBOL(do_mmap_pgoff); SYSCALL_DEFINE6(mmap_pgoff, unsigned long, addr, unsigned long, len, unsigned long, prot, unsigned long, flags, @@ -1734,22 +1709,16 @@ int do_munmap(struct mm_struct *mm, unsigned long start, size_t len) } EXPORT_SYMBOL(do_munmap); -int vm_munmap(unsigned long addr, size_t len) +SYSCALL_DEFINE2(munmap, unsigned long, addr, size_t, len) { - struct mm_struct *mm = current->mm; int ret; + struct mm_struct *mm = current->mm; down_write(&mm->mmap_sem); ret = do_munmap(mm, addr, len); up_write(&mm->mmap_sem); return ret; } -EXPORT_SYMBOL(vm_munmap); - -SYSCALL_DEFINE2(munmap, unsigned long, addr, size_t, len) -{ - return vm_munmap(addr, len); -} /* * release all the mappings made in a process's VM space @@ -1775,7 +1744,7 @@ void exit_mmap(struct mm_struct *mm) kleave(""); } -unsigned long vm_brk(unsigned long addr, unsigned long len) +unsigned long do_brk(unsigned long addr, unsigned long len) { return -ENOMEM; } diff --git a/trunk/scripts/checkpatch.pl b/trunk/scripts/checkpatch.pl index faea0ec612bf..de639eeeed50 100755 --- a/trunk/scripts/checkpatch.pl +++ b/trunk/scripts/checkpatch.pl @@ -1869,6 +1869,12 @@ sub process { "No space is necessary after a cast\n" . $hereprev); } + if ($rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $prevrawline =~ /^\+[ \t]*$/) { + CHK("BLOCK_COMMENT_STYLE", + "Don't begin block comments with only a /* line, use /* comment...\n" . $hereprev); + } + # check for spaces at the beginning of a line. # Exceptions: # 1) within comments diff --git a/trunk/scripts/xz_wrap.sh b/trunk/scripts/xz_wrap.sh index 7a2d372f4885..17a5798c29da 100644 --- a/trunk/scripts/xz_wrap.sh +++ b/trunk/scripts/xz_wrap.sh @@ -12,8 +12,8 @@ BCJ= LZMA2OPTS= -case $SRCARCH in - x86) BCJ=--x86 ;; +case $ARCH in + x86|x86_64) BCJ=--x86 ;; powerpc) BCJ=--powerpc ;; ia64) BCJ=--ia64; LZMA2OPTS=pb=4 ;; arm) BCJ=--arm ;; diff --git a/trunk/security/commoncap.c b/trunk/security/commoncap.c index 71a166a05975..0cf4b53480a7 100644 --- a/trunk/security/commoncap.c +++ b/trunk/security/commoncap.c @@ -29,7 +29,6 @@ #include #include #include -#include /* * If a non-root user executes a setuid-root binary in @@ -506,11 +505,6 @@ int cap_bprm_set_creds(struct linux_binprm *bprm) } skip: - /* if we have fs caps, clear dangerous personality flags */ - if (!cap_issubset(new->cap_permitted, old->cap_permitted)) - bprm->per_clear |= PER_CLEAR_ON_SETID; - - /* Don't let someone trace a set[ug]id/setpcap binary with the revised * credentials unless they have the appropriate permit */ diff --git a/trunk/security/smack/smack_lsm.c b/trunk/security/smack/smack_lsm.c index 45c32f074166..10056f2f6df3 100644 --- a/trunk/security/smack/smack_lsm.c +++ b/trunk/security/smack/smack_lsm.c @@ -3640,38 +3640,8 @@ struct security_operations smack_ops = { }; -static __init void init_smack_known_list(void) +static __init void init_smack_know_list(void) { - /* - * Initialize CIPSO locks - */ - spin_lock_init(&smack_known_huh.smk_cipsolock); - spin_lock_init(&smack_known_hat.smk_cipsolock); - spin_lock_init(&smack_known_star.smk_cipsolock); - spin_lock_init(&smack_known_floor.smk_cipsolock); - spin_lock_init(&smack_known_invalid.smk_cipsolock); - spin_lock_init(&smack_known_web.smk_cipsolock); - /* - * Initialize rule list locks - */ - mutex_init(&smack_known_huh.smk_rules_lock); - mutex_init(&smack_known_hat.smk_rules_lock); - mutex_init(&smack_known_floor.smk_rules_lock); - mutex_init(&smack_known_star.smk_rules_lock); - mutex_init(&smack_known_invalid.smk_rules_lock); - mutex_init(&smack_known_web.smk_rules_lock); - /* - * Initialize rule lists - */ - INIT_LIST_HEAD(&smack_known_huh.smk_rules); - INIT_LIST_HEAD(&smack_known_hat.smk_rules); - INIT_LIST_HEAD(&smack_known_star.smk_rules); - INIT_LIST_HEAD(&smack_known_floor.smk_rules); - INIT_LIST_HEAD(&smack_known_invalid.smk_rules); - INIT_LIST_HEAD(&smack_known_web.smk_rules); - /* - * Create the known labels list - */ list_add(&smack_known_huh.list, &smack_known_list); list_add(&smack_known_hat.list, &smack_known_list); list_add(&smack_known_star.list, &smack_known_list); @@ -3706,8 +3676,16 @@ static __init int smack_init(void) cred = (struct cred *) current->cred; cred->security = tsp; - /* initialize the smack_known_list */ - init_smack_known_list(); + /* initialize the smack_know_list */ + init_smack_know_list(); + /* + * Initialize locks + */ + spin_lock_init(&smack_known_huh.smk_cipsolock); + spin_lock_init(&smack_known_hat.smk_cipsolock); + spin_lock_init(&smack_known_star.smk_cipsolock); + spin_lock_init(&smack_known_floor.smk_cipsolock); + spin_lock_init(&smack_known_invalid.smk_cipsolock); /* * Register with LSM diff --git a/trunk/security/smack/smackfs.c b/trunk/security/smack/smackfs.c index 038811cb7e62..5c32f36ff706 100644 --- a/trunk/security/smack/smackfs.c +++ b/trunk/security/smack/smackfs.c @@ -1614,6 +1614,20 @@ static int __init init_smk_fs(void) smk_cipso_doi(); smk_unlbl_ambient(NULL); + mutex_init(&smack_known_floor.smk_rules_lock); + mutex_init(&smack_known_hat.smk_rules_lock); + mutex_init(&smack_known_huh.smk_rules_lock); + mutex_init(&smack_known_invalid.smk_rules_lock); + mutex_init(&smack_known_star.smk_rules_lock); + mutex_init(&smack_known_web.smk_rules_lock); + + INIT_LIST_HEAD(&smack_known_floor.smk_rules); + INIT_LIST_HEAD(&smack_known_hat.smk_rules); + INIT_LIST_HEAD(&smack_known_huh.smk_rules); + INIT_LIST_HEAD(&smack_known_invalid.smk_rules); + INIT_LIST_HEAD(&smack_known_star.smk_rules); + INIT_LIST_HEAD(&smack_known_web.smk_rules); + return err; } diff --git a/trunk/sound/core/vmaster.c b/trunk/sound/core/vmaster.c index 857586135d18..14a286a7bf2b 100644 --- a/trunk/sound/core/vmaster.c +++ b/trunk/sound/core/vmaster.c @@ -419,7 +419,6 @@ EXPORT_SYMBOL(snd_ctl_make_virtual_master); * snd_ctl_add_vmaster_hook - Add a hook to a vmaster control * @kcontrol: vmaster kctl element * @hook: the hook function - * @private_data: the private_data pointer to be saved * * Adds the given hook to the vmaster control element so that it's called * at each time when the value is changed. diff --git a/trunk/sound/last.c b/trunk/sound/last.c index 7ffc182e0844..bdd0857b8871 100644 --- a/trunk/sound/last.c +++ b/trunk/sound/last.c @@ -38,4 +38,4 @@ static int __init alsa_sound_last_init(void) return 0; } -late_initcall_sync(alsa_sound_last_init); +__initcall(alsa_sound_last_init); diff --git a/trunk/sound/pci/hda/patch_conexant.c b/trunk/sound/pci/hda/patch_conexant.c index d906c5b74cf0..a36488d94aaa 100644 --- a/trunk/sound/pci/hda/patch_conexant.c +++ b/trunk/sound/pci/hda/patch_conexant.c @@ -3971,14 +3971,9 @@ static void cx_auto_init_output(struct hda_codec *codec) int i; mute_outputs(codec, spec->multiout.num_dacs, spec->multiout.dac_nids); - for (i = 0; i < cfg->hp_outs; i++) { - unsigned int val = PIN_OUT; - if (snd_hda_query_pin_caps(codec, cfg->hp_pins[i]) & - AC_PINCAP_HP_DRV) - val |= AC_PINCTL_HP_EN; + for (i = 0; i < cfg->hp_outs; i++) snd_hda_codec_write(codec, cfg->hp_pins[i], 0, - AC_VERB_SET_PIN_WIDGET_CONTROL, val); - } + AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP); mute_outputs(codec, cfg->hp_outs, cfg->hp_pins); mute_outputs(codec, cfg->line_outs, cfg->line_out_pins); mute_outputs(codec, cfg->speaker_outs, cfg->speaker_pins); @@ -4396,10 +4391,8 @@ static void apply_pin_fixup(struct hda_codec *codec, enum { CXT_PINCFG_LENOVO_X200, - CXT_PINCFG_LENOVO_TP410, }; -/* ThinkPad X200 & co with cxt5051 */ static const struct cxt_pincfg cxt_pincfg_lenovo_x200[] = { { 0x16, 0x042140ff }, /* HP (seq# overridden) */ { 0x17, 0x21a11000 }, /* dock-mic */ @@ -4408,33 +4401,15 @@ static const struct cxt_pincfg cxt_pincfg_lenovo_x200[] = { {} }; -/* ThinkPad 410/420/510/520, X201 & co with cxt5066 */ -static const struct cxt_pincfg cxt_pincfg_lenovo_tp410[] = { - { 0x19, 0x042110ff }, /* HP (seq# overridden) */ - { 0x1a, 0x21a190f0 }, /* dock-mic */ - { 0x1c, 0x212140ff }, /* dock-HP */ - {} -}; - static const struct cxt_pincfg *cxt_pincfg_tbl[] = { [CXT_PINCFG_LENOVO_X200] = cxt_pincfg_lenovo_x200, - [CXT_PINCFG_LENOVO_TP410] = cxt_pincfg_lenovo_tp410, }; -static const struct snd_pci_quirk cxt5051_fixups[] = { +static const struct snd_pci_quirk cxt_fixups[] = { SND_PCI_QUIRK(0x17aa, 0x20f2, "Lenovo X200", CXT_PINCFG_LENOVO_X200), {} }; -static const struct snd_pci_quirk cxt5066_fixups[] = { - SND_PCI_QUIRK(0x17aa, 0x20f2, "Lenovo T400", CXT_PINCFG_LENOVO_TP410), - SND_PCI_QUIRK(0x17aa, 0x215e, "Lenovo T410", CXT_PINCFG_LENOVO_TP410), - SND_PCI_QUIRK(0x17aa, 0x215f, "Lenovo T510", CXT_PINCFG_LENOVO_TP410), - SND_PCI_QUIRK(0x17aa, 0x21ce, "Lenovo T420", CXT_PINCFG_LENOVO_TP410), - SND_PCI_QUIRK(0x17aa, 0x21cf, "Lenovo T520", CXT_PINCFG_LENOVO_TP410), - {} -}; - /* add "fake" mute amp-caps to DACs on cx5051 so that mixer mute switches * can be created (bko#42825) */ @@ -4471,13 +4446,13 @@ static int patch_conexant_auto(struct hda_codec *codec) case 0x14f15051: add_cx5051_fake_mutes(codec); codec->pin_amp_workaround = 1; - apply_pin_fixup(codec, cxt5051_fixups, cxt_pincfg_tbl); break; default: codec->pin_amp_workaround = 1; - apply_pin_fixup(codec, cxt5066_fixups, cxt_pincfg_tbl); } + apply_pin_fixup(codec, cxt_fixups, cxt_pincfg_tbl); + /* Show mute-led control only on HP laptops * This is a sort of white-list: on HP laptops, EAPD corresponds * only to the mute-LED without actualy amp function. Meanwhile, diff --git a/trunk/sound/pci/hda/patch_realtek.c b/trunk/sound/pci/hda/patch_realtek.c index e65e35433055..2508f8109f11 100644 --- a/trunk/sound/pci/hda/patch_realtek.c +++ b/trunk/sound/pci/hda/patch_realtek.c @@ -1445,13 +1445,6 @@ enum { ALC_FIXUP_ACT_BUILD, }; -static void alc_apply_pincfgs(struct hda_codec *codec, - const struct alc_pincfg *cfg) -{ - for (; cfg->nid; cfg++) - snd_hda_codec_set_pincfg(codec, cfg->nid, cfg->val); -} - static void alc_apply_fixup(struct hda_codec *codec, int action) { struct alc_spec *spec = codec->spec; @@ -1485,7 +1478,9 @@ static void alc_apply_fixup(struct hda_codec *codec, int action) snd_printdd(KERN_INFO "hda_codec: %s: " "Apply pincfg for %s\n", codec->chip_name, modelname); - alc_apply_pincfgs(codec, cfg); + for (; cfg->nid; cfg++) + snd_hda_codec_set_pincfg(codec, cfg->nid, + cfg->val); break; case ALC_FIXUP_VERBS: if (action != ALC_FIXUP_ACT_PROBE || !fix->v.verbs) @@ -4866,7 +4861,6 @@ enum { ALC260_FIXUP_GPIO1_TOGGLE, ALC260_FIXUP_REPLACER, ALC260_FIXUP_HP_B1900, - ALC260_FIXUP_KN1, }; static void alc260_gpio1_automute(struct hda_codec *codec) @@ -4894,36 +4888,6 @@ static void alc260_fixup_gpio1_toggle(struct hda_codec *codec, } } -static void alc260_fixup_kn1(struct hda_codec *codec, - const struct alc_fixup *fix, int action) -{ - struct alc_spec *spec = codec->spec; - static const struct alc_pincfg pincfgs[] = { - { 0x0f, 0x02214000 }, /* HP/speaker */ - { 0x12, 0x90a60160 }, /* int mic */ - { 0x13, 0x02a19000 }, /* ext mic */ - { 0x18, 0x01446000 }, /* SPDIF out */ - /* disable bogus I/O pins */ - { 0x10, 0x411111f0 }, - { 0x11, 0x411111f0 }, - { 0x14, 0x411111f0 }, - { 0x15, 0x411111f0 }, - { 0x16, 0x411111f0 }, - { 0x17, 0x411111f0 }, - { 0x19, 0x411111f0 }, - { } - }; - - switch (action) { - case ALC_FIXUP_ACT_PRE_PROBE: - alc_apply_pincfgs(codec, pincfgs); - break; - case ALC_FIXUP_ACT_PROBE: - spec->init_amp = ALC_INIT_NONE; - break; - } -} - static const struct alc_fixup alc260_fixups[] = { [ALC260_FIXUP_HP_DC5750] = { .type = ALC_FIXUP_PINS, @@ -4974,11 +4938,7 @@ static const struct alc_fixup alc260_fixups[] = { .v.func = alc260_fixup_gpio1_toggle, .chained = true, .chain_id = ALC260_FIXUP_COEF, - }, - [ALC260_FIXUP_KN1] = { - .type = ALC_FIXUP_FUNC, - .v.func = alc260_fixup_kn1, - }, + } }; static const struct snd_pci_quirk alc260_fixup_tbl[] = { @@ -4988,7 +4948,6 @@ static const struct snd_pci_quirk alc260_fixup_tbl[] = { SND_PCI_QUIRK(0x103c, 0x280a, "HP dc5750", ALC260_FIXUP_HP_DC5750), SND_PCI_QUIRK(0x103c, 0x30ba, "HP Presario B1900", ALC260_FIXUP_HP_B1900), SND_PCI_QUIRK(0x1509, 0x4540, "Favorit 100XS", ALC260_FIXUP_GPIO1), - SND_PCI_QUIRK(0x152d, 0x0729, "Quanta KN1", ALC260_FIXUP_KN1), SND_PCI_QUIRK(0x161f, 0x2057, "Replacer 672V", ALC260_FIXUP_REPLACER), SND_PCI_QUIRK(0x1631, 0xc017, "PB V7900", ALC260_FIXUP_COEF), {} diff --git a/trunk/sound/pci/hda/patch_sigmatel.c b/trunk/sound/pci/hda/patch_sigmatel.c index 4742cac26aa9..33a9946b492c 100644 --- a/trunk/sound/pci/hda/patch_sigmatel.c +++ b/trunk/sound/pci/hda/patch_sigmatel.c @@ -5063,11 +5063,12 @@ static void stac92xx_update_led_status(struct hda_codec *codec, int enabled) if (spec->gpio_led_polarity) muted = !muted; + /*polarity defines *not* muted state level*/ if (!spec->vref_mute_led_nid) { if (muted) - spec->gpio_data |= spec->gpio_led; + spec->gpio_data &= ~spec->gpio_led; /* orange */ else - spec->gpio_data &= ~spec->gpio_led; + spec->gpio_data |= spec->gpio_led; /* white */ stac_gpio_set(codec, spec->gpio_mask, spec->gpio_dir, spec->gpio_data); } else { diff --git a/trunk/sound/soc/codecs/Kconfig b/trunk/sound/soc/codecs/Kconfig index 59d8efaa17e9..6508e8b790bb 100644 --- a/trunk/sound/soc/codecs/Kconfig +++ b/trunk/sound/soc/codecs/Kconfig @@ -57,7 +57,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TPA6130A2 if I2C select SND_SOC_TLV320DAC33 if I2C select SND_SOC_TWL4030 if TWL4030_CORE - select SND_SOC_TWL6040 if TWL6040_CORE + select SND_SOC_TWL6040 if TWL4030_CORE select SND_SOC_UDA134X select SND_SOC_UDA1380 if I2C select SND_SOC_WL1273 if MFD_WL1273_CORE @@ -276,6 +276,7 @@ config SND_SOC_TWL4030 tristate config SND_SOC_TWL6040 + select TWL6040_CORE tristate config SND_SOC_UDA134X diff --git a/trunk/sound/soc/codecs/twl6040.c b/trunk/sound/soc/codecs/twl6040.c index dc7509b9d53a..2d8c6b825e57 100644 --- a/trunk/sound/soc/codecs/twl6040.c +++ b/trunk/sound/soc/codecs/twl6040.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -1527,7 +1528,7 @@ static int twl6040_resume(struct snd_soc_codec *codec) static int twl6040_probe(struct snd_soc_codec *codec) { struct twl6040_data *priv; - struct twl6040_codec_data *pdata = dev_get_platdata(codec->dev); + struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev); struct platform_device *pdev = container_of(codec->dev, struct platform_device, dev); int ret = 0; diff --git a/trunk/sound/soc/omap/Kconfig b/trunk/sound/soc/omap/Kconfig index deafbfaacdbf..e00dd0b1139c 100644 --- a/trunk/sound/soc/omap/Kconfig +++ b/trunk/sound/soc/omap/Kconfig @@ -97,7 +97,7 @@ config SND_OMAP_SOC_SDP3430 config SND_OMAP_SOC_OMAP_ABE_TWL6040 tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec" - depends on TWL6040_CORE && SND_OMAP_SOC && ARCH_OMAP4 + depends on TWL4030_CORE && SND_OMAP_SOC && ARCH_OMAP4 select SND_OMAP_SOC_DMIC select SND_OMAP_SOC_MCPDM select SND_SOC_TWL6040 diff --git a/trunk/tools/perf/.gitignore b/trunk/tools/perf/.gitignore index 26b823b61aa1..416684be0ad3 100644 --- a/trunk/tools/perf/.gitignore +++ b/trunk/tools/perf/.gitignore @@ -19,5 +19,3 @@ TAGS cscope* config.mak config.mak.autogen -*-bison.* -*-flex.* diff --git a/trunk/tools/perf/Makefile b/trunk/tools/perf/Makefile index 03059e75665a..820371f10d1b 100644 --- a/trunk/tools/perf/Makefile +++ b/trunk/tools/perf/Makefile @@ -237,20 +237,21 @@ export PERL_PATH FLEX = $(CROSS_COMPILE)flex BISON= $(CROSS_COMPILE)bison -$(OUTPUT)util/parse-events-flex.c: util/parse-events.l +event-parser: + $(QUIET_BISON)$(BISON) -v util/parse-events.y -d -o $(OUTPUT)util/parse-events-bison.c $(QUIET_FLEX)$(FLEX) --header-file=$(OUTPUT)util/parse-events-flex.h -t util/parse-events.l > $(OUTPUT)util/parse-events-flex.c -$(OUTPUT)util/parse-events-bison.c: util/parse-events.y - $(QUIET_BISON)$(BISON) -v util/parse-events.y -d -o $(OUTPUT)util/parse-events-bison.c +$(OUTPUT)util/parse-events-flex.c: event-parser +$(OUTPUT)util/parse-events-bison.c: event-parser -$(OUTPUT)util/pmu-flex.c: util/pmu.l +pmu-parser: + $(QUIET_BISON)$(BISON) -v util/pmu.y -d -o $(OUTPUT)util/pmu-bison.c $(QUIET_FLEX)$(FLEX) --header-file=$(OUTPUT)util/pmu-flex.h -t util/pmu.l > $(OUTPUT)util/pmu-flex.c -$(OUTPUT)util/pmu-bison.c: util/pmu.y - $(QUIET_BISON)$(BISON) -v util/pmu.y -d -o $(OUTPUT)util/pmu-bison.c +$(OUTPUT)util/pmu-flex.c: pmu-parser +$(OUTPUT)util/pmu-bison.c: pmu-parser -$(OUTPUT)util/parse-events.o: $(OUTPUT)util/parse-events-flex.c $(OUTPUT)util/parse-events-bison.c -$(OUTPUT)util/pmu.o: $(OUTPUT)util/pmu-flex.c $(OUTPUT)util/pmu-bison.c +$(OUTPUT)util/parse-events.o: event-parser pmu-parser LIB_FILE=$(OUTPUT)libperf.a @@ -526,7 +527,7 @@ else endif ifdef NO_GTK2 - BASIC_CFLAGS += -DNO_GTK2_SUPPORT + BASIC_CFLAGS += -DNO_GTK2 else FLAGS_GTK2=$(ALL_CFLAGS) $(ALL_LDFLAGS) $(EXTLIBS) $(shell pkg-config --libs --cflags gtk+-2.0) ifneq ($(call try-cc,$(SOURCE_GTK2),$(FLAGS_GTK2)),y) @@ -851,6 +852,8 @@ help: @echo ' html - make html documentation' @echo ' info - make GNU info documentation (access with info )' @echo ' pdf - make pdf documentation' + @echo ' event-parser - make event parser code' + @echo ' pmu-parser - make pmu format parser code' @echo ' TAGS - use etags to make tag information for source browsing' @echo ' tags - use ctags to make tag information for source browsing' @echo ' cscope - use cscope to make interactive browsing database' diff --git a/trunk/tools/perf/perf-archive.sh b/trunk/tools/perf/perf-archive.sh index 95b6f8b6177a..677e59d62a8d 100644 --- a/trunk/tools/perf/perf-archive.sh +++ b/trunk/tools/perf/perf-archive.sh @@ -29,14 +29,13 @@ if [ ! -s $BUILDIDS ] ; then fi MANIFEST=$(mktemp /tmp/perf-archive-manifest.XXXXXX) -PERF_BUILDID_LINKDIR=$(readlink -f $PERF_BUILDID_DIR)/ cut -d ' ' -f 1 $BUILDIDS | \ while read build_id ; do linkname=$PERF_BUILDID_DIR.build-id/${build_id:0:2}/${build_id:2} filename=$(readlink -f $linkname) echo ${linkname#$PERF_BUILDID_DIR} >> $MANIFEST - echo ${filename#$PERF_BUILDID_LINKDIR} >> $MANIFEST + echo ${filename#$PERF_BUILDID_DIR} >> $MANIFEST done tar cfj $PERF_DATA.tar.bz2 -C $PERF_BUILDID_DIR -T $MANIFEST diff --git a/trunk/tools/perf/util/session.c b/trunk/tools/perf/util/session.c index 1efd3bee6336..00923cda4d9c 100644 --- a/trunk/tools/perf/util/session.c +++ b/trunk/tools/perf/util/session.c @@ -876,11 +876,11 @@ static int perf_session_deliver_event(struct perf_session *session, dump_sample(session, event, sample); if (evsel == NULL) { ++session->hists.stats.nr_unknown_id; - return 0; + return -1; } if (machine == NULL) { ++session->hists.stats.nr_unprocessable_samples; - return 0; + return -1; } return tool->sample(tool, event, sample, evsel, machine); case PERF_RECORD_MMAP: diff --git a/trunk/virt/kvm/iommu.c b/trunk/virt/kvm/iommu.c index e9fff9830bf0..a457d2138f49 100644 --- a/trunk/virt/kvm/iommu.c +++ b/trunk/virt/kvm/iommu.c @@ -240,13 +240,9 @@ int kvm_iommu_map_guest(struct kvm *kvm) return -ENODEV; } - mutex_lock(&kvm->slots_lock); - kvm->arch.iommu_domain = iommu_domain_alloc(&pci_bus_type); - if (!kvm->arch.iommu_domain) { - r = -ENOMEM; - goto out_unlock; - } + if (!kvm->arch.iommu_domain) + return -ENOMEM; if (!allow_unsafe_assigned_interrupts && !iommu_domain_has_cap(kvm->arch.iommu_domain, @@ -257,16 +253,17 @@ int kvm_iommu_map_guest(struct kvm *kvm) " module option.\n", __func__); iommu_domain_free(kvm->arch.iommu_domain); kvm->arch.iommu_domain = NULL; - r = -EPERM; - goto out_unlock; + return -EPERM; } r = kvm_iommu_map_memslots(kvm); if (r) - kvm_iommu_unmap_memslots(kvm); + goto out_unmap; -out_unlock: - mutex_unlock(&kvm->slots_lock); + return 0; + +out_unmap: + kvm_iommu_unmap_memslots(kvm); return r; } @@ -313,11 +310,6 @@ static void kvm_iommu_put_pages(struct kvm *kvm, } } -void kvm_iommu_unmap_pages(struct kvm *kvm, struct kvm_memory_slot *slot) -{ - kvm_iommu_put_pages(kvm, slot->base_gfn, slot->npages); -} - static int kvm_iommu_unmap_memslots(struct kvm *kvm) { int idx; @@ -328,7 +320,7 @@ static int kvm_iommu_unmap_memslots(struct kvm *kvm) slots = kvm_memslots(kvm); kvm_for_each_memslot(memslot, slots) - kvm_iommu_unmap_pages(kvm, memslot); + kvm_iommu_put_pages(kvm, memslot->base_gfn, memslot->npages); srcu_read_unlock(&kvm->srcu, idx); @@ -343,11 +335,7 @@ int kvm_iommu_unmap_guest(struct kvm *kvm) if (!domain) return 0; - mutex_lock(&kvm->slots_lock); kvm_iommu_unmap_memslots(kvm); - kvm->arch.iommu_domain = NULL; - mutex_unlock(&kvm->slots_lock); - iommu_domain_free(domain); return 0; } diff --git a/trunk/virt/kvm/kvm_main.c b/trunk/virt/kvm/kvm_main.c index 9739b533ca2e..42b73930a6de 100644 --- a/trunk/virt/kvm/kvm_main.c +++ b/trunk/virt/kvm/kvm_main.c @@ -808,13 +808,12 @@ int __kvm_set_memory_region(struct kvm *kvm, if (r) goto out_free; - /* map/unmap the pages in iommu page table */ + /* map the pages in iommu page table */ if (npages) { r = kvm_iommu_map_pages(kvm, &new); if (r) goto out_free; - } else - kvm_iommu_unmap_pages(kvm, &old); + } r = -ENOMEM; slots = kmemdup(kvm->memslots, sizeof(struct kvm_memslots),